CN1499729A - High-speed, high precision D/A converter in structure of current rudder - Google Patents
High-speed, high precision D/A converter in structure of current rudder Download PDFInfo
- Publication number
- CN1499729A CN1499729A CNA021340242A CN02134024A CN1499729A CN 1499729 A CN1499729 A CN 1499729A CN A021340242 A CNA021340242 A CN A021340242A CN 02134024 A CN02134024 A CN 02134024A CN 1499729 A CN1499729 A CN 1499729A
- Authority
- CN
- China
- Prior art keywords
- matrix
- current source
- current
- module
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Analogue/Digital Conversion (AREA)
Abstract
The D/A converter possesses circuit for generating bias of current source, current source matrix, and high consistency digital input decoder etc five parts. The circuit for generating bias of current source and the current source matrix are connected to autocorrection module for current source matrices with different weights. The said autocorrection module can also connect to current source matrix directly, and data are output to register matrix. Internal correction module for current source matrix with same weight unit is connected to current source matrix and register matrix directly. With digital input being decoded, high consistency decoder outputs a matrix of control switch, which makes currents in current source matrix lead in differential two output branches. Differential current passes through module of converting current and voltage to be output in differential voltage mode.
Description
The present invention relates to integrated circuit and make the field.Particularly a kind of structure of current rudder digital to analog converter.
Present structure of current rudder digital to analog converter (DAC) designs, and has reached the precision of 14 bit 400MHz sampled clock signals.Its circuit block diagram comprises 4 parts as shown in Figure 1: current source offset generating circuit, input digit decoding circuit, electric current constitute to the current source matrix and the switch matrix of voltage conversion circuit and several segmentations.
The current source offset generating circuit produces bias voltage or electric current, and this biasing makes that the size of current between the current source cell of internal matrix is identical, and K integer power of the size between the current source cell electric current between the different matrix and 2 is linear.Wherein, integer K is that the bit of segmentation matrix is represented.As the current source number of MSB matrix is 32 (31) individual, and the unitary current size is I, and the current source number of inferior MSB matrix is 16 (15) individual, and then the size of current of unit current source is I/16 in time MSB matrix.
The input digit decoding circuit is exported the numeral that the numeral input is decoded as the thermometer pattern, and the numeric representation of 2 system numerals of the number of " 0 " or " 1 " and input is proportional in the output.2 system signals as input signal are B110, and 4*1+2*1+1*0=6 " 1 " data and 1 " 0 " data are then arranged in the output.
The current source matrix of segmentation and switch matrix are according to the output of decoding, electric current delivery node P or node N with each unit in the current source matrix, the switch that is output as " 1 " corresponding to decoding is with the electric current delivery node P of current source cell and be output as the switch of " 0 " corresponding to decoding, with the electric current delivery node N of current source cell.
The current conversion that electric current is collected node P and node N to voltage conversion circuit is voltage output.
The major defect of above circuit structure is:
Need special integrated circuit technology.The speed of digital signal is fast, and needing fast, technology supports; Simultaneously, current source cell is wanted precision-matched in the structure of current rudder, then needs the technology of high precision performance.
Need to add the consistency that postpones between each branch road in the delay cell assurance digital decoding circuit.
Units match in the current source matrix need be utilized physical location and special circuit structure to realize.
Owing to above reason, cause inside to contain the low and price height of the chip yield of High Speed and High Accuracy D C transducer, performance changes instability that causes system etc. along with the time.
Arriving along with the 3G radio communication epoch, the DAC performance that sending module in portable terminal and the base station is used will have strict requirement, in order to popularize the 3G wireless communication technology, must improve chip yield, reduce the stability of chip cost and raising chip performance.
Above shortcoming in view of prior art the objective of the invention is, and designs a kind of high-speed, high precision structure of current rudder digital to analog converter, makes it to overcome the above shortcoming of prior art.
The present invention realizes by the following method.
A kind of structure of current rudder high-speed, high precision D/A converter has current source offset generating circuit, current source matrix, high consistency numeral input decoding, can survey recoverable segmented current source matrix and switch matrix group, output current is to five parts of modular converter of voltage; The detection of current source cell error and correcting circuit comprise 3 modules: between register matrix, different weight current source matrix from dynamic(al) correction, with the inner school of weight unit current source matrix module; Between current source offset generating circuit and current source matrix and different weight current source matrixes automatically correction module is connected, and automatic correction module also can directly be connected with current source matrix between different weight current source matrix, data output to the register matrix; Be connected with the register matrix with current source matrix with the inner correction module of weight unit current source matrix: the numeral input is after decoding, high consistency decoder output control switch matrix, the electric current of current source matrix is imported the two-way output branch road of difference, difference current, is exported with the differential voltage pattern behind voltage transformation module through electric current.
Advantage of the present invention is significantly, and during operate as normal, the numeral input is after too high consistency decoding, and the delay that each decoding outputs between the input signal all is essentially identical; Simultaneously, because current source has all passed through from dynamic(al) correction, can As time goes on not degenerate, its matching precision is guaranteed, therefore, the structure of using among the present invention can realize the more high-precision digital-to-analogue conversion of more speed, is applicable to more small-scale segmentation matrix structure, can effectively dwindle area of chip.
Description of drawings is as follows.
Fig. 1: present structure of current rudder High Speed and High Accuracy D C schematic diagram
Fig. 2: improved DAC structural representation among the present invention
Fig. 3: the current source matrix internal element is from the dynamic(al) correction schematic diagram
Fig. 4: intersegmental current source matrix consistency is from the dynamic(al) correction schematic diagram
Fig. 5 a: the saw-toothed oscillator schematic diagram that frequency is directly proportional with electric current
Fig. 5 b: oscillator wave figure
Fig. 6: big current source matrix bias structure schematic diagram
Fig. 7 a: the triangular-wave generator that frequency is directly proportional with electric current
Fig. 7 b: oscillator wave mode schematic diagram
Fig. 8: current source matrix element circuit schematic diagram
Fig. 9 a:MidDecoder merge module schematic diagram
Fig. 9 b:MidDecoder schematic diagram
Fig. 9 c:5 bit thermometer mode decoder cell schematics
Fig. 9 d: mutation MidDecoder-1 schematic diagram
Fig. 9 e: mutation MidDecoder-2 schematic diagram
Figure 10: 4 bit MidDecoder schematic diagrames
Figure 11: the error schematic diagram of electric capacity charging and discharge
Figure 12: the relation table of reference clock signal stability and DAC upper limit precision.
Figure 13: the connection relational table of 13 outputs of the input of 5 bit decoder and MidDecoder.
Below in conjunction with drawings and Examples content of the present invention is described in further detail.
Be illustrated in figure 2 as improved DAC block diagram.Comprise 5 part current source offset generating circuits, high consistency input digit decoding circuit, electric current detection and correcting circuit to the current source matrix of voltage conversion circuit and several segmentations and switch matrix, current source cell error.
The detection of current source cell error and correcting circuit comprise 3 modules: between register matrix, different weight current source matrix from dynamic(al) correction, proofread and correct with the weight unit current source matrix is inner.Simultaneously, need carry out change in design to the current source cell of internal matrix to support zero offset capability.
Annexation is: between current source offset generating circuit and current source matrix and different weight current source matrixes automatically correction module be connected, and automatic correction module also can directly be connected with current source matrix between different weight current source matrixes, and data output to the register matrix; Be connected with the register matrix with current source matrix with the inner correction module of weight unit current source matrix: the numeral input is after decoding, high consistency decoder output control switch matrix, the electric current of current source matrix is imported the two-way output branch road of difference, difference current, is exported with the differential voltage pattern behind voltage transformation module through electric current.
Behind the chip power, at first carry out proofreading and correct, the data of carrying out the error correction needs that calculate are stored in the register matrix with digital form with the weight unit current source matrix is inner; Carry out then between different weight current source matrixes from dynamic(al) correction, the data of carrying out error correction and needing that calculate are stored in the register matrix with digital form; After automatic error correction finishes, with data in the register with accordingly between matrix and matrix current source cell be communicated with, obtain between internal matrix and matrix all current sources of precision-matched.
The current source matrix internal element is from the dynamic(al) correction schematic diagram as shown in Figure 3, annexation is: the address bus decoder is connected with current source cell and register matrix, the output current of current source cell connects Test Switchboard, one end of Test Switchboard connects into electric current the switch matrix of operate as normal, an other end is got involved oscillator with electric current, the output of oscillator connects adder and adder is output as the input of memory and logical operation, the output of memory and logical operation is connected register and many bit adder, and the final output of many bit adder is stored in the register and intermediate data directly is connected with current source matrix.Under normal mode of operation, the correcting current of each unit in the Data Control current source matrix in the register, being input as reference clock signal of adder 2 and be output as the input of memory and logical operation.
Each unit in the current source matrix is made of elementary current source Iu and a plurality of correcting currents source Iec, and the correcting current source is connected the back with correcting switch in parallel with the elementary current source.
Operation principle is: electrification reset, the elementary current source of each unit and correcting current source disconnect in the current source matrix, introduce each elementary current source in the oscillator one by one, in the identical time period that reference clock signal indicates, the pulse that oscillator sends is counted, and the result is stored in memory and the logical operation module.
Find out the maximum count result of memory and logical operation module stored.
With the count results of unit 1 in maximum data and the matrix relatively,, then utilize the address bus decoder to open register if data are identical, with complete 0 storage on the registers group of appropriate address; If the count results of unit 1 is littler than maximum data, then many bit adder are added 1, correcting current unit in the Control current source matrix unit 1, the single-bit correction electric current of wherein minimal weight is in parallel with the elementary current source, Test Switchboard 1 is opened, electric current is imported oscillator, in the time period that reference clock signal indicates, recomputate the number of the pulse that oscillator sends.
Whether newer count results is identical with maximum data, if data are identical, then utilize the address bus decoder to open register, with the storage on many bit adder on the registers group of appropriate address: otherwise, many bit adder are added 1, newly once count computing, within or error identical with maximum data requiring until the result of counting, with many bit adder storage at this moment on registers group.
In above correction, utilize subtraction also can carry out.
The types of long, the oscillator of the precision of proofreading and correct and the stability of reference clock signal and adder 1 etc. are relevant.
The position of setting adder 1 is long to be 14 bits, and count results and maximum data differ 1 bit, and then the matching error of current source is;
Current-source matching error=1/16384 of the long decision in position of adder 1
The stability of reference clock signal and the relation of matching precision are shown in Figure 12 table.
The relation of the type of oscillator and Current-source matching precision is discussed in the back.
Intersegmental as shown in Figure 4 current source matrix consistency is from the dynamic(al) correction schematic diagram, annexation is: the output current of a unit of current source matrix 1 connects Test Switchboard, one end of Test Switchboard connects into electric current the switch matrix of operate as normal, an other end is got involved oscillator with electric current, the output of oscillator connects adder and adder is output as the input of memory and logical operation, the output of memory and logical operation is connected register and many bit adder, and the final output of many bit adder is stored in the register and intermediate data directly is connected with current source matrix.Under normal mode of operation, the correcting current of each unit in the Data Control current source matrix in the register, being input as reference clock signal of adder 2 and be output as the input of memory and logical operation.
Setover as the current source of segmentation N1 matrix behind unit current source I1_D process K:1 in the segmentation 1 and twice current mirror of N:1.Unit in the matrix of correcting current source is connected with switch successively, is connected with the biasing of K:1 image electric current after the end parallel connection of switch, is connected with the biasing of N:1 image electric current after the other end parallel connection.
Operation principle is:
Electrification reset, introduce in the oscillator in the correction after-current source of a unit in segmentation 1 current source matrix, in the identical time period that reference clock signal indicates, the pulse that oscillator sends is counted, DS1 is stored in memory and the logical operation module as a result.Introduce in the oscillator in the correction after-current source of a unit in the segmentation N1 current source matrix, in the identical time period that reference clock signal indicates, the pulse that oscillator sends is counted, and DSN1 is stored in memory and the logical operation module as a result.
The result of twice counting relatively, check data DS1 whether be DSN1 K*N doubly.For example, the matrix of N1 segmentation is 5 bits, 32 matrixes, then K*N=32.If DS1 is K*N times of DSN1, then data " 0 " are stored on the appropriate address of register; Otherwise, according to following step adjustment.
If DS1 is greater than K*N DSN1 doubly, the current source matrix cell current that segmentation 1 is described is bigger than what expect, then many bit adder are added 1, make the electric current of a unit in the matrix of correcting current source enter the K:1 mirror image, then the correction after-current source of a unit in the segmentation N1 current source matrix is introduced in the oscillator, in the identical time period that reference clock signal indicates, the pulse that oscillator sends is counted, DSN1 is stored in memory and the logical operation module as a result.If DS1 is less than K*N DSN1 doubly, the current source matrix cell current that segmentation 1 is described is littler than what expect, then many bit adder are subtracted 1, make the electric current of a unit in the matrix of correcting current source enter the N:1 mirror image, then the correction after-current source of a unit in the segmentation N1 current source matrix is introduced in the oscillator, in the identical time period that reference clock signal indicates, the pulse that oscillator sends is counted, DSN1 is stored in memory and the logical operation module as a result.
Check once more data DS1 whether be DSN1 K*N doubly.If DS1 be DSN1 K*N doubly, then will this moment the storage of adder on the appropriate address of register: otherwise, continue to adjust according to above-mentioned steps until meeting the demands.
Above-mentioned current source correction matrix also can adopt the heavy structure of mixing of current source and electric current, and like this, adjustment can all concentrate on K:1 current mirror branch road or N:1 mirror image branch.
Be illustrated in figure 5 as the saw-toothed oscillator schematic diagram that frequency is directly proportional with size of current.Annexation is: current source I1 is through after the switch SW 1, electric current is inserted direct current node or electric capacity respectively, voltage on the electric capacity inserts back the positive input terminal of comparator between the dead zone and the negative input end of comparator connects reference voltage, the output of comparator through two inverters after, respectively output pulse waveform OUTB and OUT, switch SW 1 is subjected to OUTB and OUT control and switch SW 2 is controlled by OUT.
Operation principle is: behind the electrification reset, the voltage on the electric capacity is " 0 ", at this moment, OUTB=1 and OUT=0, switch SW 1 inserts electric capacity to the electric capacity charging and switch SW 2 disconnects with current source I1; Cross back the upper threshold value of comparator between the dead zone when voltage on the electric capacity after, the comparator output switching activity, OUTB=0 and OUT=1, at this moment, switch SW 1 disconnects and switch SW 2 conductings, and electric capacity begins discharge, after voltage on the electric capacity is crossed back lower limit between the dead zone, comparator upset, OUTB=1 and OUT=0, thus begin a new charge cycle.
Waveform on the electric capacity such as Fig. 5 b are depicted as sawtooth waveforms and OUT is an impulse waveform.According to C*dV/dt=I, Tch=C*dV/I, and Tdis is relevant with other factors, as the speed of device, the size of electric capacity etc.
Under following two kinds of situations, do not consider the influence of Tdis:
Tdis is infinitely close to 0
In any twice counting, the influence of Tdis is identical.
In actual applications, 2 all can't be satisfied more than.
Setting the Tdis minimum is 100ns, and the maximum matching error in any twice counting is 10%, and comparator returns and is 1V between the dead zone, and the charging current size is 80uA, and the precision prescribed of DAC is 14 bits.
The unmatched influence of discharging is:
Tdis*10％/(Tdis+Tch)＜1/(2*16384)
Tdis＜＜Tch
Then, Tdis*10%/Tch＜1/ (2*16384)
Tch＞32768*10ns＝0.33ms
And Tch=C*dV/I
C＝Tch*I/dV＝0.33ms*80uA/1V＝0.33nF
Electric capacity is too big, can't finish zero offset capability at chip internal.The method that reduces capacitance size is:
(1) improves the matching degree of discharge time in twice counting
(2) increase between time dead zone of comparator
(3) size of reduction current source current
Preceding two kinds of methods are subjected to the restriction of conditions such as technology, power supply, and the third method is desirable.The prerequisite that reduces the current source current size is: only in the size of test and calibration phase reduction electric current, recover original size of current when operate as normal; Little electric current is linear with big electric current, can expand to current state pro rata to the correction of little electric current.
Be illustrated in figure 6 as big current source matrix bias structure schematic diagram.Annexation is: transistor M1, M2, M3, M4, M5, the source electrode of M8 connects power supply, M1, M2, the grid of M3 is connected with node Iin1 with the drain electrode of M1, M5, M6, the grid of M7 is connected with node Iin2 with the drain electrode of M5, M4, M8 respectively with switch SW 1, SW2, connect, M9, M10, M11, M12, the grid of M13 is connected with the drain electrode of the drain electrode of M9 and M7, M14, M15, M16, M17, the grid of M18 is connected with the drain electrode of the drain electrode of M14 and M6, the drain electrode of M4, grid and switch SW 3 connect and compose the biasing of current source matrix, the drain electrode of M8, grid and switch SW 4 connect and compose the another one biasing of current source matrix, M10, the drain electrode of M11 is connected and M12 with switch SW 1, the drain electrode of M13 with manage SW2 and be connected M9, M14, M15, M16, M17, the source ground of M18.
Operation principle is: the breadth length ratio of transistor M9, M10, M11, M12, M13 is K: K: 1: K: 1, and transistor M14, nurse 15, M16, M17, M18 breadth length ratio are K; K: 1: K: 1, under the normal operating conditions, switch imports M4 and M8 with the electric current of M10, M12 through switch SW 1, SW2, then electric current keeps the numerical value same with electric current I in1, Iin2 substantially, under test mode, switch imports M4, M8 with the electric current of M11, M13, and then this moment, electric current will be 1/K under the normal condition.
Set K=32, then as above-mentioned, the electric capacity that needs is 330/32=10pf.
Because the circuit of introducing can cause extra error, therefore when using big current offset, precision can reduce.
Below discuss another pierce circuit that improves precision
Be depicted as the triangular-wave generator that frequency is directly proportional with electric current as Fig. 7 a, annexation is: current source I1 is through after the switch SW 1, electric current is inserted switch SW 2 and electric capacity respectively, voltage on the electric capacity inserts back the positive input terminal of comparator between the dead zone and the negative input end of comparator connects reference voltage, the output of comparator through two inverters after, difference output pulse waveform OUTB and OUT, switch SW 1, SW2, SW3 are controlled by OUTB and OUT, current source I2 handles through entering image electric current M:1 after the switch SW 2, passes through switch SW 3 then as the capacitance discharges electric current.
Operation principle is: behind the electrification reset, the voltage on the electric capacity is " 0 ", at this moment, OUTB=1 and OUT=0, switch SW 1 inserts electric capacity to the electric capacity charging and switch SW 2 imports the M:1 mirror images with electric current I 2 with current source I1, imports power supplys through switch SW 3 then; Cross back the upper threshold value of comparator between the dead zone when voltage on the electric capacity after, the comparator output switching activity, OUTB=0 and OUT=1, at this moment, switch SW 1 inserts switch SW 2 with electric current I 1, switch SW 2 inserts electric current I 2 GND and electric current I 1 is inserted mirror image M:1, give capacitor discharge through switch SW 3, after voltage on the electric capacity was crossed back lower limit between the dead zone, comparator overturn, OUTB=1 and OUT=0, thus a new charge cycle begun.
In above circuit, electric current I 2 is close to I1 and equates, its effect is to provide a working point to improve the speed of current switching to image current M:1.
By preceding described, charging current is I1 and discharging current is I1/M.
Charging interval Tch=C*dV/I1
Discharge time Tdis=C*dV*M/I1
Oscillator frequency=1/ (Tch+Tdis)=I1/ (C*dV* (1+M))
Wherein, dV is the voltage between the dead zone that returns of comparator, and M is a fixed coefficient of image electric current, therefore, adopt the detection of the error that this kind oscillator will be and proofread and correct more accurate.The main source of error of triangular wave oscillator bearing calibration is led the flex point of trailing edge and the trailing edge flex point to rising edge in rising edge.As shown in figure 11, the factor of this error is: the FEEDTHROUGH effect of the logic control signal in the switch, the time difference of charging current and discharging current conversion etc.Owing to a plurality of identical current sources are adopted a same error-detecting module, therefore,, can obtain high-precision correction as long as keep mating in the variation of flex point at any two different current sources.
The time period of setting flex point is 10ns, matching error during at different current source is 0.1%, then at the digital to analog converter of 14 bit accuracy, the rising edge time that needs is: voltage is 1V to 10*0.1%*16384=164ns. between the dead zone when comparator returns, when current source current was 80uA, capacitance size was C=I*dt/dV=80uA*164ns/1V=13pF.
Below with the circuit structure of unit in the example explanation current source matrix.Current source matrix element circuit schematic diagram as shown in Figure 8, annexation is: the source electrode of transistor M1, M2, M3, M4, M5, M6, M7 connects power supply, their grid is connected with node Vbias1P biasing, the drain electrode of M2, M3, M4, M5, M6, M7 respectively with correcting switch SWec[1:7] an end be connected, correcting switch SWec[1:7] end output be connected with the leakage agent of M1 and the source electrode of M8, the grid of M8 is connected with node bias VbiasP2, correcting switch SWec[1:7] other end output earth connection.The switch matrix unit of the drain electrode of M8 during with operate as normal is connected, and the end output of switch meets node IoutP, and other end output meets node IoutN, correcting switch SWec[1:7] state controlled by the related data in the register.
Electric current among the transistor M1 is the elementary current of unit in the current source matrix, M[2:7] in electric current be correcting current.When the corresponding data in the register when being effective, then Xiang Guan correcting switch adds the correcting current of correspondence the source electrode of M8 to and makes that the output current of correlation unit increases in the current source matrix.
The number in correcting current source precision and factor such as the kind in correcting current source and difference as required.The correcting current source can be that the essentially identical current source of a plurality of size of current constitutes, also can be that size of current becomes the current source of 2 systems substantially and constitutes: if the matching precision that technology is guaranteed is 1%, then the size of current in correcting current source can be respectively: I/64, I/128, I/256..., wherein, I is the size of elementary current in the current source matrix.
Below discuss the high consistency structure of decoding circuit.
MidDecoder merge module schematic diagram shown in Fig. 9 a, signal have experienced the gate of as much and have handled before entering d type flip flop and latching.Be depicted as 5 bit MidDecoder schematic diagrames as Fig. 9 b, wherein used merge module and the d type flip flop shown in 4 Fig. 9 a, all signals are handled entering the gate that has also all experienced as much before latching.
5 bit thermometer mode decoder cell schematics shown in Fig. 9 c in the decoding of 5 bits, are used 31 identical unit.Wherein, three of each unit input signal L_IN[1:3] all be from 13 outputs of MidDecoder, to make up to carry out.The annexation of corresponding logic output and input for example, is exported OUTPUT[15 in order to obtain logic shown in the line table], L1 need be connected with L_IN1, L7 is connected with L_IN2 and GND is connected with L_IN3.
Annexation described in the table 2 only is wherein a kind of, other annexation also can realize the function of thermometer decoding, for example, (L2, L11 L12) only are a kind of connection of correspondence to OUTPUT (20) "=", when connection changes to (L12, VDD in the time of GND), can realize same function.
5 bit MidDecoder have multiple implementation, shown in Fig. 9 d and Fig. 9 e, in order to obtain corresponding logic output result, 13 outputs of MidDecoder must be realized different connections with decoder element.
As Figure 13 is the annexation of 13 outputs of the input of 5 bit decoder and MidDecoder
Be the MidDecoder circuit of 4 bit decoding devices as shown in figure 10.Simultaneously, 15 unit that 4 bit thermometer decoding circuits need be shown in Fig. 9 c.Their annexation is shown in the connection relational table of 8 outputs of the input of 4 bit decoder of Figure 14 and MidDecoder.
Claims (12)
1, a kind of structure of current rudder high-speed, high precision D/A converter has current source offset generating circuit, current source matrix, high consistency numeral input decoding, can survey recoverable segmented current source matrix and switch matrix group, output current is to five parts of modular converter of voltage; The detection of current source cell error and correcting circuit comprise 3 modules: between register matrix, different weight current source matrix from dynamic(al) correction, with the weight unit current source matrix inner school module: automatic correction module is connected between current source offset generating circuit and current source matrix and different weight current source matrixes, and automatic correction module also can directly be connected with current source matrix between different weight current source matrixes, and data output to the register matrix; Be connected with the register matrix with current source matrix with the inner correction module of weight unit current source matrix; Numeral input is after decoding, and high consistency decoder output control switch matrix imports the two-way output branch road of difference with the electric current of current source matrix, and difference current, is exported with the differential voltage pattern behind voltage transformation module through electric current.
2, according to claim 1, it is characterized in that: numeral input decoder module is input as the N bit digital signal and is output as 2 N power N powers individual or 2 and subtracts one, and the number of " 0 " or " 1 " is successively decreased successively or progressively increased in the output.
3, structure of current rudder high-speed, high precision D/A converter according to claim 1 is characterized in that: decoding circuit (to call MidDecoder in the following text) and two parts of thermometer mode decoder in the middle of numeral input decoder module comprises; The numeral input of middle decoding circuit can not wait to 10 Bit datas from 2 Bit datas; The thermometer mode decoder has the integral number power of 2 integral number power or 2 to subtract an identical unit to constitute.
4, structure of current rudder high-speed, high precision D/A converter according to claim 3 is characterized in that: MidDecoder circuit logic output that numeral input decoder module is different and the annexation between the input of thermometer mode decoder are different; Between same MidDecoder circuit and the thermometer mode decoder, also can take multiple connected mode.
5, structure of current rudder high-speed, high precision D/A converter according to claim 1 is characterized in that: the current source matrix error correction module is by error is added up to the measurement of error, utilizes the method for digital counting to realize then; Its correction to error is to increase or the electric current of less this unit is realized by the correcting unit in the Data Control current source matrix of utilize measuring.
6, structure of current rudder high-speed, high precision D/A converter according to claim 5, it is characterized in that, the size of current of the unit current source of measuring in oscillator of current source matrix error measure module structure, the frequency of this oscillator and matrix is directly proportional; In the time period that equates, the number of times that output is reversed to oscillator measures, and different upset number of times has promptly been represented the error between the unit current source.
7, structure of current rudder high-speed, high precision D/A converter according to claim 6 is characterized in that, oscillator can make saw-toothed oscillator, also can be triangular wave oscillator.
8, structure of current rudder high-speed, high precision D/A converter according to claim 6 is characterized in that, the identical time period in the current source matrix error measure module can utilize inner high stable clock signal to obtain; Also can utilize outside high stable clock signal to obtain.
9, structure of current rudder high-speed, high precision D/A converter according to claim 5 is characterized in that, if correction module is the matrix of segmentation, then need to carry out internal matrix is proofreaied and correct and matrix between correction; If be the matrix of not segmentation, then only need proofread and correct at internal matrix.
10, structure of current rudder high-speed, high precision D/A converter according to claim 9 is characterized in that, proofreaies and correct and carries out after powering on; The data that proofread and correct to need obtain by the error measure module, are stored in the register matrix, and the increase and decrease of electric current in this Data Control matrix unit, thus reach the purpose of size of current precision-matched between the unit; Data in the memory remain unchanged in the digital to analog converter normal work period.
11, structure of current rudder high-speed, high precision D/A converter according to claim 9 is characterized in that, the correction data in the current source matrix error correction module in the memory can obtain by polling method, also can obtain by variable step size method.
12, structure of current rudder high-speed, high precision D/A converter according to claim 9, it is characterized in that, the error correction of different internal matrixs, can use a correction module one by one matrix carry out the unit one by one, also can use a correction module to carry out simultaneously by each matrix; The correction of error must use same correction module to carry out between matrix.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA021340242A CN1499729A (en) | 2002-11-08 | 2002-11-08 | High-speed, high precision D/A converter in structure of current rudder |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA021340242A CN1499729A (en) | 2002-11-08 | 2002-11-08 | High-speed, high precision D/A converter in structure of current rudder |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1499729A true CN1499729A (en) | 2004-05-26 |
Family
ID=34231354
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA021340242A Pending CN1499729A (en) | 2002-11-08 | 2002-11-08 | High-speed, high precision D/A converter in structure of current rudder |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1499729A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101902222A (en) * | 2009-05-26 | 2010-12-01 | 瑞昱半导体股份有限公司 | Automatic-correcting current source, and digital analogue converter using same and operating method |
| CN102195653A (en) * | 2010-02-10 | 2011-09-21 | 爱德万测试株式会社 | Output apparatus and test apparatus |
| CN101686057B (en) * | 2008-09-28 | 2012-02-29 | 扬智科技股份有限公司 | Digital analogue converter |
| CN103095303A (en) * | 2012-10-23 | 2013-05-08 | 深圳先进技术研究院 | Current mode and voltage mode combined digital analog converter |
| CN104769848A (en) * | 2012-08-29 | 2015-07-08 | 瑞典爱立信有限公司 | Digital analog converter |
| CN107517058A (en) * | 2017-08-25 | 2017-12-26 | 电子科技大学 | A kind of segmented current steer type DAC and its Background calibration method with calibration function |
| CN108183711A (en) * | 2018-01-24 | 2018-06-19 | 厦门理工学院 | A kind of current source cell selection method of dynamic random equilibrium |
-
2002
- 2002-11-08 CN CNA021340242A patent/CN1499729A/en active Pending
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101686057B (en) * | 2008-09-28 | 2012-02-29 | 扬智科技股份有限公司 | Digital analogue converter |
| CN101902222A (en) * | 2009-05-26 | 2010-12-01 | 瑞昱半导体股份有限公司 | Automatic-correcting current source, and digital analogue converter using same and operating method |
| CN101902222B (en) * | 2009-05-26 | 2013-07-03 | 瑞昱半导体股份有限公司 | Automatic-correcting current source, and digital analogue converter using same and operating method |
| CN102195653A (en) * | 2010-02-10 | 2011-09-21 | 爱德万测试株式会社 | Output apparatus and test apparatus |
| CN104769848A (en) * | 2012-08-29 | 2015-07-08 | 瑞典爱立信有限公司 | Digital analog converter |
| CN104769848B (en) * | 2012-08-29 | 2019-03-15 | 瑞典爱立信有限公司 | Digital analog converter |
| CN103095303A (en) * | 2012-10-23 | 2013-05-08 | 深圳先进技术研究院 | Current mode and voltage mode combined digital analog converter |
| CN103095303B (en) * | 2012-10-23 | 2018-02-06 | 深圳先进技术研究院 | A kind of current mode and voltage-type compositive mathematical models converter |
| CN107517058A (en) * | 2017-08-25 | 2017-12-26 | 电子科技大学 | A kind of segmented current steer type DAC and its Background calibration method with calibration function |
| CN107517058B (en) * | 2017-08-25 | 2019-08-30 | 电子科技大学 | A kind of segmented current steer type DAC and its Background calibration method with calibration function |
| CN108183711A (en) * | 2018-01-24 | 2018-06-19 | 厦门理工学院 | A kind of current source cell selection method of dynamic random equilibrium |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8471751B2 (en) | Two-stage analog-to-digital converter using SAR and TDC | |
| CN109861691B (en) | Analog-to-digital converter circuit of two-step hybrid structure SAR TDC based on delay phase-locked loop | |
| CN110958021B (en) | Self-calibration system and method for high-speed high-precision current rudder digital-to-analog converter | |
| CN1290266C (en) | A/D converter | |
| CN104283563B (en) | Successive approximation type analog-digital converter for monotonic switching mode | |
| CN104967451A (en) | Successive approximation type analog-to-digital converter | |
| CN1341293A (en) | High-precision D-A converter circuit | |
| CN104485957B (en) | Production line analog-digital converter | |
| CN110557013B (en) | PWM dead time control system | |
| CN1913364A (en) | Digital/analog converter | |
| CN102594353A (en) | Digital-to-analog converter and successive approximation storage converter | |
| CN1499730A (en) | Pipeline structured A/D converter with high speed and high precision | |
| CN111327324A (en) | Capacitor array structure suitable for successive approximation type analog-to-digital converter | |
| CN1499729A (en) | High-speed, high precision D/A converter in structure of current rudder | |
| CN111865319A (en) | Ultra-low power consumption successive approximation type analog-to-digital converter based on four-input comparator | |
| CN116846391A (en) | Low-offset low-power consumption dynamic comparator based on double calibration | |
| CN109783061B (en) | True random number generator sampled by oscillator | |
| CN110690901A (en) | High-speed low-power-consumption SAR ADC capacitance mismatch self-calibration method and circuit | |
| CN104852739B (en) | A kind of precision restructural delay line analog-digital converter circuit for digital power | |
| CN104113339B (en) | high-speed asynchronous successive approximation type analog-to-digital converter | |
| CN117826562A (en) | High-precision digital time converter circuit with calibration loop | |
| CN117215361A (en) | Ramp voltage generating circuit and waveform digitizing system | |
| CN1254119C (en) | Method for controlling multichannel, and circuit for carrying out same | |
| CN1691495A (en) | Differential amplifier device, 2-stage amplifier device, and analog/digital converter device | |
| CN115473531A (en) | High-precision high-linearity analog-to-digital converter with low power consumption and small layout |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |