CN1494369A - Electroplating method of prited circuit board - Google Patents
Electroplating method of prited circuit board Download PDFInfo
- Publication number
- CN1494369A CN1494369A CNA031593828A CN03159382A CN1494369A CN 1494369 A CN1494369 A CN 1494369A CN A031593828 A CNA031593828 A CN A031593828A CN 03159382 A CN03159382 A CN 03159382A CN 1494369 A CN1494369 A CN 1494369A
- Authority
- CN
- China
- Prior art keywords
- power supply
- substrate
- dielectric substrate
- circuit board
- connection pads
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
- C25D5/02—Electroplating of selected surface areas
- C25D5/022—Electroplating of selected surface areas using masking means
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
- H05K3/241—Reinforcing the conductive pattern characterised by the electroplating method; means therefor, e.g. baths or apparatus
- H05K3/242—Reinforcing the conductive pattern characterised by the electroplating method; means therefor, e.g. baths or apparatus characterised by using temporary conductors on the printed circuit for electrically connecting areas which are to be electroplated
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
- H05K3/243—Reinforcing the conductive pattern characterised by selective plating, e.g. for finish plating of pads
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/0959—Plated through-holes or plated blind vias filled with insulating material
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/05—Patterning and lithography; Masks; Details of resist
- H05K2203/0502—Patterning and lithography
- H05K2203/054—Continuous temporary metal layer over resist, e.g. for selective electroplating
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/15—Position of the PCB during processing
- H05K2203/1572—Processing both sides of a PCB by the same process; Providing a similar arrangement of components on both sides; Making interlayer connections from two sides
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
- H05K3/0052—Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
- H05K3/427—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in metal-clad substrates
Abstract
A plating method for a printed circuit board includes: a first step of providing a substrate having a plurality of connection pads and circuit patterns connected to the connection pads; a second step of using some of the circuit patterns provided on a surface of the substrate as a power connection portion and connecting the power connection portion to an external power source; a third step of covering a surface of the substrate excepting the connection pads with a plating resistance resist to shield it; a fourth step of supplying power to the connection pad through the power connection portion and forming a gold-plated layer on the connection pad; and a fifth step of making the power connection portion and the external power source to be electrically short. With this method, a printed circuit board without a power supply line for gold-plating can be obtained.
Description
Background of invention
Invention field
The present invention relates to printed circuit board (PCB), relate in particular to the electro-plating method of printed circuit board (PCB), described method can form electrodeposited coating and need not to be used for power line gold-plated on pad.
The description of prior art
Fig. 1 is a plan view, the major part according to the printed circuit board (PCB) of conventional art is shown, and Fig. 2 is a sectional view, and the major part according to the printed circuit board (PCB) of conventional art is shown.
As shown in Fig. 1 and 2, on a substrate 1, form multilayer board 1a and 1b, when they are separated, intactly form polylith printed circuit board (PCB) 1a and 1b.
In the traditional printing circuit board, on the surface of stock 8, form a plurality of bond pads 3 and a plurality of ball-pads 4, connect leads having connected many of will be connected to semiconductor chip on electric on the pad 3, on pad 4 with the solder ball that is used for being connected with other printed circuit board (PCB).Form circuit pattern by the single or multiple lift in the printed circuit board (PCB).Bond pad 3 and ball-pads 4 are connected to circuit pattern on electric.
Central authorities form the long power line 5 with certain width on the surface of stock 8, lead-in conductor 6 is come out from power line 5 branches, and be connected to bond pad 3 or ball-pads 4.Because many electric currents flow in power line 5, so the width of formed power line 5 is wideer than the width of lead-in conductor 6.
In the printed circuit board (PCB) of conventional art, when when external source offers power line 5 to power supply, power supply is offered bond pad 3 and ball-pads 4 by many lead-in conductors 6, carry out gold-plated.
When finishing gold-plated process, carry out the process that the polylith printed circuit board (PCB) is separated.That is, by using scriber (router) to separate printed circuit board (PCB) 1a and 1b along 7 cuttings of line line of cut.
At this moment, because line line of cut 7 is wideer than power line 5, thus when separating printed circuit board (PCB) 1a and 1b, removed power line 5, so that each bond pad 3 and ball-pads 4 short circuit on electric, and only keep lead-in conductor 6.
Yet, have following point according to traditional electroplating printed circuit board method.
Promptly, because bond pad is retained in the surface of finishing printed circuit board (PCB) 1a and 1b with the lead-in conductor 6 that ball-pads 4 is connected, so when the semiconductor chip that uses on the fitting printed circuit board, lead-in conductor 6 causes the interference of peripheral circuits or increases power loss, and an element of effect as obstruction signal flow, the result degrades the performance of product.
As shown in FIG. 3, in order to deal with problems, after gold-plated on carrying out bond pad 3 and ball-pads 4, remove lead-in conductor by engraving method.
Yet, in this case, only correctly place etching protective film than difficulty in the location of bond pad 3 and ball-pads 4.Also have, send another problem, when removing lead-in conductor, the etching solution of institute's combination is penetrated in bond pad 3 and the ball-pads 4, even has removed bond pad 3 and ball-pads 4.Therefore, for fear of this problem, not exclusively remove lead-in conductor 6 and the remaining lead-in conductor of reservation.
Yet even in this case, the existence of remaining lead-in conductor 10 causes above-mentioned identical problem more or less.
In addition, in the printed circuit board (PCB) of conventional art, handle difficulty of solder mask, because after processing of circuit, removed lead-in conductor.
Summary of the invention
Therefore, the purpose of this invention is to provide a kind of electro-plating method of printed circuit board (PCB), described method can reduce power loss and improve the performance of product by the printed circuit board (PCB) with lead-in conductor is provided.
In order to reach these and other advantage, and according to purpose of the present invention, as implementing here and describing widely, a kind of electro-plating method of the printed circuit board (PCB) that is provided for, comprise: a kind of electro-plating method that is used for printed circuit board (PCB) comprises: the first step of substrate is provided, and described substrate has a plurality of connection pads and is connected to the circuit pattern of connection pads; Use second step of some circuit pattern, on substrate surface, provide described circuit pattern, and the power supply coupling part is connected to external power source as the power supply coupling part; With stoping the substrate surface of electroplating film covering except connection pads to its third step that shields; The 4th step that power supply is offered connection pads and on connection pads, form Gold plated Layer by the power supply coupling part; And the 5th step that makes power supply coupling part and external power source short circuit on electric.
In electroplating printed circuit board method of the present invention, second step comprises: apply photoresist on substrate surface; Remove a part of photoresist connection pads is exposed, and some circuit pattern is exposed, to form the power supply coupling part; And on the surface of substrate the coated electrolyte layer, be used for the connection between power supply coupling part and the external power source.
In the electro-plating method of printed circuit board (PCB) of the present invention, form dielectric substrate by chemical plating method, dielectric substrate has the thickness of 0.3～0.7 μ m.
In the electro-plating method of printed circuit board (PCB) of the present invention, in third step, apply the prevention electroplating film at the substrate surface that has dielectric substrate to form thereon, and the 5th step comprises: remove dielectric substrate and stop electroplating film; And on the surface of the substrate of removing dielectric substrate and prevention electro-cladding, apply photoresist, make it power supply short circuit to cover the power supply coupling part.
In order to achieve the above object, a kind of electroplating printed circuit board method that also provides comprises: the first step of substrate is provided, and the two sides of described substrate has a plurality of bond pads and ball-pads and is connected to bond pad and the circuit pattern of ball-pads; Use second step of some circuit pattern, on substrate surface, provide described circuit pattern, and the first power supply coupling part is connected to external power source as the first and second power supply coupling parts; Be coated with ball-pads formation substrate surface thereon to its third step that shields with the prevention electroplating film; By the first power supply coupling part power supply is offered bond pad to form the 4th step of Gold plated Layer on bond pad; And the 5th step that makes the first power supply coupling part and external power source short circuit on electric; The second source coupling part is connected to external power source and is coated with ball-pads formation substrate surface thereon to its 6th step that shields with the prevention electroplating film; By the second source coupling part power supply is offered ball-pads to form the 7th step of Gold plated Layer on ball-pads; And the 8th step that makes second source coupling part and external power source short circuit on electric.
In electroplating printed circuit board method of the present invention, the 5th step comprises: remove dielectric substrate and stop electroplating film; And on the surface of the substrate of removing dielectric substrate and prevention electroplating film, apply photoresist, make it power supply short circuit to cover the first power supply coupling part.
In the electro-plating method of printed circuit board (PCB) of the present invention, the 6th step comprises: form dielectric substrate forming on the substrate surface of bond pad with the place that it is connected to the second source coupling part on electric; And coating stops electroplating film on the surface of dielectric substrate.
In the electro-plating method of printed circuit board (PCB) of the present invention, the 8th step comprises: remove prevention electroplating film and dielectric substrate; And cover the second source coupling part with photoresist, make the short circuit on electric of second source coupling part.
From detailed description below in conjunction with accompanying drawing, will be more clear to above-mentioned purpose, characteristic, aspect and advantage of the present invention with other.
The accompanying drawing summary
Comprising to provide further understanding of the present invention and the accompanying drawing that is combined in this and constitutes a part of this specification are illustrated embodiments of the invention, is to explain principle of the present invention with the effect of specification.
In the accompanying drawings:
Fig. 1 is a plane graph, and an example according to the printed circuit board (PCB) of conventional art is shown;
Fig. 2 is a perspective view, and the printed circuit board (PCB) according to conventional art is shown;
Fig. 3 is a plane graph, and another example according to the printed circuit board (PCB) of conventional art is shown;
Fig. 4 A illustrates a kind of process of order of method to 4L, and described method is used to make the circuit pattern according to the printed circuit board (PCB) of preferred embodiment of the present invention; And
Fig. 5 A is a plane graph to 5E, and order illustrates the circuit pattern manufacture process according to the printed circuit board (PCB) of preferred embodiment of the present invention.
The detailed description of preferred embodiment
Now with the preferred embodiment of the present invention of detailed clearancen, preferred embodiment example shown in the drawings.
Fig. 4 A illustrates a kind of process of order of method to 4L, and described method is used to make the circuit pattern according to the printed circuit board (PCB) of preferred embodiment of the present invention.
The electro-plating method of printed circuit board (PCB) of the present invention is described to 4L referring now to Fig. 4 A.
At first, preparing substrate 50.Substrate 50 comprises at least a or multiple insulating material is carried out hot compression and insulating barrier 52 that forms and a plurality of circuit patterns 54 that are stacked on insulating barrier 52 inside.On two surfaces of insulating barrier 52, form metal level 56, and form a plurality of through holes 58 with connecting circuit pattern 54 and metal level 56 (with reference to figure 4A) on electric.
Make substrate 50 by the manufacture process of general multilayer board, in described multilayer board, on multilayer insulation plate, form circuit pattern by compound inslation stack of plates and hot compression.
On the surface of substrate 50, form electrodeposition of metals 60 by electroplating process.Forming electrodeposition of metals 60 on the surface of metal level 56 and on the inwall of through hole 58.
The electrodeposition of metals 60 that forms on the surface of metal level 56 is used for forming circuit pattern 54, and is used in ensuing process (with reference to figure 4B) connecting circuit pattern on electric at the electrodeposition of metals 60 that forms on the inwall of through hole 58.
Then, selectively remove metal level 56 and electrodeposition of metals 60 to form circuit pattern 62.Promptly, on two surfaces of substrate 50, form circuit pattern 62 by general exposure/developing process and etching process, use some circuit pattern 62 as on electric, being connected to the bond pad 64 of semiconductor chip, and use some other circuit pattern as the ball-pads 66 that is connected to other printed circuit board (PCB) on electric.Generally, ball-pads 66 is formed on the opposite face of the one side that forms bond pad 65.
Bond pad (bonding pad) 64 be connected to be used for be installed in printed circuit board (PCB) on the golden lead that is connected on electric of semiconductor chip, and on electric, be connected to by connecting the circuit pattern 62 that pattern 68 forms at through hole 58 places.
Solder ball is appended to ball-pads 66, be used for connecting, and ball-pads 66 is connected to the circuit pattern 62 that forms at through hole 58 places on electric by connecting pattern 68 with different printed circuit board (PCB)s.
After circuit pattern 62, on the surface of substrate 50, form bond pad 64 and ball-pads 66, on the surface of substrate 50, apply photoresist 70.Photoresist 70 is protective circuit patterns 62, and is not coated in connection pads 64 and 66 places that constitute bond pad 64 and ball-pads 66.
That is, on the whole surface of substrate 50, apply after the photoresist 70, remove photoresist 70 by other process, to expose connection pads 64 and 66 at connection pads 64 and 66 part places.
Form the first and second power supply coupling parts 72 and 74, be used as the path that power supply is offered connection pads 64 and 66.
Make a part of circuit pattern 62 exposures (expose) form the first and second power supply coupling parts 72 and 74 by removing a part of photoresist 70.That is, make the formed a part of circuit pattern 62 that is connected to through hole 58 expose (with reference to figure 4D).
To be described in the process that connection pads 64 and 66 places form Gold plated Layer now.
At first, on two surfaces of substrate 50, form dielectric substrate 76 and 78, so that the first and second power supply coupling parts 72 and 74 are connected to external power source.
Best, form thin as far as possible dielectric substrate 76 and 78, make and in ensuing process, remove easily.For example, best, dielectric substrate 76 and 78 has the thickness of 0.3 μ m～0.7 μ m.
Then, on the opposite face of the one side that forms bond pad 64, carry out shielding processes (with reference to figure 4F) with prevention electroplating film 80.
After this, remove the lip-deep dielectric substrate 76 (with reference to figure 4G and 5B) that forms bond pad 64 by engraving method etc.At this moment, because on the surface (that is, the opposite face of bond pad 64) that forms ball-pads 66, applied prevention electroplating film 80, so do not remove dielectric substrate 78.
Except said method, can only on the surface that forms ball-pads 66, form dielectric substrate 78, and on the surface that forms bond pad 64, not form dielectric substrate 76.
In this state, when providing power supply (P) by the first power supply coupling part 72, power supply is offered bond pad 64 by dielectric substrate 78, the circuit pattern 62 that is formed on through hole 58 places and connection pads 68 from the outside.
Then, on the surface of bond pad 64, form Gold plated Layer 82 (with reference to figure 4H).Arrow shown in Figure 4 is represented power source path, and circuit pattern 62 is to form in the lip-deep annular shape of through hole 58, and is connected to the first power supply coupling part 72 and bond pad 64 on electric.
After bond pad 64 places are completed into Gold plated Layer 82, remove the prevention electroplating film 80 and the dielectric substrate 78 that on the surface that ball-pads 66 is provided, form.Then, 70 apply the first power supply coupling part 72 with photoresist, make its short circuit (with reference to Figure 41,5C and 5D) on electric.
On bond pad 64, form after the Gold plated Layer 82, on ball-pads 66, form Gold plated Layer 92.
At first, on two surfaces of the substrate 50 of finishing said process, form dielectric substrate 86 and 88.Then, on electric, connect second source coupling part 74 and dielectric substrate 88.
Then, on the surface of the dielectric substrate 88 that forms on the one side that bond pad 64 is provided, apply prevention electroplating film 90.
Then, remove the dielectric substrate 86 (with reference to figure 4J) that on the surface that ball-pads 66 is provided, applies by engraving method etc.
In this state, by second source coupling part 74 external power source (P) is applied to ball-pads 66, to form Gold plated Layer 92 (with reference to figure 4K and 5E) at ball-pads 66 places.
(P) offers dielectric substrate 88 external power source, and is applied to ball-pads 66 by being connected to dielectric substrate 88 with the second source coupling part 74 that is formed on the circuit pattern 62 at through hole 58 and connection pads 68 places.
After ball-pads 66 places form Gold plated Layer 92, remove and stop electroplating film 90 and dielectric substrate 88, and 70 cover second source coupling parts 74 with photoresist so that can be on electric short circuit second source coupling part 74.
Describe so far, the manufacture method of the circuit pattern of the printed circuit board (PCB) by the said process manufacturing has following advantage.
Promptly, because use some circuit pattern as the power supply coupling part and on substrate surface, form dielectric substrate, external power source is sent to connection pads by the power supply coupling part, so do not need the lead-in conductor of power supply, therefore, the performance that can reduce the loss of power and can improve product.
The present invention can in several forms, implement and do not depart from spirit of the present invention or essence feature, should also be appreciated that, any details of above-mentioned explanation does not limit the foregoing description, unless point out separately, but should broadly be interpreted as in the spirit and scope of the present invention of appending claims definition, therefore, specify appending claims to comprise in all borders of dropping on claims and the scope or change and modification in the equivalent of this border and scope.
Claims (8)
1. the electro-plating method of a printed circuit board (PCB) is characterized in that, it comprises:
The first step of substrate is provided, and described substrate has a plurality of connection pads and is connected to the circuit pattern of described connection pads;
Use second step of some circuit pattern, on described substrate surface, provide described circuit pattern, and described power supply coupling part is connected to external power source as the power supply coupling part;
With stoping electroplating film to cover the third step of the substrate surface except described connection pads;
Power supply is offered described connection pads and on described connection pads, form the 4th step of Gold plated Layer by described power supply coupling part; And
Make the 5th step of described power supply coupling part and described external power source short circuit on electric.
2. the method for claim 1 is characterized in that, described second step comprises the following steps:
On described substrate surface, apply photoresist;
Remove a part of photoresist and make the connection pads exposure, and make some circuit pattern exposure, to form the power supply linkage unit; And
Coated electrolyte layer on the surface of described substrate is used to connect power supply linkage unit and external power source.
3. method as claimed in claim 2 is characterized in that, forms described power supply linkage unit by remove photoresist from a part of circuit pattern, and receives power supply by linking to each other with described dielectric layer.
4. method as claimed in claim 2 is characterized in that, forms described dielectric substrate by the electrodeless plating method.
5. method as claimed in claim 2 is characterized in that described dielectric substrate has the thickness of 0.3～0.7 μ m.
6. method as claimed in claim 2 is characterized in that, forms the described dielectric substrate with desired thickness by carrying out electrolytic plating method on the dielectric substrate that forms in addition.
7. method as claimed in claim 2 is characterized in that, in second step, stoping electroplating film to be coated on the dielectric substrate formation substrate surface thereon.
8. method as claimed in claim 2 is characterized in that, described the 4th step comprises:
Remove described dielectric substrate and stop electroplating film; And on the substrate surface of removing dielectric substrate and prevention electroplating film, apply photoresist, make it power supply short circuit to cover the power supply linkage unit.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2002-0055977 | 2002-09-14 | ||
| KR1020020055977 | 2002-09-14 | ||
| KR1020020055977A KR20040024381A (en) | 2002-09-14 | 2002-09-14 | Plating method for PCB |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1494369A true CN1494369A (en) | 2004-05-05 |
| CN1306856C CN1306856C (en) | 2007-03-21 |
Family
ID=31987440
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB031593828A Expired - Fee Related CN1306856C (en) | 2002-09-14 | 2003-09-11 | Electroplating method of prited circuit board |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US20040050708A1 (en) |
| KR (1) | KR20040024381A (en) |
| CN (1) | CN1306856C (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1310297C (en) * | 2004-06-22 | 2007-04-11 | 威盛电子股份有限公司 | Packaging base plate with no plating bar and making method for same |
| CN101437357B (en) * | 2007-11-14 | 2010-07-14 | 英业达股份有限公司 | Welding pad structure for printed circuit board and method for forming the same |
| CN102268718A (en) * | 2011-07-13 | 2011-12-07 | 番禺得意精密电子工业有限公司 | Input equipment, electroplating device and electroplating method using electroplating device |
| CN114883252A (en) * | 2022-05-26 | 2022-08-09 | 业成科技（成都）有限公司 | Substrate electroplating method, substrate, display panel, display device and electronic equipment |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100641851B1 (en) * | 2004-10-25 | 2006-11-03 | 엘지전자 주식회사 | Making method of printed circuit board |
| CN100455161C (en) * | 2004-12-07 | 2009-01-21 | 鸿富锦精密工业（深圳）有限公司 | Method for disigning of printed circuit board and printed circuit board thereof |
| US20070111491A1 (en) * | 2005-11-13 | 2007-05-17 | Hsu Jun C | Process for electroplating metal layer without plating lines after the solder mask process |
| CN103046031B (en) * | 2012-12-11 | 2014-08-13 | 胜宏科技（惠州）股份有限公司 | Method for chemically gold-plating circuit board |
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|---|---|---|---|---|
| JPH0335594A (en) * | 1989-07-03 | 1991-02-15 | Matsushita Electric Works Ltd | Method of processing multilayer printed circuit board |
| JPH04110491A (en) * | 1990-08-31 | 1992-04-10 | Sony Corp | Circuit board |
| US5567295A (en) * | 1994-01-11 | 1996-10-22 | Dell Usa L.P. | Method and apparatus for making staggered blade edge connectors |
| US6268016B1 (en) * | 1996-06-28 | 2001-07-31 | International Business Machines Corporation | Manufacturing computer systems with fine line circuitized substrates |
| CN1104832C (en) * | 1996-08-09 | 2003-04-02 | 松下电工株式会社 | Method for plating independent conductor circuit |
| US6376049B1 (en) * | 1997-10-14 | 2002-04-23 | Ibiden Co., Ltd. | Multilayer printed wiring board and its manufacturing method, and resin composition for filling through-hole |
| JP4129665B2 (en) * | 1999-10-12 | 2008-08-06 | 日本サーキット工業株式会社 | Manufacturing method of substrate for semiconductor package |
| JP2002158423A (en) * | 2000-11-21 | 2002-05-31 | Oki Electric Ind Co Ltd | Structure of printed wiring board and electrolytic plating method |
| JP2002232154A (en) * | 2001-02-07 | 2002-08-16 | Mitsumi Electric Co Ltd | Method for wiring plating lead wire of gold-plating substrate |
-
2002
- 2002-09-14 KR KR1020020055977A patent/KR20040024381A/en not_active Application Discontinuation
-
2003
- 2003-08-20 US US10/644,036 patent/US20040050708A1/en not_active Abandoned
- 2003-09-11 CN CNB031593828A patent/CN1306856C/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1310297C (en) * | 2004-06-22 | 2007-04-11 | 威盛电子股份有限公司 | Packaging base plate with no plating bar and making method for same |
| CN101437357B (en) * | 2007-11-14 | 2010-07-14 | 英业达股份有限公司 | Welding pad structure for printed circuit board and method for forming the same |
| CN102268718A (en) * | 2011-07-13 | 2011-12-07 | 番禺得意精密电子工业有限公司 | Input equipment, electroplating device and electroplating method using electroplating device |
| CN102268718B (en) * | 2011-07-13 | 2013-07-10 | 番禺得意精密电子工业有限公司 | Input equipment, electroplating device and electroplating method using electroplating device |
| CN114883252A (en) * | 2022-05-26 | 2022-08-09 | 业成科技（成都）有限公司 | Substrate electroplating method, substrate, display panel, display device and electronic equipment |
| CN114883252B (en) * | 2022-05-26 | 2024-02-23 | 业成光电（深圳）有限公司 | Substrate electroplating method, substrate, display panel, display device and electronic equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| US20040050708A1 (en) | 2004-03-18 |
| CN1306856C (en) | 2007-03-21 |
| KR20040024381A (en) | 2004-03-20 |
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