CN1494140A - 一种可改善阻抗匹配的打线垫结构 - Google Patents

一种可改善阻抗匹配的打线垫结构 Download PDF

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CN1494140A
CN1494140A CNA031585272A CN03158527A CN1494140A CN 1494140 A CN1494140 A CN 1494140A CN A031585272 A CNA031585272 A CN A031585272A CN 03158527 A CN03158527 A CN 03158527A CN 1494140 A CN1494140 A CN 1494140A
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wire pad
metal level
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CN1290184C (zh
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徐鑫洲
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Via Technologies Inc
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Abstract

一种可改善阻抗匹配的打线垫结构，其结构为具有多层电性连接的电子元件传送信号以及接地之用，其结构的主要特征为：两打线垫间具有相互平行、互相重叠且不连接的金属平行板结构；而打线垫之间的结构在具有此金属平行板结构下，可增加与此打线垫结构耦接回路的电容性，以调整回路的阻抗匹配以及电气特性。

Description

一种可改善阻抗匹配的打线垫结构
技术领域
本发明是有关于一种打线垫结构，特别是有关于一种可改善阻抗匹配的打线垫结构。
背景技术
在电子产品不断推陈出新的情况下，其在工作上的频率也逐渐增加，以满足消费者的需求。举例来说，一个射频电路或高速电路其所对应的封装结构，其工作频率就常需要达到GHz等级。
因此，在高速工作频率下，电子产品其对应的封装体结构，就必须具有较佳的电气特性，以使电子产品工作时能够稳定。请参考图1，图1为射频电路其封装体结构的剖面图。如图1所示，封装体结构100中芯片110与基板127间的信号传递可通过较长的金属线125由芯片125耦接至基板127上的引脚(lead)。而芯片110与基板127间信号的部分接地则常通过较短的金属线120直接耦接至基板127上用以承载芯片的芯片垫(die pad)130上，以期望芯片110与基板127间较短的信号回路来达成封装体结构100具有较好的电气特性以及散热要求。
不过，此高频封装体结构100中芯片110与基板127间回路所对应的金属线125、120截面积总和仍然过大，因此，此高频封装体结构100所表现出来的电气特性将属于高电感性以及高阻抗性，且此高频封装体结构100于高频工作时，会因此回路阻抗不匹配而造成信号间的严重反射，而回路的返回损耗(Return Loss)也将变小。
为了使此高频封装体结构100的电气特性更佳，也就是封装体结构100中芯片110与基板127间回路的电感性与电容性能够互相匹配，或返回损耗与介入损耗能够互相匹配。现有技术通常会在封装体结构100中的芯片110内设置NMOS晶体管或PMOS晶体管作为稳定电压的电容，以使封装体结构100的电气特性能够较佳。但NMOS晶体管或PMOS晶体管的设置却无法使得封装体结构100的信号频宽以及准确性有多方面的应用。
此外，又为了使此高频封装体结构100的电气特性更佳，除了在封装体结构100的芯片110中设置作为电容的NMOS晶体管或PMOS晶体管外，更利用金属-半导体-金属(MIM)制程来设置此NMOS晶体管或PMOS晶体管。但此MIM制程也有成本过高，无法广泛运用的困扰。
有鉴于此，本发明提供一种可改善阻抗匹配的打线垫结构，期望通过打线垫结构的简单改良，以增加封装体结构中芯片与基板间回路的电容性，而使此回路的阻抗匹配最佳，封装体结构的电气特性更好。
发明内容
本发明的主要目的是提供一种可改善阻抗匹配的打线垫结构，此打线垫结构为具有多层电性连接的电子元件传送信号以及接地之用，其结构的主要特征为：两打线垫间具有相互平行、互相重叠且不连接的金属结构。
其中，此两打线垫相邻且由电子元件表面埋入至电子元件内部有一深度，此两打线垫由电子元件表面至内部可视其所需而具有依序堆叠的多个金属层以及插塞部。且其中，此两打线垫分别至少一金属层面对面平行延伸且互相重叠有一区域，且两打线垫其金属层重叠区域相距有一距离。
在本发明较佳实施例中，此可改善阻抗匹配的打线垫结构为应用于高频电路的封装体结构，因此上述电子元件可为一芯片或是多层电路板。
在本发明较佳实施例中，芯片内的本发明的打线垫结构为具有三打线垫，其分别为第一打线垫、第二打线垫以及第三打线垫。而第一、第二以及第三打线垫分具有三个插塞部以及三个金属层，且第一打线垫的第一金属层、第二打线垫的第二金属层、第一打线垫的第二金属层、第二打线垫的第三金属层、第一打线垫的第三金属层依序延伸重叠，第三打线垫的第一金属层、第二打线垫的第二金属层、第三打线垫的第二金属层、第二打线垫的第三金属层、第三打线垫的第三金属层依序延伸重叠。
综合上述，本发明提供了一种可改善阻抗匹配的打线垫结构，期望通过打线垫结构的简单改良，以增加封装体结构中芯片与基板间回路的电容性，而使此回路的阻抗匹配最佳，封装体结构的电气特性更好。
附图说明
图1为射频电路的封装体结构的剖面图
图2为本发明较佳实施例的打线垫结构的上视图
图3为本发明较佳实施例的打线垫结构的剖面图
图4为图3的立体结构图；以及
图5、图6A以及图6B为图1封装体结构使用本发明打线垫结构前后其插入损耗、返回损耗的对照表及对照图
其中，附图标记说明如下：
100封装体结构
110芯片
112绝缘层
120、125、240、250金属线
127基板
130芯片垫
210-230打线垫
320-360金属层
365-373插塞部
M1-M6金属层
具体实施方式
本发明基于封装体结构中，芯片与基板间回路所对应的金属线截面积总和仍然过大，而高频封装体结构所表现出来的电气特性将属于高电感性以及高阻抗性，因此，高频封装体结构于高频工作时，会因回路间阻抗不匹配造成信号间的严重反射，导致封装体结构电气特性不佳。
而且，本发明基于以在封装体结构中芯片内以MIM制程设置NMOS晶体管或PMOS晶体管的方式来增加电气特性时，此设置方式由于其制程特殊，成本较高，且此设置方式还将使得封装体结构中芯片与基板回路频宽及准确性均无法广泛应用。
因此，本发明主要考虑改良封装体结构中于芯片上用以承接金属线的打线垫结构，期望将打线垫结构中与芯片内部多层金属板结构连接的金属层延伸，以通过至少两打线垫间金属层的面对面平行延伸且重叠，而等效形成平行电路板，并增加封装体结构中芯片与基板回路间的电容性，来达到增加封装体结构的电气特性。
为了使本发明的特征、目的及功能得到更进一步的认知与了解，现配合
附图详细说明如下：
请先参考图2，图2为本发明较佳实施例的打线垫结构的上视图。在图2中，芯片110上具有打线垫210-230，而芯片110与基板127间的金属线125、240、250，则分别通过打线垫220、210以及230与芯片内各层金属板电性连接。
请接着参考图3，图3为本发明较佳实施例的打线垫结构的剖面图。在图3中，打线垫210-230相邻且由芯片110表面310埋入至芯片110内部有一定深度，由芯片110表面310至芯片110内部的打线垫210-230结构可视芯片110的多层金属设置(芯片110为6层金属设计)而分别具有依序堆叠的金属(metal)部320-360以及插塞(plug)部365-373。
即，打线垫210由芯片110表面310至芯片110内依序具有插塞部365、金属层320、插塞部366、金属层330、插塞部367以及金属层340。打线垫220由芯片110表面310至芯片110内依序具有金属层345、插塞部368、金属层349、插塞部369、金属层348以及插塞部370。打线垫230由芯片110表面310至芯片110内依序具有插塞部371、金属层349、插塞部3372、金属层350、插塞部373以及金属层360。
而打线垫210的金属层320-340则分别作为与芯片110内第五金属层M5、第三金属层M3以及第一金属层M1耦接。打线垫220的金属层345-348则分别作为与芯片110内第六金属层M6、第四金属层M4以及第二金属层M2耦接。打线垫230的金属层349-360则分别作为与芯片110内第五金属层M5、第三金属层M3以及第一金属层M1耦接。可同时参考图4，图4为图3的立体结构图。
其中，在此打线垫210-230结构中特别的是，打线垫210的金属层320-340与打线垫220的金属层345-348相互面对面平行延伸且互相重叠有一区域，且两打线垫210、220的金属层320-340、345-348分别两两将形成相距有一距离d的平行金属板结构380。因此，打线垫210-220问具有由金属层320、金属层347、金属层330、金属层348、金属层340依序排列的平行金属板结构380。其间并存有绝缘层(如硅氧化层)112
同理。打线垫220的金属层345-348与打线垫230的金属层349-360，相互面对面平行延伸且互相重叠有一区域，两打线垫220、230的金属层345-348、349-360分别两两将也形成相距有一距离d的平行金属板结构390。因此，打线垫220-230间具有由金属层349、金属层347、金属层350、金属层348、金属层360依序排列的平行金属板结构390。
由于两打线垫210、220、230的金属层320-360间将具有平行金属板结构380、390，因此当芯片110通过打线垫210-230的各金属层320-360传递信号至芯片110中的各金属层M1-M6时，本领域技术人员可知，打线垫210-230间所出现的平行金属板结构380、390将使得芯片110内回路的电容性增加。
因此，根据回路的阻抗匹配公式：
可知，图1现有技术的封装体结构100中芯片110与基板120间回路的高电感性可通过本发明打线垫210-230结构所呈现的高电容性而得到匹配。换句话说，芯片110与基板120间回路的阻抗(Z)即可通过本发明打线垫210-230结构所呈现的高电容性而趋于最佳值。
从实验数据亦可知，当图1封装体结构中芯片110使用本发明的打线垫210-230结构时，其电气表现，即介入损耗及返回损耗的表现，将趋于最佳值。请参考图5表格并对照图6A以及图6B，图5、图6A以及图6B为图1封装体结构100使用本发明打线垫210-230结构前后其插入损耗(S11)、返回损耗(S21)的对照表及对照图。
当封装体结构100使用本发明的打线垫210-230结构，且封装体结构110工作频率为2.4GHz时，其整体回路的返回损耗(S11)为-24.29dB，较使用前的-16.70dB下降了7.59dB，其整体回路的插入损耗(S21)为-0.11dB，较使用前的-0.18dB上升了0.07dB。而当封装体结构110工作频率为5.0GHz时，其整体回路的返回损耗(S11)为-13.24dB，较使用前的-10.24dB下降了3dB，其整体回路的插入损耗(S21)为-0.11dB，较使用前的-0.18dB上升了0.24dB。
因此，封装体结构100其整体回路在使用本发明的打线垫210-230结构之后，其整体回路的插入损耗(S21)下降，其整体回路的返回损耗(S11)提升。而插入损耗(S21)的下降将有助于封装体结构100的高频信号的完整传递以及能量损失降低。因此，使用本发明打线垫210-230结构后的封装体结构100的整体回路的返回损耗(S11)以及插入损耗(S21)分布将可趋于最佳化。
此外，若根据本发明两打线垫间出现有平行金属板结构的概念，本发明的打线垫结构将不仅能用于芯片上，还将可广泛运用于打线式的封装设计中。
综合上述，本发明提出一种可改善阻抗匹配的打线垫结构，通过两打线垫间金属层的面对面的平行延伸而形成平行金属板结构，以适当增加与打线垫连接回路的电容性。因此，当本发明打线垫结构运用于封装设计时，不但能使封装体结构其整体回路的阻抗得以匹配，且其整体回路的插入损耗、返回损耗分布将可趋于最佳化，而具有较佳的电气特性。
以上所述仅为本发明的较佳实施例，当不能以之限制本发明的范围。即大凡依本发明的权利要求所做的均等变化及修饰，仍将不失本发明的要义所在，即不脱离本发明的精神和范围，因此都应视为本发明的进一步实施状况。

Claims (8)

1.一种可改善阻抗匹配的打线垫结构，其特征在于，该打线垫结构为具有多层电性连接的一电子元件传送信号以及接地之用，其结构包括：
至少两打线垫，相邻且由该电子元件表面埋入至该电子元件内部有一深度，该两打线垫由该电子元件表面至内部可视其所需而具有依序堆叠的至少两个金属层以及插塞部，其中，该两打线垫至少分别有一金属层面对面平行延伸且互相重叠有一区域，且该两打线垫的金属层重叠区域相距有一距离。
2.如权利要求1所述的可改善阻抗匹配的打线垫结构，其特征在于，其中该电子元件为一芯片。
3.如权利要求1所述的可改善阻抗匹配的打线垫结构，其特征在于，其中该电子元件为一电路板。
4.如权利要求2所述的可改善阻抗匹配的打线垫结构，其特征在于，其中该芯片具有六层板。
5.如权利要求4所述的可改善阻抗匹配的打线垫结构，其特征在于，其中该结构具有三打线垫，其分别为一第一打线垫、第二打线垫以及第三打线垫。
6.如权利要求5所述的可改善阻抗匹配的打线垫结构，其特征在于，其中该第一、该第二以及该第三打线垫分别具有三个插塞部以及三个金属层，且该第一打线垫的第一金属层、该第二打线垫的第二金属层、该第一打线垫的第二金属层、该第二打线垫的第三金属层、第一打线垫的第三金属层依序延伸重叠，该第三打线垫的第一金属层、该第二打线垫的第二金属层、该第三打线垫的第二金属层、该第二打线垫的第三金属层、该第三打线垫的第三金属层依序延伸重叠。
7.一种可改善阻抗匹配的打线垫结构，其特征在于，该打线垫结构为具有多层电性连接的一电子元件传送信号以及接地之用，其结构主要特征为：
两打线垫间额外具有相互平行、互相重叠且不连接的金属板结构。
8.如权利要求7所述的可改善阻抗匹配的打线垫结构，其特征在于，其中该两打线垫相邻且由该电子元件表面埋入至该电子元件内部有一深度，该两打线垫由该电子元件表面至内部可视其所需而具有依序堆叠的多个金属层以及插塞部，其中，该两打线垫至少分别有一金属层面对面平行延伸且互相重叠有一区域，且该两打线垫的金属层重叠区域相距有一距离。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102779802A (zh) * 2012-07-13 2012-11-14 日月光半导体制造股份有限公司 半导体封装结构及其制造方法
CN102779802B (zh) * 2012-07-13 2015-12-16 日月光半导体制造股份有限公司 半导体封装结构及其制造方法

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