CN1482668A - Method for forming clearance wall between grid and capacitor - Google Patents
Method for forming clearance wall between grid and capacitor Download PDFInfo
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- CN1482668A CN1482668A CNA021316759A CN02131675A CN1482668A CN 1482668 A CN1482668 A CN 1482668A CN A021316759 A CNA021316759 A CN A021316759A CN 02131675 A CN02131675 A CN 02131675A CN 1482668 A CN1482668 A CN 1482668A
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Abstract
A method for making the clearance wall between the grid electrode and the capacitor comprising, forming a superfissure insulation area on the substrate, which forms a pad layer of oxide, an etching interruption layer and a first oxide layer, etching a depressed area downwards, depositing a first conductor layer on the depressed inner wall, removing the first oxide layer and the etching interruption layer, forming in turn a dielectric layer, a second conductor layer, a first silicon nitride layer and a nitrogen silicon oxide layer on the superfissure insulating area and the active area, etching the active region downwards to the pad oxide layer.
Description
Technical field
The invention relates to a kind of manufacture method of semiconductor device, and particularly relevant for a kind of method of making in the semiconductor device between the clearance wall of grid and electric capacity.
Background technology
When semi-conductive technology is constantly progressive, it is a kind of inexorable trend that internal memory manufacturing and logic manufacturing are combined.Be used in the integral chip (System on Chip) under 1T-SRAM (the containing a transistorized SRAM) situation that comes to this.In 1T-SRAM, in order to reach the purpose that takies minimum area, employed design be with electric capacity be embedded in the shallow-channel insulation district (Shallow Trench Insulator, STI) and character line (Word line) just be pressed on the electric capacity.Just because such design, just must overcome the high stepped design of grid (High step height for transistor gate) with and grid and electric capacity between the situation that is easy to leak electricity.As shown in Figure 1, below be the incidental shortcoming of this kind design:
1, adhere to badly between electrode 30 and the anti-reflecting layer 40 (ARC layer) on the electric capacity, cause when gate oxidation is made, top electrode 30 oxidations generate silica.Fig. 3 a-3d is the electron microscope picture of known manufacturing, and wherein Fig. 3 c and Fig. 3 d are respectively the thin portion enlarged drawing of Fig. 3 a and Fig. 3 b, and arrow indication part is the silica that the top electrode oxidation generates among the figure.
2, because by the down etched sidewall 80 of anti-reflecting layer 40, all can't be vertical upstanding wall, behind etching of silicon nitride (Silicon Nitride), left silicon nitride gap wall 50 (Silicon Nitride Spacer) Chang Wufa covers top electrode 30.Fig. 2 a-2c is the electron microscope picture of known manufacturing, and wherein Fig. 2 b and 2c are the thin portion enlarged drawings of Fig. 2 a, distinguish the boundary of grid and silicon nitride sideshake wall among Fig. 2 b especially with white dashed line, and silicon nitride gap wall does not cover top electrode fully.
3, at the other silica sideshake wall 60 (Oxide Spacer) of silicon nitride sideshake wall 50, repeatedly gate oxidation manufacturing and a large amount of consumption of Chang Yinwei, in Fig. 2 b, silica sideshake wall full consumption totally, only remaining silicon nitride gap wall.
4, the 2nd adds that the 3rd shortcoming causes silicon nitride sideshake wall 50 and silica sideshake wall 60 all effectively insulated gate electrode 70 and top electrode 30, just leaks electricity, even situation of short circuit easily.
The present invention is pressed in design on the electric capacity in order to overcome character line, and clearance wall can't effectively completely cut off the situation of electrode on grid and the electric capacity.Address this problem, character line (gate trace) just can Bu Xu be Yaoed Around and is crossed electric capacity, thereby has shortened the length of character line, makes that semiconductor subassembly speed is faster, also effectively reduces chip area.
Summary of the invention
Therefore purpose of the present invention is exactly that a kind of manufacture method that forms the clearance wall of grid and electric capacity is being provided, when making in the semiconductor device gate trace in order to overcome, the clearance wall that meets with can't completely cut off the shortcoming of gate trace and electric capacity fully.
Another purpose of the present invention is to propose the structure of the clearance wall of a kind of isolated gate line and an electric capacity.
According to the present invention, a kind of manufacture method that forms the clearance wall of grid and electric capacity, this method comprises at least: form a shallow-channel insulation district in the semiconductor base material; Form a lower electrode layer, one first dielectric layer, a upper electrode layer and one second dielectric layer successively in this shallow-channel insulation district; Cover an oxide layer and one the 3rd dielectric layer successively in the sidewall and the top of this upper electrode layer; Etching the 3rd dielectric layer forms clearance wall.Wherein this second dielectric layer is the silicon nitride layer that forms with low-pressure chemical vapor deposition.This oxide layer is that the mode with low-pressure chemical vapor deposition forms.The 3rd dielectric layer is the silicon nitride layer that forms with low-pressure chemical vapor deposition.
According to the present invention, crack wall construction between a kind of formation one gate trace and the electric capacity, this structure comprises at least: a capacitance structure is positioned on the one side in shallow-channel insulation district; One L type clearance wall is positioned at the sidewall and the top, this shallow-channel insulation district of this capacitance structure; And one second clearance wall be positioned at the clearance wall of this L type one side away from this capacitance structure, and this L type clearance wall and second clearance wall combine between the crack wall construction between this capacitance structure and this gate trace.Wherein this L type clearance wall is the silicon nitride layer that forms with low-pressure chemical vapor deposition.This second clearance wall is the oxide layer that forms with low-pressure chemical vapor deposition.
According to a preferred embodiment of the present invention, the manufacture method step of the clearance wall of this kind formation grid and electric capacity is as follows: form the shallow-channel insulation district on semiconductor substrate, and form a pad oxide thereon successively, one etching stopping layer and first oxide layer, in active area and adjacent shallow-channel insulation district thereof, cover photoresist layer, expose predetermined electric capacity and make the zone, etch a sunk area downwards and remove photoresist layer, it is conformal in this depression inwall to deposit first conductor layer, remove first oxide layer and etching stopping layer, and form dielectric layer successively, second conductor layer, first silicon nitride layer, silicon oxynitride layer covers on shallow-channel insulation district and the active area, on this active area, be etched down to pad oxide, form second silicon nitride layer and second oxide layer successively, elder generation's etching second oxide layer, etching second silicon nitride layer forms the clearance wall that silicon nitride and oxide layer combine at last again, remove this pad oxide, form a grid oxic horizon on active area, form gate trace at last.
According to above preferred embodiment of the present invention; second oxide layer can be used as the protective layer of etching second silicon nitride layer; the silicon nitride layer clearance wall of avoiding covering second conductor layer is by over etching, thereby the silicon nitride layer clearance wall could cover second conductor layer fully, reaches the purpose of insulation.
The accompanying drawing simple declaration
State with other purpose, feature and advantage and can become apparent on the present invention for allowing, a preferred embodiment cited below particularly, and conjunction with figs. are described in detail below:
Fig. 1 is the schematic diagram that shows known manufacture process;
Fig. 2 a-2c is the electron microscope picture of known manufacture process;
Fig. 3 a-3d is the electron microscope picture of known manufacture process;
Fig. 4-the 12nd shows the manufacturing step generalized section according to a preferred embodiment of the present invention; And
Figure 13 a-13c is the electron microscope picture of finishing according to a preferred embodiment of the present invention.
Specific embodiment
Please refer to Fig. 4-the 12nd, show the manufacturing step generalized section according to a preferred embodiment of the present invention, Figure 13 a-13c is the electron microscope picture of finishing according to a preferred embodiment of the present invention.Below conjunction with figs. and narration are illustrated the manufacturing step of preferred embodiment of the present invention.
As shown in Figure 4, and formation shallow-channel insulation district 15 on the semiconductor base material (ShallowTrench Insulator, the STI) zone that makes as 1T-SRAM electric capacity, and be separated out active region 75 (Active Area).As shown in Figure 5; deposition pad oxide 18 (Pad Oxide) on semiconductor substrate; be used for protecting the semiconductor silicon base material, deposition etch stops layer 22 (Stop layer) and oxide layer 24 (Oxide) successively again, and etching stopping layer can be silicon nitride or silicon oxynitride.
Next manufacturing step as shown in Figure 6, covers photoresist layer in active area 75 and adjacent shallow-channel insulation district 15 thereof, expose predetermined electric capacity and make the zone.The shallow-channel insulation district that exposes is carried out etching, form the manufacturing depression of electric capacity.Next deposited capacitances bottom electrode 20 (Bottom electrode), and removing the bottom electrode that covers on the oxide layer 24 with the mode of cmp (Chemical MechanicalPolish), the material of bottom electrode 20 can be polysilicon (Polysilicon) or other conductive metal layer.
Next manufacturing step as shown in Figure 7, utilizes the mode of wet etching to remove oxide layer 24 and etching stopping layer 22 successively, and the etchant that removes oxide layer 24 can be hydrofluoric acid (HF), and removing etching stopping layer 22 can be hot phosphoric acid (H
3PO
4).
Next manufacturing step, as shown in Figure 8, electrode (Top Electrode) 30, silicon nitride layer 35 and anti-reflecting layer (Anti-Reflective Coating Layer on the dielectric layer 25 of deposited capacitances, the electric capacity successively, ARC Layer) 40, wherein dielectric layer 25 can be the double-decker of silica/silicon nitride or the three-decker of silicon oxide/silicon nitride/silicon oxide, top electrode 30 can be polysilicon or other conductive metal layer, and anti-reflecting layer 40 can be a silicon oxynitride.Be noted that especially; silicon nitride layer 35 is that the mode of using low-pressure chemical vapor deposition (LPCVD) forms; its function is to protect the polysilicon of top electrode 30 to prevent its oxidation; can overcome in the known technology; when forming grid oxic horizon; top electrode 30 is understood because adhere to defective tightness with anti-reflecting layer 40, and makes the polysilicon oxidation of top electrode 30, and this is one of characteristics of the present invention.
Next manufacturing step as shown in Figure 9, is etched down to pad oxide 18 from anti-reflecting layer 40 above this active area, next form silicon nitride layer 50 and oxide layer 60 successively with low-pressure chemical vapor deposition again.
Next manufacturing step, as shown in figure 10, selective etch oxide layer 60 must stop when etching into silicon nitride layer 50, can form oxide layer clearance wall 65 after etching is finished.Next silicon-nitride selective etching 50 again must stop when etching into pad oxide 18, can form silicon nitride layer clearance wall 55 as shown in figure 11 after etching is finished.
After being noted that especially the manufacturing sequence place different with known technology that the present invention forms clearance wall is deposited silicon nitride layer 50 and oxide layer 60, carry out twice selective etch again.Advantage is the protective layer that oxide layer 60 can be used as etches both silicon nitride layer 50, and the silicon nitride layer clearance wall 55 of the electrode 30 of avoiding being incumbent on is by over etching.Therefore, use the formed silicon nitride layer clearance wall of the present invention electrode 30 that could be incumbent on fully, reach the purpose of insulation.Figure 13 a-c is the electron microscope picture that a preferred embodiment of the present invention is finished, and Fig. 2 b of comparison diagram 13b and known technology just can clearly find out and use effect of the present invention.
To specify in addition be and known semiconductor manufacturing in clearance wall inequality be that the shape of the formed silicon nitride layer clearance wall of the present invention is the L type, as the SiN among label among Figure 12 55 and Figure 13 b.
Last step as shown in figure 12, removes pad oxide 18, then forms grid oxic horizon 85, forms gate trace 70 at last.
By the invention described above preferred embodiment as can be known; use the present invention and have following advantage: 1. the polysilicon of protection top electrode 30 prevents its oxidation; can overcome when forming grid oxic horizon; top electrode 30 is understood because adhere to defective tightness with anti-reflecting layer 40, and makes the shortcoming of the polysilicon oxidation of top electrode 30.2. oxide layer 60 can be used as the protective layer of etches both silicon nitride layer 50, and the silicon nitride layer clearance wall 55 of the electrode 30 of avoiding being incumbent on is by over etching, thereby the silicon nitride layer clearance wall electrode 30 that could be incumbent on fully, reaches the purpose of insulation.3. because the 1.th and 2. advantage, character line (gate trace) just can Bu Xu be Yaoed Around and is crossed electric capacity, thereby has shortened the length of character line, makes that semiconductor subassembly speed is faster, and can reduce chip area.
Though the present invention discloses as above with a preferred embodiment; right its is not in order to limit the present invention; anyly have the knack of this technical staff; without departing from the spirit and scope of the present invention; when can being used for a variety of modifications and variations, so protection scope of the present invention is as the criterion when looking accompanying the claim person of defining.
Claims (7)
1, a kind of manufacture method that forms the clearance wall of grid and electric capacity, this method comprises at least:
Form a shallow-channel insulation district in the semiconductor base material;
Form a lower electrode layer, one first dielectric layer, a upper electrode layer and one second dielectric layer successively in this shallow-channel insulation district;
Cover an oxide layer and one the 3rd dielectric layer successively in the sidewall and the top of this upper electrode layer;
Etching the 3rd dielectric layer forms clearance wall.
2, the method for claim 1, wherein this second dielectric layer is the silicon nitride layer that forms with low-pressure chemical vapor deposition.
3, the method for claim 1, wherein this oxide layer is that mode with low-pressure chemical vapor deposition forms.
4, the method for claim 1, wherein the 3rd dielectric layer is the silicon nitride layer that forms with low-pressure chemical vapor deposition.
5, crack wall construction between a kind of formation one gate trace and the electric capacity, this structure comprises at least:
One capacitance structure is positioned on the one side in shallow-channel insulation district;
One L type clearance wall is positioned at the sidewall and the top, this shallow-channel insulation district of this capacitance structure; And
One second clearance wall is positioned at the clearance wall of this L type one side away from this capacitance structure, and this L type clearance wall and second clearance wall combine between the crack wall construction between this capacitance structure and this gate trace.
6, structure as claimed in claim 5, wherein this L type clearance wall is the silicon nitride layer that forms with low-pressure chemical vapor deposition.
7, structure as claimed in claim 5, wherein this second clearance wall is the oxide layer that forms with low-pressure chemical vapor deposition.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021316759A CN1294643C (en) | 2002-09-11 | 2002-09-11 | Method for forming clearance wall between grid and capacitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021316759A CN1294643C (en) | 2002-09-11 | 2002-09-11 | Method for forming clearance wall between grid and capacitor |
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| Publication Number | Publication Date |
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| CN1482668A true CN1482668A (en) | 2004-03-17 |
| CN1294643C CN1294643C (en) | 2007-01-10 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB021316759A Expired - Lifetime CN1294643C (en) | 2002-09-11 | 2002-09-11 | Method for forming clearance wall between grid and capacitor |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110391233A (en) * | 2018-04-17 | 2019-10-29 | 联华电子股份有限公司 | Semiconductor element and preparation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2875733B2 (en) * | 1994-02-15 | 1999-03-31 | 松下電子工業株式会社 | Method for manufacturing semiconductor device |
| US6190977B1 (en) * | 1999-04-30 | 2001-02-20 | Texas Instruments - Acer Incorporated | Method for forming MOSFET with an elevated source/drain |
| US6291307B1 (en) * | 1999-08-06 | 2001-09-18 | Chartered Semiconductor Manufacturing Ltd. | Method and structure to make planar analog capacitor on the top of a STI structure |
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2002
- 2002-09-11 CN CNB021316759A patent/CN1294643C/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110391233A (en) * | 2018-04-17 | 2019-10-29 | 联华电子股份有限公司 | Semiconductor element and preparation method thereof |
| CN110391233B (en) * | 2018-04-17 | 2022-10-14 | 联华电子股份有限公司 | Semiconductor element and manufacturing method thereof |
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| Publication number | Publication date |
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| CN1294643C (en) | 2007-01-10 |
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