CN1477919A - Method for designing printed circuit board and its equipment - Google Patents
Method for designing printed circuit board and its equipment Download PDFInfo
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- CN1477919A CN1477919A CNA021299463A CN02129946A CN1477919A CN 1477919 A CN1477919 A CN 1477919A CN A021299463 A CNA021299463 A CN A021299463A CN 02129946 A CN02129946 A CN 02129946A CN 1477919 A CN1477919 A CN 1477919A
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Abstract
The method for designing printed circuit board includes the following steps: firstly, inputting design file of printed circuit board; then according to the condition of every device in the design file building device model; utilizing device model to make signal quality and time sequence automatic checkup and imitation of design file; finally outputting signal quality and time sequence automatic checkup and imitation report. The equipment includes input module for inputting design file of said printed circuit board, device model library module for storing device model, automatic checkup imitation module, output module and other various submodules.
Description
Technical Field
The invention relates to the field of printed circuit board design, in particular to a method and a device for printed circuit board design.
Background
With the development of the information industry, Printed Circuit boards (Printed Circuit boards) are used more and more widely, and the layout of the wiring and the component position on the Printed Circuit Board is more and more complicated, and the increase of the complexity naturally increases the chance of the signal quality or timing error of the Printed Circuit Board. Therefore, in order to ensure the quality of the printed circuit board, it is necessary to verify whether the signal quality and timing sequence in the printed circuit board after design meet the requirements, so as to quickly correct the errors and problems in the design.
The prior art scheme is as follows: and (3) checking and simulating the signal quality or the time sequence of the single network by using a rule checking function or a simulation tool attached to the printed circuit board design tool software. In the case of multiple networks, the networks are individually verified by manual work using rule checking functions or simulation tools attached to the printed circuit board design tool software.
It is clear that the prior art solutions have a number of drawbacks, in particular as follows:
1. the operation is complex, and for the situation of multiple networks, one network needs to be checked and simulated, so that the comprehensiveness is difficult to ensure;
2. the function is single, and the simulation and the check in the prior art can only realize point-to-point simulation;
3. the cost is high, and a large amount of manpower and time are consumed.
Disclosure of Invention
The invention provides a method and a device for designing a printed circuit board, which can realize automatic inspection and simulation of signal quality and time sequence.
To achieve the above object, the method for printed circuit board design of the present invention comprises the steps of:
a. inputting a printed circuit board design file;
b. constructing a device model according to the condition of each device in the input printed circuit board design file;
c. automatically checking and simulating the quality and the time sequence of the signal by using a device model;
d. and outputting a report of automatic signal inspection and simulation.
Wherein, the constructing the device model in the step b specifically comprises:
b1, checking whether a corresponding device model exists in the device model library according to the condition of each device in the input printed circuit board design file;
b2, if existing, not constructing the device model, otherwise constructing the device model.
The data used in the process of constructing the device model are as follows: simulation data, level data, timing data, signal operation data, and other special data.
The simulation of the signal quality in the step c specifically includes the following steps:
c11, firstly extracting a network topological structure designed by the printed circuit board;
c12, calling a corresponding device model, and obtaining the signal quality condition of the load end through simulation according to the simulation data and the signal working data in the device model;
c13, finally obtaining the violation condition according to the level data in the data.
In the step c, in addition to the simulation of the signal quality, the simulation of the signal crosstalk is also performed, and the method specifically includes:
c21, firstly finding out signal pairs with longer parallel routing and smaller spacing distance;
c22, and then calculating the amplitude of the crosstalk by using simulation data and signal working data in the device model.
The checking of the signal timing sequence in the step c specifically includes:
c31, firstly, calculating the time delay of the signal according to the time sequence data of the output device and then according to the network topology structure designed by the printed circuit board to obtain the time sequence condition of the load end;
and c32, finally, comparing the time sequence data of the load end device to judge whether the requirements can be met. For a complex network topology, the timing condition of a load end is determined through signal simulation.
In addition, in the step c, in addition to performing automatic inspection and simulation of signal quality and timing, simulation and timing inspection are performed on signals of the cross-drive type device according to other special data of the device model.
The apparatus for printed circuit board design of the present invention is characterized in that the apparatus comprises: the device comprises an input module for inputting a printed circuit board design file, a device model library module for storing a device model, an automatic inspection simulation module for automatically inspecting and simulating signal quality and time sequence, and an output module for outputting an automatic inspection and simulation report; the automatic checking simulation module comprises: the device model management submodule, the signal quality simulation submodule and the time sequence check submodule are used for generating, modifying, deleting and calling the device model. Wherein:
the design file of the printed circuit board is firstly input by the input module, then the generation, modification, deletion and calling operations of the device model are carried out in the device model library module by the device model management submodule according to the condition of each device in the input design file of the printed circuit board, then the signal quality and signal time sequence of each device model are checked and simulated by the signal quality simulation submodule and the time sequence checking submodule, and finally the signals are sent to the output module to output an automatic checking and simulation report.
Due to the adoption of the technical scheme, the invention has the following advantages:
1. the signal quality and the time sequence can be automatically checked and simulated, and the working efficiency is greatly improved;
2. through automatic inspection and simulation, errors in signal quality and time sequence in PCB design can be quickly found, and comprehensiveness is guaranteed;
3. the automatic simulation of signal crosstalk and the timing sequence check and simulation of the cross-drive device can be carried out;
4. the compatibility is strong, and various printed circuit board design software can be embedded, and the software can be separated from the printed circuit board design software for independent use.
The invention is described in detail below with reference to the figures and specific embodiments.
Drawings
FIG. 1 is a system architecture diagram of an apparatus for printed circuit board design of the present invention;
FIG. 2 is a flow chart of a method of the present invention for printed circuit board design;
FIG. 3 is a flow chart of the present invention for constructing a device model in step b of the printed circuit board design method;
FIG. 4 is a flow chart of a simulation of signal quality in step c of the printed circuit board design method of the present invention;
FIG. 5 is a flow chart of the present invention for simulating signal crosstalk in step c of the printed circuit board design method;
FIG. 6 is a flow chart of the present invention for checking the timing of signals in step c of the printed circuit board design method;
detailed description of the invention
Referring to fig. 1 to 6, the system architecture diagram of the apparatus for printed circuit board design according to the present invention includes: an input module (21) for inputting a printed circuit board design file, a device model library module (23) for storing a device model, an automatic inspection simulation module (22) for automatically inspecting or simulating signal quality and time sequence, and an output module (24) for automatically inspecting and outputting a simulation report; the automatic inspection simulation module comprises (22): a device model management submodule (25), a signal quality simulation submodule (26) and a timing inspection submodule (27) for generating, modifying, deleting and calling the device model; wherein,
the design file of the printed circuit board is firstly input by an input module (21), then the generation, modification, deletion and calling operations of a device model are carried out in a device model library module (23) by a device model management submodule (25) according to the condition of each device in the input design file of the printed circuit board, then a signal quality simulation submodule (26) and a time sequence check submodule (27) carry out signal quality and signal time sequence check and simulation on each network, and finally the design file is sent to an output module (24) to output an automatic check and simulation report.
When a designer needs to verify whether signal quality and timing in a printed circuit board meet requirements after designing the printed circuit board, more specifically, the method comprises the following steps:
first, inputting a printed circuit board design file. Namely, the printed circuit board design file is input to the automatic inspection simulation module (22) through the input module (21).
And secondly, constructing a device model according to each device condition in the input printed circuit board design file.
The device model contains Simulation data, supports Simulation models which are used more frequently in the current Simulation, such as SPICE (Simulation Program with Integrated Circuit kernel) or IBIS (I/O Buffer Information Specification) models, and further contains: level data, timing data, signal operation data, and other special data, wherein:
the level data refers to the level values and special requirements of input signals and output signals of pins of the chip, the maximum value, the minimum value and the typical value of the input and output levels of the pins can be obtained through the data, and sometimes the maximum value, the minimum value and the typical value can also be a reference value or a requirement index value of edge time (rising edge or falling edge) of the signals, so that whether the input and output levels have problems can be judged, wherein the special requirements refer to the requirements of signal edge monotonicity, burr width and the like, and are used for judging whether the signals have abnormal conditions such as monotonous edges or pulses and the like, for example, the requirements of clock signal edge monotonicity;
the timing data includes input timing and output timing requirements;
the signal operation data refers to some specific requirements of signal operation, such as the frequency of clock input, the pulse width of data signals, and the like;
the other special data is data such as DELAY and SKEW given to a drive device, for example, a bus driver, and is also included when another programmable device, for example, a CPLD (complex programmable Logic device), an FPGA (field programmable gate Array), or the like is used as a drive.
After a user inputs a printed circuit board design file into the automatic inspection simulation module (22) through the input module (21), the module accesses the component model library module (23) according to the condition of components in the printed circuit board design file, checks whether component models exist or not, and prompts the user to create models or import models from other places if the component models do not exist. For some programmable devices, such as CPLDs, FPGAs, etc., the user will be prompted to create a model of that portion of data without other special data. In addition, different working modes exist for some devices, a user is prompted to select one of the working modes or input the current signal working data; in addition, the user can also browse the device model library module (23) and can modify, delete, call and the like the device model data in the device model library module.
And thirdly, utilizing the device model to automatically check and simulate the signal quality and the time sequence. After the automatic inspection simulation module (22) finishes the inspection of the device model library module (23), the automatic inspection and simulation of signal quality and time sequence are carried out, namely: and checking and simulating signal quality and signal time sequence.
The simulation of the signal quality, first of all, the simulation submodule (26) of the signal quality extracts the network topological structure designed by the printed circuit board, such as driver, network routing, load and match, then transfer the model of the relevant driver and load from the device model library module (23), according to the simulation model data and the signal working data, the signal condition of the load end can be obtained through simulation analysis, and then according to the level data in the model, judge whether the violation condition exists.
The signal quality simulation submodule (26) also enables automatic simulation of signal crosstalk. Firstly, finding out signal pairs with longer parallel routing and smaller spacing distance, and then utilizing simulation data and signal working data in the device model library module (23) to calculate the amplitude of crosstalk.
And the signal time sequence is checked, namely firstly, the time sequence checking submodule (27) calculates the time delay of a signal according to the time sequence data of an output device and then according to a network topological structure designed by the printed circuit board to obtain the time sequence situation of a load end, and then the time sequence data of the load end device is compared to obtain whether the time sequence data can meet the requirement. For a complex network topology, such as a case with a plurality of loads, the timing condition of the load end is determined through signal simulation.
For some special driving devices, the devices are represented by other special data in the device model library, and corresponding time delay conditions are included. Through simulation and calculation, signal simulation and timing inspection across driving devices can be achieved.
And fourthly, outputting a signal automatic check and simulation report.
After the user finishes the checking and simulation of the signal quality and the signal time sequence, a relevant report including a checking result, a network name and the like is given through an output module (24), and in addition, parts which are not checked, such as statistical coverage rate and the like, are listed for the user to refer to.
Claims (9)
1. A method for printed circuit board design, the method comprising the steps of:
a. inputting a printed circuit board design file;
b. constructing a device model according to the condition of each device in the input printed circuit board design file;
c. utilizing the device model to automatically check and simulate the signal quality and the time sequence;
d. and outputting automatic inspection and simulation report of signal quality and time sequence.
2. The method for printed circuit board design according to claim 1, wherein the constructing of the device model in step b specifically comprises:
b1, checking whether a corresponding device model exists in the device model library according to the condition of each device in the input printed circuit board design file;
b2, if existing, not constructing the device model, otherwise constructing the device model.
3. A method for printed circuit board design according to claim 2, wherein the data used to construct the device model in step b is: simulation data, level data, time sequence data and signal working data.
4. The method for printed circuit board design according to claim 1, wherein the simulation of signal quality in step c specifically comprises the steps of:
c11, firstly extracting a network topological structure designed by the printed circuit board;
c12, calling a corresponding device model, and obtaining the signal quality condition of the load end through simulation according to the simulation data and the signal working data in the device model;
c13, finally obtaining the violation condition according to the level data in the data.
5. The method for printed circuit board design according to claim 4, wherein the simulation of signal quality in step c further comprises simulation of signal crosstalk, specifically comprising:
c21, firstly finding out signal pairs with longer parallel routing and smaller spacing distance;
c22, and then calculating the amplitude of the crosstalk by using simulation data and signal working data in the device model.
6. The method as claimed in claim 1, wherein the checking of the signal timing in step c specifically comprises:
c31, firstly, calculating the time delay of the signal according to the time sequence data of the output device and then according to the network topology structure designed by the printed circuit board to obtain the time sequence condition of the load end;
and c32, finally, comparing the time sequence data of the load end device to judge whether the requirements can be met. For a complex network topology, the timing condition of a load end is determined through signal simulation.
7. The method of claim 1, wherein obtaining the timing of the load side further comprises: if the network topology is complex, the timing condition of the load end is determined through signal simulation.
8. The method of claim 1, wherein said performing signal quality and timing automatic checks and simulations in step c further comprises: and according to other special data of the device model, signal simulation and timing inspection across the driving class devices are realized.
9. An apparatus for printed circuit board design, the apparatus comprising: the device comprises an input module for inputting a printed circuit board design file, a device model library module for storing a device model, an automatic inspection simulation module for automatically inspecting and simulating signal quality and time sequence, and an output module for outputting an automatic inspection and simulation report; the automatic checking simulation module comprises: the device model management submodule, the signal quality simulation submodule and the time sequence check submodule are used for generating, modifying, deleting and calling the device model; wherein,
the design file of the printed circuit board is firstly input by the input module, then the generation, modification, deletion and calling operations of the device model are carried out in the device model library module by the device model management submodule according to the condition of each device in the input design file of the printed circuit board, then the signal quality simulation submodule and the time sequence detection submodule carry out the detection and simulation of the signal quality and the signal time sequence of each network, and finally the printed circuit board design file is sent to the output module to output an automatic detection and simulation report.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02129946 CN1223246C (en) | 2002-08-23 | 2002-08-23 | Method for designing printed circuit board and its equipment |
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| CN 02129946 CN1223246C (en) | 2002-08-23 | 2002-08-23 | Method for designing printed circuit board and its equipment |
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100428676C (en) * | 2005-04-23 | 2008-10-22 | 华为技术有限公司 | Printing circuit-board parallel design system based on network and method therefor |
| CN100458800C (en) * | 2006-09-21 | 2009-02-04 | 华为技术有限公司 | Automatic construction system and method for electronic circuit design |
| CN101714010B (en) * | 2009-10-28 | 2012-05-23 | 龙芯中科技术有限公司 | Clock domain crossing timing simulation system and method |
| CN105005015A (en) * | 2015-04-23 | 2015-10-28 | 广西电网有限责任公司电力科学研究院 | Circuit fault simulation system based on hardware circuit fault injection |
| CN105404754A (en) * | 2015-12-09 | 2016-03-16 | 浪潮电子信息产业股份有限公司 | Method for evaluating SI signal quality based on POWER influence |
| CN106455324A (en) * | 2016-09-09 | 2017-02-22 | 郑州云海信息技术有限公司 | Method and system for generating topological structures |
| CN106682374A (en) * | 2017-03-17 | 2017-05-17 | 北京润科通用技术有限公司 | Analog simulation method and system of working time sequence |
| CN107180143A (en) * | 2017-06-16 | 2017-09-19 | 郑州云海信息技术有限公司 | A kind of analysis of encoding transmits topology, method and the PCB trace method of influence on signal |
| CN107688682A (en) * | 2016-12-23 | 2018-02-13 | 北京国睿中数科技股份有限公司 | A kind of method that circuit topology is extracted using timing path |
| CN109299534A (en) * | 2018-09-20 | 2019-02-01 | 深圳市博科技股份有限公司 | A kind of modeling method and device of printed circuit board |
-
2002
- 2002-08-23 CN CN 02129946 patent/CN1223246C/en not_active Expired - Fee Related
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100428676C (en) * | 2005-04-23 | 2008-10-22 | 华为技术有限公司 | Printing circuit-board parallel design system based on network and method therefor |
| CN100458800C (en) * | 2006-09-21 | 2009-02-04 | 华为技术有限公司 | Automatic construction system and method for electronic circuit design |
| CN101714010B (en) * | 2009-10-28 | 2012-05-23 | 龙芯中科技术有限公司 | Clock domain crossing timing simulation system and method |
| CN105005015A (en) * | 2015-04-23 | 2015-10-28 | 广西电网有限责任公司电力科学研究院 | Circuit fault simulation system based on hardware circuit fault injection |
| CN105404754A (en) * | 2015-12-09 | 2016-03-16 | 浪潮电子信息产业股份有限公司 | Method for evaluating SI signal quality based on POWER influence |
| CN106455324A (en) * | 2016-09-09 | 2017-02-22 | 郑州云海信息技术有限公司 | Method and system for generating topological structures |
| CN107688682A (en) * | 2016-12-23 | 2018-02-13 | 北京国睿中数科技股份有限公司 | A kind of method that circuit topology is extracted using timing path |
| CN106682374A (en) * | 2017-03-17 | 2017-05-17 | 北京润科通用技术有限公司 | Analog simulation method and system of working time sequence |
| CN107180143A (en) * | 2017-06-16 | 2017-09-19 | 郑州云海信息技术有限公司 | A kind of analysis of encoding transmits topology, method and the PCB trace method of influence on signal |
| CN109299534A (en) * | 2018-09-20 | 2019-02-01 | 深圳市博科技股份有限公司 | A kind of modeling method and device of printed circuit board |
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| CN1223246C (en) | 2005-10-12 |
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