CN1223246C - Method for designing printed circuit board and its equipment - Google Patents
Method for designing printed circuit board and its equipment Download PDFInfo
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- CN1223246C CN1223246C CN 02129946 CN02129946A CN1223246C CN 1223246 C CN1223246 C CN 1223246C CN 02129946 CN02129946 CN 02129946 CN 02129946 A CN02129946 A CN 02129946A CN 1223246 C CN1223246 C CN 1223246C
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Abstract
The present invention relates to a method and a device for designing a printed circuit board, which comprises the following steps that firstly, a design file of a printed circuit board is input; then, according to the condition of each component in the input design file of the printed circuit board, component models are structured; next, the component models are utilized to carry out the automatic check and imitation of signal quality and time sequence for the design file of the printed circuit board; finally, a report for the automatic check and imitation of signal quality and time sequence is output. The device comprises an input module, a component model library module, an automatic check and imitation module and an output module, wherein the input module is used for inputting the design file of the printed circuit board, the component model library module is used for storing the component models, the automatic check and imitation module is used for carrying out the automatic check and imitation of signal quality and time sequence for the design file of the printed circuit board, and the output module is used for outputting the report for the automatic check and imitation of signal quality and time sequence. The automatic check and imitation module comprises a sub module for component model management, a sub module for signal quality and imitation and a sub module for time sequence check, which are used for generating, modifying, deleting and recalling the component models.
Description
Technical field
The present invention relates to the PCB design field, relate to a kind of method and device that is used for PCB design specifically.
Background technology
Continuous development along with information industry, the application of printed circuit board (PCB) (Printed Circuit Board) also more and more widely, the design of the wiring on the printed circuit board (PCB), position of components layout also becomes increasingly complex, and the increase nature of complexity will make printed circuit board signal quality or sequential wrong chance increase occur.Therefore in order to guarantee the quality of printed circuit board (PCB), whether the signal quality and the sequential that just press for printed circuit board (PCB) the inside, checking design back meet the requirements, to revise mistake and the problem that exists in the design apace.
The prior art scheme is: use regular audit function or emulation tool subsidiary in the PCB design tool software, at the signal quality or the sequential of single network check, emulation.And for the situation of a plurality of networks, then be by manually going to use PCB design tool software subsidiary regular audit function or emulation tool that network is verified one by one.
Clearly, the prior art scheme has a lot of shortcomings, and is specific as follows:
1, complicated operation for the situation of many networks, need be checked and emulation one by one, is difficult to guarantee comprehensive;
2, function singleness, the emulation of prior art and inspection are merely able to realize point-to-point emulation;
3, cost is very high, expends great amount of manpower and time.
Summary of the invention
The invention provides a kind of method that is used for PCB design and device that signal quality and sequential are carried out automatic inspection and emulation can realized.
For achieving the above object, the method that is used for PCB design of the present invention comprises following steps:
A, infput sheet design document;
B, according to the input the PCB design file in each device situation, the structure device model;
C, utilize device model, carry out the emulation of signal quality and the automatic inspection of sequential;
The emulation of d, quality of output signals and the automatic inspection of sequential;
Wherein, the emulation of the signal quality among the described step c specifically may further comprise the steps:
C11, at first extract the network topology structure of PCB design;
C12, secondly call the corresponding devices model,, obtain the signal quality situation of load end by emulation according to emulated data and signal operational data wherein;
C13, last basis level data wherein obtain situation in violation of rules and regulations;
The inspection of the signal sequence among the described step c specifically comprises:
C31, at first according to the time series data of output device, then according to the network topology structure of PCB design, the time delay of signal calculated obtains the sequential situation of load end;
C32, contrast the time series data of load end device at last, judge whether and to meet the demands.For the network topology structure of complexity, determine the sequential situation of load end by signal simulation.
Structure device model among the described step b specifically comprises:
B1, according to each device situation in the PCB design file of input, check in the device model library whether have the corresponding devices model;
B2, if exist, then no longer construct device model, otherwise the structure device model.
The employed data of structure device model described in the step b have: emulated data, level data, time series data, signal operational data.
The emulation of the signal quality among the described step c also further comprises the emulation of signal cross-talk, specifically comprises:
C21, at first find out and walking line signal long, that spacing distance is less right;
C22, utilize emulated data, signal operational data in the device model then, calculate the amplitude of crosstalking.
The described sequential situation that obtains load end also comprises: if for the network topology structure of complexity, determine the sequential situation of load end by signal simulation.
Carry out signal quality and sequential automatic inspection and emulation described in the step c also further comprise: according to other special datas of device model, realize striding signal simulation and the sequential inspection that drives the class device.
A kind of device that is used for PCB design comprises: be used for PCB design file input input module, be used for the memory device model the device model library module, be used to carry out signal quality and sequential automatic inspection and emulation the automatic inspection emulation module, be used for the output module of automatic inspection and simulation report output; Described automatic inspection emulation module comprises: the generation, modification, deletion, the device model management submodule of call operation, signal quality emulation submodule, the sequential that are used to carry out device model are checked submodule; Wherein,
The PCB design file is earlier by after the input module input, again through device model management submodule according to the PCB design file of input in each device situation, in the device model library module, carry out generation, modification, deletion, the call operation of device model, check that by signal quality emulation submodule and sequential submodule carries out the inspection and the emulation of signal quality and signal sequence to each network then, deliver to output module output automatic inspection and simulation report at last.
Because the present invention adopts above-mentioned technical scheme, so have following advantage:
1, can carry out signal quality and sequential automatic inspection and emulation, improve operating efficiency greatly;
2, through automatic inspection and emulation, can find the mistake that signal quality and sequential aspect exist in the PCB PCB design fast, guaranteed comprehensive;
3, can carry out the automatic simulation of signal cross-talk, and stride sequential inspection and the emulation that drives the class device;
4, compatible strong, can either embed multiple PCB design software, can break away from these softwares again, the independent use.
Describe the present invention in detail below in conjunction with the drawings and specific embodiments.
Description of drawings
Fig. 1 is the system architecture diagram that the present invention is used for the device of PCB design;
Fig. 2 is the flow chart that the present invention is used for method for designing printed circuit board;
Fig. 3 is the flow chart that the present invention is used for the structure device model of method for designing printed circuit board step b;
Fig. 4 is that the present invention is used for the flow chart of method for designing printed circuit board step c to the emulation of signal quality;
Fig. 5 is that the present invention is used for method for designing printed circuit board step c carries out emulation to signal cross-talk flow chart;
Fig. 6 is that the present invention is used for the flow chart that method for designing printed circuit board step c checks signal sequence;
Specific implementation
Please refer to Fig. 1 to Fig. 6, the present invention is used for the system architecture diagram of the device of PCB design, and this device comprises: be used for PCB design file input input module (21), be used for the memory device model device model library module (23), be used to carry out signal quality and sequential automatic inspection or emulation automatic inspection emulation module (22), be used for the output module (24) of automatic inspection and simulation report output; Described automatic inspection emulation module comprises (22): the generation, modification, deletion, the device model management submodule (25) of call operation, signal quality emulation submodule (26), the sequential that are used to carry out device model are checked submodule (27); Wherein,
The PCB design file is earlier by after input module (21) input, again through device model management submodule (25) according to the PCB design file of input in each device situation, in device model library module (23), carry out generation, modification, deletion, the call operation of device model, check that by signal quality emulation submodule (26) and sequential submodule (27) carries out the inspection and the emulation of signal quality and signal sequence to each network then, deliver to output module (24) output automatic inspection and simulation report at last.
When the designer after design finishes printed circuit board (PCB), need the signal quality and the sequential of checking printed circuit board (PCB) the inside whether to meet the requirements, more specifically, it comprises following steps:
The first, infput sheet design document.Promptly the PCB design file is inputed to automatic inspection emulation module (22) by input module (21).
The second, according to each device situation in the PCB design file of input, the structure device model.
This device model has comprised emulated data, support the simulation model that present emulation is used often, the simulated program of lsi core) or IBIS (I/O Buffer Information Specification: input and output buffer information specification) model as SPICE (Simulation Program with Integrated Circuit Emphasis:, also comprise in addition: level data, time series data, signal operational data and other special datas, wherein:
Level data is meant input signal and the output signal level value and the specific (special) requirements of the pin of chip, can obtain the maximum of level of the input and output of pin by these data, minimum value and representative value, sometimes also can be the desired value that requires of reference value or edges of signals time (rising edge or trailing edge), so just can judge whether the input and output level has problems, wherein said specific (special) requirements refers to signal edge monotonicity, requirements such as burr width, be used for judging whether have these abnormal conditions such as the not dull or pulse in edge in the signal, such as the requirement of clock edges monotonicity;
Time series data comprises input timing and output timing requirement;
The signal operational data is meant some specific requirements of signal work, such as the frequency of clock input, the pulse duration of data-signal etc.;
Other special datas are meant at driving element, as bus driver, the DELAY that provides (time delay), SKEW data such as (deviations), CPLD), FPGA (Field Programmable Graph Array: when using as driver, also possess these data field programmable gate array) etc. other programming device such as CPLD (Complex Programmab1eLogic Dvice:.
After the user imports automatic inspection emulation module (22) with the PCB design file by input module (21), this module is according to the device situation in the PCB design file, go to visit device model library module (23), and whether the device model of checking wherein exists, if there is no, prompting user model of creation is perhaps from other local models that imports.For some programming devices, such as CPLD, FPGA etc. will point out the user to create the model of this partial data when not having other special datas.Have the different operating mode for some device in addition, it is wherein a kind of to point out the user to select, perhaps import present signal operational data; The user also can browse this device model library module (23) in addition, can operation such as make amendment, deletes, call to the device model data of the inside.
Three, utilize device model, carry out signal quality and sequential automatic inspection and emulation.Behind automatic inspection emulation module (22) inspection the finishing device model library module (23), carry out signal quality and sequential automatic inspection and emulation, that is: the inspection of signal quality and signal sequence and emulation.
The emulation of signal quality, it at first is the network topology structure that signal quality emulation submodule (26) extracts PCB design, such as driver, network cabling, load and coupling etc., call the relevant driver and the model of load from device model library module (23) then, according to simulation model data and signal operational data wherein, just can access the RST of load end by simulation analysis, and then, judge wherein whether there is situation in violation of rules and regulations according to the level data in the model.
Signal quality emulation submodule (26) is also realized the automatic simulation of signal cross-talk.At first, it is right to find out the signal that also walking line is grown, spacing distance is less, utilizes emulated data, signal operational data in the device model library module (23) then, just can calculate the amplitude of crosstalking.
The inspection of signal sequence, at first be that sequential is checked the time series data of submodule (27) according to output device, then according to the network topology structure of PCB design, the time delay of signal calculated, obtain the sequential situation of load end, contrast the time series data of load end device again, just can access and whether can meet the demands.For the network topology structure of complexity,, determine the sequential situation of load end by signal simulation such as the situation that a plurality of loads are arranged.
For some special driving elements, these devices comprise corresponding time delay situation by obtaining embodiment in other special datas in the device model storehouse.By emulation like this and calculating, just can realize striding signal simulation and the sequential inspection that drives the class device.
Four, output signal automatic inspection and simulation report.
After the user carries out the inspection of signal quality and signal sequence and emulation and finishes, provide relevant report by output module (24), comprise check result, network title etc., also listing does not in addition have the part checked, as the statistics coverage rate etc., for reference.
Claims (7)
1, a kind of method that is used for PCB design is characterized in that, this method comprises following steps:
A, infput sheet design document;
B, according to the input the PCB design file in each device situation, the structure device model;
C, utilize device model, carry out the emulation of signal quality and the automatic inspection of sequential;
The emulation of d, quality of output signals and the automatic inspection of sequential;
Wherein, the emulation of the signal quality among the described step c specifically may further comprise the steps:
C11, at first extract the network topology structure of PCB design;
C12, secondly call the corresponding devices model,, obtain the signal quality situation of load end by emulation according to emulated data and signal operational data wherein;
C13, last basis level data wherein obtain situation in violation of rules and regulations;
The inspection of the signal sequence among the described step c specifically comprises:
C31, at first according to the time series data of output device, then according to the network topology structure of PCB design, the time delay of signal calculated obtains the sequential situation of load end;
C32, contrast the time series data of load end device at last, judge whether and to meet the demands,, determine the sequential situation of load end by signal simulation for the network topology structure of complexity.
2, a kind of method that is used for PCB design as claimed in claim 1 is characterized in that, the structure device model among the described step b specifically comprises:
B1, according to each device situation in the PCB design file of input, check in the device model library whether have the corresponding devices model;
B2, if exist, then no longer construct device model, otherwise the structure device model.
3, a kind of method that is used for PCB design as claimed in claim 2 is characterized in that, the employed data of structure device model described in the step b have: emulated data, level data, time series data, signal operational data.
4, a kind of method that is used for PCB design as claimed in claim 1 is characterized in that, the emulation of the signal quality among the described step c also further comprises the emulation of signal cross-talk, specifically comprises:
C21, at first find out and walking line signal long, that spacing distance is less right;
C22, utilize emulated data, signal operational data in the device model then, calculate the amplitude of crosstalking.
5, a kind of method that is used for PCB design as claimed in claim 1 is characterized in that, the described sequential situation that obtains load end also comprises: if for the network topology structure of complexity, determine the sequential situation of load end by signal simulation.
6, a kind of method that is used for PCB design as claimed in claim 1, it is characterized in that, carry out signal quality and sequential automatic inspection and emulation described in the step c also further comprise: according to other special datas of device model, realize striding signal simulation and the sequential inspection that drives the class device.
7, a kind of device that is used for PCB design, it is characterized in that this device comprises: be used for PCB design file input input module, be used for the memory device model the device model library module, be used to carry out signal quality and sequential automatic inspection and emulation the automatic inspection emulation module, be used for the output module of automatic inspection and simulation report output; Described automatic inspection emulation module comprises: the generation, modification, deletion, the device model management submodule of call operation, signal quality emulation submodule, the sequential that are used to carry out device model are checked submodule; Wherein,
The PCB design file is earlier by after the input module input, again through device model management submodule according to the PCB design file of input in each device situation, in the device model library module, carry out generation, modification, deletion, the call operation of device model, check that by signal quality emulation submodule and sequential submodule carries out the inspection and the emulation of signal quality and signal sequence to each network then, deliver to output module output automatic inspection and simulation report at last.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02129946 CN1223246C (en) | 2002-08-23 | 2002-08-23 | Method for designing printed circuit board and its equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN 02129946 CN1223246C (en) | 2002-08-23 | 2002-08-23 | Method for designing printed circuit board and its equipment |
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| CN1477919A CN1477919A (en) | 2004-02-25 |
| CN1223246C true CN1223246C (en) | 2005-10-12 |
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Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100428676C (en) * | 2005-04-23 | 2008-10-22 | 华为技术有限公司 | Printing circuit-board parallel design system based on network and method therefor |
| CN100458800C (en) * | 2006-09-21 | 2009-02-04 | 华为技术有限公司 | Automatic construction system and method for electronic circuit design |
| CN101714010B (en) * | 2009-10-28 | 2012-05-23 | 龙芯中科技术有限公司 | Clock domain crossing timing simulation system and method |
| CN105005015A (en) * | 2015-04-23 | 2015-10-28 | 广西电网有限责任公司电力科学研究院 | Circuit fault simulation system based on hardware circuit fault injection |
| CN105404754A (en) * | 2015-12-09 | 2016-03-16 | 浪潮电子信息产业股份有限公司 | Method for evaluating SI signal quality based on POWER impact |
| CN106455324A (en) * | 2016-09-09 | 2017-02-22 | 郑州云海信息技术有限公司 | Method and system for generating topological structures |
| CN107688682B (en) * | 2016-12-23 | 2021-05-14 | 北京国睿中数科技股份有限公司 | Method for extracting circuit topology by using time sequence path |
| CN106682374A (en) * | 2017-03-17 | 2017-05-17 | 北京润科通用技术有限公司 | Analog simulation method and system of working time sequence |
| CN107180143A (en) * | 2017-06-16 | 2017-09-19 | 郑州云海信息技术有限公司 | A kind of analysis of encoding transmits topology, method and the PCB trace method of influence on signal |
| CN109299534B (en) * | 2018-09-20 | 2023-07-25 | 深圳市一博科技股份有限公司 | Modeling method and device for printed circuit board |
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Assignee: King Brother Technology Limited Assignor: Huawei Technologies Co., Ltd. Contract fulfillment period: 2007.3.16 to 2012.3.15 contract change Contract record no.: 2009440001250 Denomination of invention: Method for designing printed circuit board and its equipment Granted publication date: 20051012 License type: Exclusive license Record date: 2009.8.14 |
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Effective date of registration: 20100108 Address after: No. 80, martyrs Road, Guangzhou, Yuexiu District No. 6 business building Patentee after: Guangzhou Dr. Technology Exchange Center Co., Ltd. Address before: No. 1, FA FA Road, Nanshan District Science Park, Shenzhen, Guangdong Patentee before: Huawei Technologies Co., Ltd. |
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