CN1477690A - Test method of complex semiconductor packaged structure - Google Patents
Test method of complex semiconductor packaged structure Download PDFInfo
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- CN1477690A CN1477690A CNA021304963A CN02130496A CN1477690A CN 1477690 A CN1477690 A CN 1477690A CN A021304963 A CNA021304963 A CN A021304963A CN 02130496 A CN02130496 A CN 02130496A CN 1477690 A CN1477690 A CN 1477690A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 105
- 238000010998 test method Methods 0.000 title claims description 11
- 238000012360 testing method Methods 0.000 claims abstract description 109
- 239000000758 substrate Substances 0.000 claims abstract description 46
- 239000002390 adhesive tape Substances 0.000 claims abstract description 25
- 238000005520 cutting process Methods 0.000 claims abstract description 25
- 238000000034 method Methods 0.000 claims description 25
- 235000012431 wafers Nutrition 0.000 claims description 22
- 238000005538 encapsulation Methods 0.000 claims description 11
- 239000000853 adhesive Substances 0.000 claims description 8
- 230000001070 adhesive effect Effects 0.000 claims description 8
- 239000004568 cement Substances 0.000 claims description 2
- 239000000919 ceramic Substances 0.000 claims description 2
- 238000004804 winding Methods 0.000 claims description 2
- 238000001514 detection method Methods 0.000 abstract description 7
- 229910000679 solder Inorganic materials 0.000 abstract description 5
- 238000004806 packaging method and process Methods 0.000 abstract description 2
- 230000008569 process Effects 0.000 description 10
- 239000004020 conductor Substances 0.000 description 9
- 230000032683 aging Effects 0.000 description 8
- 230000027455 binding Effects 0.000 description 5
- 238000009739 binding Methods 0.000 description 5
- 238000007789 sealing Methods 0.000 description 5
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 238000007747 plating Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- SEEZIOZEUUMJME-FOWTUZBSSA-N cannabigerolic acid Chemical compound CCCCCC1=CC(O)=C(C\C=C(/C)CCC=C(C)C)C(O)=C1C(O)=O SEEZIOZEUUMJME-FOWTUZBSSA-N 0.000 description 1
- SEEZIOZEUUMJME-UHFFFAOYSA-N cannabinerolic acid Natural products CCCCCC1=CC(O)=C(CC=C(C)CCC=C(C)C)C(O)=C1C(O)=O SEEZIOZEUUMJME-UHFFFAOYSA-N 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000013100 final test Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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Abstract
The testing method of complex semiconductor packaged structure includes the following steps: on a substrate packaging complex numbers of semiconductor, sticking adhesive tape, cutting substrate, testing semiconductor and sorting. Before the complex semiconductor packaged structure is cut, firstly an adhesive tape is stuck on its surface, then the substrate can be cut, then a detection card with complex detection contacts can be contacted with solder ball to make test, and finally, according to the tested result said semiconductor packaged structure can be sorted. It can test lots of complex semiconductor packaged structures.
Description
Technical field
The society of the present invention semi-conductive test in Ji, especially a kind of method of testing of complex semiconductor packaged structure, substantive test semiconductor package on adhesive tape and promote testing efficiency, reduce the required testing time of test.
Background technology
Semiconductor package now is equipped with the undersized trend of tending to, be wafer size encapsulation (chipsize package, CSP), its package area is not more than 1.3 times of wafer size, so the size of the test jack of CSP encapsulating structure is also littler thereupon, manufacturing cost costliness not only, and need indivedual carrying CSP encapsulating structures to test jack to test, so carry out the test of semiconductor package with test jack, not only need make expensive test jack, also need be wasted in the time of carrying before the test, and reduce testing efficiency and increase testing cost.
In United States Patent (USP) case the 6th, 121, in No. 063 " method of testing of sphere grid array integrated circuit ", disclose the method for testing of a kind of BGA (Ball Grid Array) encapsulating structure 10, as shown in Figure 1, this bga structure 10 is with known cemented wafer (chip mounting), routing (wire-bonding), sealing (molding) ... encapsulate etc. technology, it includes a wafer 11, one substrate 12, one connection gasket 13, and the method for testing that this bga structure 10 encapsulates after finishing is as follows: one, this bga structure 10 is after encapsulation is finished, do not form the step of soldered ball 16, and directly cut into independently bga structure 10, so the time this bga structure 10 do not have soldered ball 16 (on the substrate 12 do not have form soldered ball 16), two, this bga structure 10 is put to high temperature accelerated ageing (pre-burning) test jack (burn-In test socket), and the connection gasket 13 on the direct contact substrate 12 of test contacts of this high temperature accelerated ageing (pre-burning) test jack, test (burn-In test) and finish high temperature accelerated ageing (pre-burning), three, substrate 12 with hydrogen peroxide (hydrogen peroxide) solvent cleaned bga structure 10, on the connection gasket 13 of substrate 12, form soldered ball 16 then, four, the bga structure 10 that forms soldered ball 16 is placed in the last test socket 17 (final test socket) (as shown in Figure 1) again, and the soldered ball 16 on the test contacts 18 direct contact substrates 12 of this last test socket 17, and finish last test, five, with bga structure 10 with known surface engagement technology (surface mounttechnique, SMT) be connected to printed circuit board (PCB) (printed circuit board, PCB).
Because of when carrying out high temperature accelerated ageing (pre-burning) test, producing a large amount of temperatures, if this moment is when carrying out high temperature accelerated ageing (pre-burning) test, directly connect the soldered ball of transferring on the substrate 12 16 with test contacts, can cause soldered ball 16 damages and soldered ball 16 fusings and part to stick on the test contacts, make high temperature accelerated ageing (pre-burning) test jack shortening in useful life, for avoiding said circumstances to take place, so after high temperature accelerated ageing (pre-burning) test is finished, form the step of soldered ball 16 again, thus, the reliability that soldered ball 16 connects, test yield and test jack useful life ... all can improve etc. problem, but the method for known formation soldered ball 16 has plating, welding and with mould formation etc., after carrying out high temperature accelerated ageing (pre-burning) test, this bga structure 10 has cut into independent packaging units, if will form soldered ball 16 in the above described manner, at electroplating jig, Mould design, the technology of welding ... etc. the aspect, all can produce some problems, and expend more processing procedure times and cost, in addition, with this method of testing, need indivedual carrying bga structure 10 to test jacks to make the row test, testing efficiency is lower, also expend the more testing time, still shortcoming can be used the practicality of a large amount of productions and test.
Summary of the invention
Main purpose of the present invention provides a kind of method of testing of complex semiconductor packaged structure, this test process is in regular turn: a plurality of semiconductors of encapsulation, Continuous pressing device for stereo-pattern, cutting substrate, measuring semiconductor and classification on a substrate, and it is applied to BGA, QFN, SON and CSP ... substantive test efficiently Deng encapsulating structure.
An of the present invention purpose provides a kind of method of testing of complex semiconductor packaged structure, complex semiconductor packaged structure sticks on the adhesive tape, and with detecting card test complex semiconductor packaged structure, do not need to be carried to individually test jack and test, to improve testing efficiency and to reduce testing cost.
According to test process of the present invention, before semiconductor package does not cut, stick in the upper surface of this semiconductor package earlier with an adhesive tape, carry out cutting substrate then, make the semiconductor package of a plurality of mutual bindings become single encapsulation unit, this moment is single still cemented on this adhesive tape from the complex semiconductor packaged structure of (singularizing), the soldered ball that directly contacts complex semiconductor packaged structure with the detecting card with a plurality of detection contacts is tested then, classify according to test result at last, test process compared to use test socket (test socket), test process of the present invention can a substantive test complex semiconductor packaged structure, so can reduce the required time of test.
Description of drawings
Fig. 1: United States Patent (USP) the 6th, 121, the sectional view the when ball grid array integrated circuit of No. 063 " method of testing of ball grid array integrated circuit " is tested;
Fig. 2: according to the method for testing of complex semiconductor packaged structure of the present invention;
Fig. 3 a: according to first specific embodiment of the present invention, the sectional view of " semiconductor packages ";
Fig. 3 b: according to first specific embodiment of the present invention, the sectional view of " adhesive tape of paste ";
Fig. 3 C: according to first specific embodiment of the present invention, the sectional view of " cutting substrate ":
Fig. 3 d: according to first specific embodiment of the present invention, the sectional view of " measuring semiconductor ";
Fig. 4: according to first specific embodiment of the present invention, the sectional view of " measuring semiconductor "; And
Fig. 5: according to the 3rd specific embodiment of the present invention, the sectional view of " measuring semiconductor ".
Embodiment
See also appended graphicly, the present invention will enumerate following embodiment explanation:
The method of testing of complex semiconductor packaged structure of the present invention, as shown in Figure 2, the method of testing 100 of this complex semiconductor packaged structure in regular turn for semiconductor packages 110, adhesive tape of paste 120, cutting substrate 130, with detecting card measuring semiconductor 140 and classify 150, and in first specific embodiment of the present invention, Fig. 3 a to Fig. 3 d is the sectional view of the method for testing 100 (be semiconductor packages 110, adhesive tape of paste 120, cutting substrate 130 and with detecting card measuring semiconductor 140) of a complex semiconductor packaged structure.
At first shown in Fig. 2 and Fig. 3 a, at first carry out semiconductor packages 110, complex semiconductor packaged structure 200 as known cemented wafer, routing, sealing ... carry out on a substrate 230, being packaged into complex semiconductor packaged structure 200 etc. step, each semiconductor package 200 mainly comprises a wafer 210, one adhesive body 220, one substrate 230 and a plurality of plain conductor 250, wherein a plurality of wafer 210 is cemented on a substrate 230, and with the connection gasket 231 of plain conductor 250 electric connection wafers 210 to substrate 230, utilize pressing mold (molding) or additive method to form an adhesive body 220 then, with sealing wafer 210 and plain conductor 250, this substrate 230 is a single or multiple lift printed circuit board (PCB) in the present embodiment, it includes the plating circuit, to electrically connect this connection gasket 231, be formed with a plurality of solder ball pads 232 on the substrate 230 in addition, this solder ball pad 232 electrically conducts to connection gasket 231.
For another example shown in Fig. 2 and Fig. 3 b, carry out adhesive tape of paste 120, stick in the upper surface 201 surface of solder ball pad 2 32 (promptly do not have) of the semiconductor package 200 of a plurality of mutual bindings with an adhesive tape 260, on the solder ball pad 232 that is conducted with connection gasket 231, form soldered ball 240, make and form a plurality of sphere grid array semiconductor packages 200 (Ball Grid Array on the substrate 230, BGA), it also can be plastic cement structure dress BGA (plastic BGA, PBGA), heat-dissipating gain-type BGA (thermal enhanced BGA, EBGA), pottery structure dress BGA (ceramic BGA, CBGA), winding BGA (tape BGA, TBGA) or chip bonding BGA (flip-chip BGA, FCBGA) ... Deng encapsulating structure, this step that forms soldered ball also can be carried out before adhesive tape of paste 120, afterwards, shown in Fig. 2 and 3C, carry out cutting substrate 130, it is with cutting tool 270 cutting substrates 230, cut gap 280 and between each semiconductor package 200, form one, make the semiconductor package 200 of a plurality of mutual bindings become single encapsulation unit, when cutting substrate 230, the plating circuit that cutting substrate 230 electrically connects and do not cut off adhesive tape 260, make single still cementedly on an adhesive tape 260, and no longer have electric connection between each semiconductor package 200 from the complex semiconductor packaged structure 200 of (singularizing).
Then, shown in Fig. 2 and 3d, carry out with detecting card measuring semiconductor 140, in test process, to test with detecting card 290, this detecting card 290 has the detection contact 291 of a plurality of soldered balls 240 corresponding to semiconductor package 200, the soldered ball 240 that contact 291 directly contacts complex semiconductor packaged structure 200 will be surveyed, and finish test, and classify 150 at last, its test result according to gained is classified.
Be with in the method for testing of complex semiconductor packaged structure, before cutting substrate 230, stick in the upper surface 201 of the semiconductor package 200 of a plurality of mutual bindings with an adhesive tape 260, the square afterwards cutting substrate 230 that carries out, right single from complex semiconductor packaged structure 200 still glutinous because of on an adhesive tape 260, directly contact the soldered ball 240 of complex semiconductor packaged structure 200 again with the detection contact 291 of detecting card 290, to test, and the semiconductor package 200 of present embodiment (being bga structure) also can be wafer size encapsulation (chip size Package, CSP), it is 1.3 times that the package area of semiconductor package 200 is not more than wafer size, so the size of its test jack is also littler thereupon, manufacturing cost costliness not only, and need indivedual carrying semiconductor package 200 to test jacks to test, and test process of the present invention can reduce indivedual carrying semiconductor packages 200 before test, and with 290 substantive test complex semiconductor packaged structures 200 of detecting card, not only but substantive test also can save and make the time of carrying before expensive test jack and the test, so test process of the present invention also is specially adapted to wafer size encapsulation (CSP), it can promote testing efficiency, reduce the required time of test, reach the reduction testing cost.
Second specific embodiment of the present invention, as shown in Figure 4, on a substrate 330, be packaged into complex semiconductor packaged structure 300, and each semiconductor package 300 mainly comprises a wafer 310, one adhesive body 320, one substrate 330, a plurality of soldered balls 340 and a plurality of plain conductor 350, wherein wafer 310 is cemented in substrate 330, and electrically connect wafers 310 to substrate 330 with plain conductor 350, then with adhesive body 320 sealing wafer 310 and plain conductors 350, and on substrate 330, form soldered ball 340, make this semiconductor package 300 become the BGA semiconductor package, stick in the upper surface 301 surface of soldered ball 340 (promptly do not have) of the semiconductor package 300 of a plurality of mutual bindings then with an adhesive tape 360, again with cutting tool (figure does not draw) cutting substrate 330, cut gap 380 and between each semiconductor package 300, form one, make this semiconductor package 300 become single encapsulation unit, when cutting substrate 330, the plating circuit of cutting substrate 330 (figure do not draw) and do not cut off adhesive tape 360, make single from complex semiconductor packaged structure 300 still glutinous because of on an adhesive tape 360, then test with detecting card 390, this detecting card 390 has the detection contact 391 of a plurality of soldered balls 340 corresponding to semiconductor package 300, to survey directly contact complex semiconductor packaged structure 300 soldered balls 340 of contact 391, and finish test, classify according to test result at last, compared to the indivedual test processs of carrying single semiconductor package 300 to test jack of need, test process of the present invention can reduce before test indivedual carrying semiconductor packages 300 and with 390 substantive test complex semiconductor packaged structures 300 of detecting card, so can promote testing efficiency, reduce the required time of test, reach the reduction testing cost.
The 3rd specific embodiment of the present invention, as shown in Figure 5, substrate in the present embodiment is a lead frame, on this lead frame, be packaged into complex semiconductor packaged structure 400, and each semiconductor package 400 mainly comprises a wafer 410, one adhesive body 420, a plurality of drawing refers to 430, one brilliant pad 440 and a plurality of plain conductor 450, its encapsulation step is: a plurality of wafer 410 is cemented on the crystalline substance pad 440 of a lead frame, and electrically connect wafers 410 to drawing of lead frame with plain conductor 450 and refer to 430, then with adhesive body 420 sealing wafer 410 and plain conductors 450, after upset, draw and refer to that 430 lower surface 431 is exposed to outside the adhesive body 420, make this semiconductor package 400 become quad flat and do not have external pin type semiconductor encapsulating structure (Quad Flat Non-Jeaded, QFN), it also can be no external pin type semiconductor encapsulating structure (the Small Outline Non-leaded of miniaturization structure dress, SON) etc., stick in a plurality of upper surfaces 401 that are connected in the semiconductor package 400 of a lead frame mutually with an adhesive tape 360 then, again with cutting tool (figure does not draw) cutting semiconductor encapsulating structure 400, cut gap 480 and between each semiconductor package 400, form one, make semiconductor package 400 become single encapsulation unit, when cutting semiconductor encapsulating structure 400, only note non-cutting adhesive tape 460, make single from complex semiconductor packaged structure 400 still cemented on an adhesive tape 460, then test with a detecting card 490, this detecting card 490 has a plurality of detection contacts 491, it refers to 430 lower surfaces 431 corresponding to drawing of semiconductor package 400, directly drawing of contact complex semiconductor packaged structure 400 refers to 430 lower surfaces 431 with surveying contact 491, and finish test, classify according to test result at last, because test process of the present invention can reduce before test indivedual carrying semiconductor packages 400 and with 490 substantive test complex semiconductor packaged structures 400 of detecting card, so can promote testing efficiency, reduce the required time of test, reach the reduction testing cost.
Though the present invention discloses as above with preferred embodiment; right its is not in order to qualification the present invention, any those who are familiar with this art, without departing from the spirit and scope of the invention; when can doing a little change and retouching, so the present invention's protection range is as the criterion when looking claims scope person of defining.
Claims (8)
1, a kind of method of testing of complex semiconductor packaged structure, it is characterized in that: it comprises step has:
Carry out semi-conductive encapsulation, on a substrate, seal a plurality of semiconductor wafers, and constitute a plurality of complex semiconductor packaged structures on a substrate with adhesive body;
Adhesive tape of paste sticks in a plurality of upper surfaces that cut preceding semiconductor package with an adhesive tape;
Cutting substrate is partitioned into substrate and sticks in the complex semiconductor packaged structure of adhesive tape, and does not have electric connection between each semiconductor package;
Measuring semiconductor contacts this complex semiconductor packaged structure with detecting card, to test; And
Classification is classified according to test result.
2, the method for testing of complex semiconductor packaged structure as claimed in claim 1 is characterized in that: its step that comprises in addition has: form the surface of a plurality of soldered balls in this substrate.
3, the method for testing of complex semiconductor packaged structure as claimed in claim 2 is characterized in that: this semiconductor package is plastic cement structure dress BGA (PBGA), heat-dissipating gain-type BGA (EBGA), ceramic structure dress BGA (CBGA), winding BGA (TBGA) or chip bonding BGA (FCBGA).
4, the method for testing of complex semiconductor packaged structure as claimed in claim 1 is characterized in that: in the step of wherein " cutting substrate ", cut with cutting tool, and form a cutting gap between each semiconductor package.
5, the method for testing of complex semiconductor packaged structure as claimed in claim 1 is characterized in that: this substrate is the printed circuit board (PCB) of single or multiple lift.
6, the method for testing of complex semiconductor packaged structure as claimed in claim 1 is characterized in that: this substrate is a lead frame.
7, the method for testing of complex semiconductor packaged structure as claimed in claim 6 is characterized in that: this semiconductor package is that quad flat does not have outer pin formula (QFN) or miniaturization structure dress does not have outer pin formula (SON).
8, the method for testing of complex semiconductor packaged structure as claimed in claim 1 is characterized in that: this semiconductor package is wafer size structure dress (CSP).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA021304963A CN1477690A (en) | 2002-08-21 | 2002-08-21 | Test method of complex semiconductor packaged structure |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA021304963A CN1477690A (en) | 2002-08-21 | 2002-08-21 | Test method of complex semiconductor packaged structure |
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| CN1477690A true CN1477690A (en) | 2004-02-25 |
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| CNA021304963A Pending CN1477690A (en) | 2002-08-21 | 2002-08-21 | Test method of complex semiconductor packaged structure |
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Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100470749C (en) * | 2005-10-24 | 2009-03-18 | 南茂科技股份有限公司 | Crystal wafer testing method and structure of LED |
| CN100543437C (en) * | 2005-09-30 | 2009-09-23 | 日月光半导体制造股份有限公司 | Fall impacting device and method of testing thereof |
| CN102362188A (en) * | 2009-03-27 | 2012-02-22 | 爱德万测试株式会社 | Test device, test method, and production method |
| CN102543791A (en) * | 2012-01-20 | 2012-07-04 | 中国科学院上海技术物理研究所 | Film adhesive force quantitative test method with HgCdTe serving as substrate |
| CN102136440B (en) * | 2010-01-26 | 2012-10-10 | 旺矽科技股份有限公司 | Accurate pointing and sorting unit |
| CN103116119A (en) * | 2011-11-17 | 2013-05-22 | 上海航天测控通信研究所 | Test board based on hyper memory (HM) 276 stack-type electronic products and test method thereof |
| CN104582286A (en) * | 2014-12-31 | 2015-04-29 | 广州兴森快捷电路科技有限公司 | Manufacturing method for Burn-in semiconductor test board |
| CN104658924A (en) * | 2015-02-06 | 2015-05-27 | 安徽师范大学 | Packaging technology for small batch of circuits |
| CN109192675A (en) * | 2018-09-11 | 2019-01-11 | 长江存储科技有限责任公司 | Encapsulate body detecting method |
| CN109192677A (en) * | 2018-09-11 | 2019-01-11 | 长江存储科技有限责任公司 | Packaging body detection device |
| CN113161251A (en) * | 2020-01-22 | 2021-07-23 | 复格企业股份有限公司 | In-process testing method and device for chip packaging |
| TWI827176B (en) * | 2022-04-13 | 2023-12-21 | 友達光電股份有限公司 | System for detecting state of cut-off wheels and method of detecting state of cut-off wheels |
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2002
- 2002-08-21 CN CNA021304963A patent/CN1477690A/en active Pending
Cited By (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100543437C (en) * | 2005-09-30 | 2009-09-23 | 日月光半导体制造股份有限公司 | Fall impacting device and method of testing thereof |
| CN100470749C (en) * | 2005-10-24 | 2009-03-18 | 南茂科技股份有限公司 | Crystal wafer testing method and structure of LED |
| CN102362188A (en) * | 2009-03-27 | 2012-02-22 | 爱德万测试株式会社 | Test device, test method, and production method |
| US8652857B2 (en) | 2009-03-27 | 2014-02-18 | Advantest Corporation | Test apparatus, test method and manufacturing method for testing a device under test packaged in a test package |
| CN102136440B (en) * | 2010-01-26 | 2012-10-10 | 旺矽科技股份有限公司 | Accurate pointing and sorting unit |
| CN103116119A (en) * | 2011-11-17 | 2013-05-22 | 上海航天测控通信研究所 | Test board based on hyper memory (HM) 276 stack-type electronic products and test method thereof |
| CN102543791A (en) * | 2012-01-20 | 2012-07-04 | 中国科学院上海技术物理研究所 | Film adhesive force quantitative test method with HgCdTe serving as substrate |
| CN104582286B (en) * | 2014-12-31 | 2017-11-17 | 广州兴森快捷电路科技有限公司 | The preparation method of Burn in semiconductor test boards |
| CN104582286A (en) * | 2014-12-31 | 2015-04-29 | 广州兴森快捷电路科技有限公司 | Manufacturing method for Burn-in semiconductor test board |
| CN104658924A (en) * | 2015-02-06 | 2015-05-27 | 安徽师范大学 | Packaging technology for small batch of circuits |
| CN104658924B (en) * | 2015-02-06 | 2017-07-14 | 安徽师范大学 | A kind of packaging technology suitable for small lot circuit |
| CN109192675A (en) * | 2018-09-11 | 2019-01-11 | 长江存储科技有限责任公司 | Encapsulate body detecting method |
| CN109192677A (en) * | 2018-09-11 | 2019-01-11 | 长江存储科技有限责任公司 | Packaging body detection device |
| CN109192675B (en) * | 2018-09-11 | 2020-07-24 | 长江存储科技有限责任公司 | Package detection method |
| CN109192677B (en) * | 2018-09-11 | 2024-06-14 | 长江存储科技有限责任公司 | Package inspection device |
| CN113161251A (en) * | 2020-01-22 | 2021-07-23 | 复格企业股份有限公司 | In-process testing method and device for chip packaging |
| TWI827176B (en) * | 2022-04-13 | 2023-12-21 | 友達光電股份有限公司 | System for detecting state of cut-off wheels and method of detecting state of cut-off wheels |
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