CN104658924A - Packaging technology for small batch of circuits - Google Patents
Packaging technology for small batch of circuits Download PDFInfo
- Publication number
- CN104658924A CN104658924A CN201510063587.5A CN201510063587A CN104658924A CN 104658924 A CN104658924 A CN 104658924A CN 201510063587 A CN201510063587 A CN 201510063587A CN 104658924 A CN104658924 A CN 104658924A
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- CN
- China
- Prior art keywords
- circuit
- minute
- curing agent
- circuits
- work
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000012536 packaging technology Methods 0.000 title claims abstract description 13
- 238000000034 method Methods 0.000 claims abstract description 41
- 238000012360 testing method Methods 0.000 claims abstract description 16
- 230000032683 aging Effects 0.000 claims abstract description 11
- 239000003795 chemical substances by application Substances 0.000 claims description 30
- 238000005538 encapsulation Methods 0.000 claims description 16
- 239000003822 epoxy resin Substances 0.000 claims description 7
- 229920000647 polyepoxide Polymers 0.000 claims description 7
- 239000004593 Epoxy Substances 0.000 claims description 5
- 239000007788 liquid Substances 0.000 claims description 5
- 230000035882 stress Effects 0.000 abstract description 9
- 238000004806 packaging method and process Methods 0.000 abstract description 3
- 238000012858 packaging process Methods 0.000 abstract 2
- 238000003483 aging Methods 0.000 abstract 1
- 238000010438 heat treatment Methods 0.000 abstract 1
- 238000007711 solidification Methods 0.000 abstract 1
- 230000008023 solidification Effects 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 description 6
- 239000000463 material Substances 0.000 description 5
- 238000002474 experimental method Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000035939 shock Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 229920001169 thermoplastic Polymers 0.000 description 1
- 239000004416 thermosoftening plastic Substances 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
Landscapes
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
Abstract
The invention discloses a packaging technology for a small batch of circuits. According to the packaging technology, packaging, ageing and testing are carried out simultaneously. The whole process of the packaging technology comprises the following steps in sequence: immersing the circuits into a curing agent; heating a mould together with the circuits from a room temperature S1 DEG C to a prescribed high temperature S2 DEG C; enabling the circuits to work for t1 minutes under S2 DEG C, cutting off the power of the circuits, keeping the power of the circuits cut off for t2 minutes, and repeating the steps relating t1 and t2 for several times till solidification is fulfilled; lowering the temperature from S2 DEG C to S3 DEG C, enabling the circuits to work for t3 minutes under S3 DEG C, cutting off the power of the circuits, keeping the power of the circuits cut off for t4 minutes, and repeating the steps relating t3 and t4 for several times. The packaging technology has the benefit that time is saved. As repeated electrifying or deenergizing of the circuits or a chip during the packaging process can reduce stress generated in the packaging process, the mechanical strength after packaging is high, the reliability is high, and the finished product ratio is improved.
Description
Technical field
The present invention relates to a kind of packaging technology of circuit, be especially applicable to the packaging technology of small lot circuit.
Background technology
Encapsulation is necessary for some circuit, is also vital.Because some circuit will be isolated from the outside, electric property is caused to decline to prevent the corrosion of the impurity in air to chip and lead-in wire, after some circuit integrated packages and the element manufacturing such as resistance, electric capacity complete simultaneously, still need with packing forms to improve confidentiality, shock resistance and interference free performance, so that be used in harsh environment, as Aeronautics and Astronautics, deep-sea and battlefield etc.Encapsulation technology directly affects the performance of circuit self performance and the design and manufacture of PCB.
According to the structural requirement of different product, the packaged types such as embedding, encapsulating and plastic packaging can be divided into.Encapsulating material aspect, epoxy resin price is relatively cheap, moulding process is simple, be applicable to production, reliability is also higher, and therefore epoxide resin material encapsulation develops very fast nearly ten years.80% ~ 90% (Japan is almost whole) of external semiconductor device are encapsulated by epoxide resin material at present.
Conventional epoxy encapsulation mode needs special purpose machinery, and purchase cost, the operation and maintenance cost of this machine are higher, and itself noise is large, if the circuit of small lot also can waste material, so small lot circuit thermoplastic envelope should not use these special purpose machinerys.
Generally, being all after encapsulated circuit, do normal temperature test in laboratory, for reducing failure rate, then doing ageing test, finally do high/low temperature test.Being generally used for circuit in harsh environment will even thousands of hours of aging dozens of under the high temperature conditions, thisly repeat experiment and need the plenty of time, and in some project, time is at full stretch, although the quantity of these circuit is little, but designing and making these to spend a large amount of time for the circuit in harsh environment, the time of therefore doing ageing test is inadequate.
In encapsulation process, between circuit and encapsulating material, stress can be produced.During circuit working, each several part temperature is different, and also can produce stress between encapsulating material.These stress can cause that intensity declines, poor, the problems of crack of shock resistance, when working under high temperature or low temperature environment, can cause circuit or wafer damage.
There is following two problems in small lot circuit manufacturing process in present stage: one is how to shorten the production time, and two is the quality and the qualification rate that improve product by how reducing stress, and this two problems all needs to solve.
Summary of the invention
In order to solve the problem, the invention discloses a kind of packaging technology being applicable to small lot circuit.By encapsulation, aging with test carry out simultaneously, whole process is followed successively by:
A () first pours curing agent in mould, then circuit is put into mould, allows circuit immerse in curing agent; Or first circuit is put into mould, then pour curing agent into, allow circuit immerse in curing agent;
B mould is raised to appointment high temperature S2 DEG C together with circuit from room temperature S1 DEG C by ();
C () makes circuit work at S2 DEG C t1 minute, keep t2 minute, repeatedly repeat t1, t2 process after power-off, and at the end of this process, curing agent is no longer liquid;
D () drops to from S2 DEG C and specifies low temperature S3 DEG C, circuit is worked t3 minute at low temperature S3 DEG C, keeps t4 minute, repeatedly repeat t3, t4 process after power-off;
E () repeatedly repeats the high/low temperature process of (c) (d);
F () is raised to high temperature S2 DEG C from low temperature S3 DEG C again, circuit is worked t1 minute at S2 DEG C, keeps t2 minute, repeatedly repeat t1, t2 process after down circuitry.
In the foregoing circuit course of work, arrange test, substandard product is eliminated.
For the circuit that will work below 110 DEG C, preferred curing agent is HL-1108 epoxy curing agent.
For the circuit that will work more than 110 DEG C, preferred curing agent is epoxy resin HASUNBOND 739.
For from Celsius 125 degree to subzero 55 degree of circuit that all will work Celsius, t1=t2=10 minute, S1=25 DEG C, S2=125 DEG C, in step (c) in triplicate; T3=t4=10 minute, S3 are subzero 55 DEG C Celsius, in step (d) in triplicate; The high/low temperature process of (c) (d) at least repeats ten times in process step (e).
For from 110 degree of circuit that all will work to 40 degrees below zero Celsius Celsius, t1=t2=15 minute, S1=25 DEG C, S2=110 DEG C, in step (c) in triplicate; T3=t4=15 minute, S3 are subzero 40 DEG C Celsius, in step (d) in triplicate; In (e) step, the high/low temperature process of (c) (d) at least repeats ten times.
The invention has the beneficial effects as follows: encapsulation, aging and test are combined as a complete flow process in an orderly manner, and in this flow process, each step does not hinder the experiment effect both other, has saved the time, has accelerated speed of production.In encapsulation process, circuit is power on/off repeatedly, to reduce the stress produced in encapsulation process.Operationally, although circuit portions temperature is different, the infringement that stress causes obviously declines finished product after encapsulation.The anti-vibrating and impact performance of the finished product after encapsulation is better, improves reliability, improves quality, improve rate of finished products, add confidentiality and the mechanical strength of circuit.
Accompanying drawing explanation
Fig. 1 encapsulates mould used in embodiment.
Fig. 2 liquid-state epoxy resin high-temperature curing agent in a mold.
Circuit to be packaged in Fig. 3 embodiment.
In Fig. 4 embodiment, circuit immerses in curing agent.
Fig. 5 is temperature-time curve.
1. moulds, 2. epoxy curing agent, 3. circuit in figure.
Embodiment
Below in conjunction with the drawings and specific embodiments, the invention will be further described.
Fig. 3 is circuit to be packaged in embodiment, and when circuit in the environment of subzero 55 degree to 125 degree Celsius Celsius, needs anti-vibration and impact by being used for, encapsulation not only increases its confidentiality, also add mechanical strength.
By the encapsulation of this circuit, aging with test carry out simultaneously, whole process is followed successively by:
A () first pours curing agent in mould, then circuit is put into mould, allows circuit immerse in curing agent;
B mould is raised to appointment high temperature S2 DEG C together with circuit from room temperature S1 DEG C by ();
C () makes circuit work at S2 DEG C t1 minute, keep t2 minute, repeatedly repeat t1, t2 process after power-off, and at the end of this process, curing agent is no longer liquid;
D () drops to from S2 DEG C and specifies low temperature S3 DEG C, circuit is worked t3 minute at low temperature S3 DEG C, keeps t4 minute, repeatedly repeat t3, t4 process after power-off;
E () repeatedly repeats the high/low temperature process of (c) (d);
F () is raised to high temperature S2 DEG C from low temperature S3 DEG C again, circuit is worked t1 minute at S2 DEG C, keeps t2 minute, repeatedly repeat t1, t2 process after down circuitry.
In the foregoing circuit course of work, complete test, substandard product is eliminated.In step (c), curing agent is solid-state by liquid conversion, and the existing state worked on power of circuit, has again the state of power-off, and iterative cycles, effectively can reduce the stress encapsulated and work produces.In step (e), although curing agent has had cured, experiment has repeatedly contributed to reducing stress further, and bad product is come out in advance.
The curing agent used is epoxy resin HASUNBOND 739, t1=t2=10 minutes, S1=25 DEG C, S2=125 DEG C, in step (c) in triplicate; T3=t4=10 minute, S3 are subzero 55 DEG C Celsius, in step (d) in triplicate; The high/low temperature process of (c) (d) at least repeats ten times in process step (e).Complete aging and test in step (f).
In an embodiment, when circuit will be used for 40 degrees below zero in the environment of 110 degree.By the encapsulation of this circuit, aging with test carry out simultaneously, curing agent is HL-1108 epoxy curing agent, and whole process is followed successively by:
A circuit is first put into mould by (), then pour curing agent into, allows circuit immerse in curing agent;
B mould is raised to appointment high temperature S2 DEG C together with circuit from room temperature S1 DEG C by ();
C () makes circuit work at S2 DEG C t1 minute, keep t2 minute, repeatedly repeat t1, t2 process after power-off, and at the end of this process, curing agent is no longer liquid;
D () drops to from S2 DEG C and specifies low temperature S3 DEG C, circuit is worked t3 minute at low temperature S3 DEG C, keeps t4 minute, repeatedly repeat t3, t4 process after power-off;
E () repeatedly repeats the high/low temperature process of (c) (d);
F () is raised to high temperature S2 DEG C from low temperature S3 DEG C again, circuit is worked t1 minute at S2 DEG C, keeps t2 minute, repeatedly repeat t1, t2 process after down circuitry.
In the foregoing circuit course of work, complete high/low temperature test, eliminated by substandard product, t3=t4=10 minute, S3 are subzero 55 DEG C, in step (d) in triplicate; The high/low temperature process of (c) (d) at least repeats ten times in process step (e).Complete aging and high/low temperature test in step (f).
The present invention not only may be used for circuit package, also may be used for the encapsulation of semiconductor chip.The present invention can do some amendments by those skilled in the art not departing under spiritual prerequisite of the present invention, but the amendment done is still in the protection range of the claim of the application.
Claims (4)
1. be applicable to a packaging technology for small lot circuit, by encapsulation, aging with test carry out simultaneously, whole process is followed successively by:
A () first pours curing agent in mould, then circuit is put into mould, allows circuit immerse in curing agent; Or first circuit is put into mould, then pour curing agent into, allow circuit immerse in curing agent;
B mould is raised to appointment high temperature S2 DEG C together with circuit from room temperature S1 DEG C by ();
C () makes circuit work at S2 DEG C t1 minute, keep t2 minute, repeatedly repeat t1, t2 process after power-off, and at the end of this process, curing agent is no longer liquid;
D () drops to from S2 DEG C and specifies low temperature S3 DEG C, circuit is worked t3 minute at low temperature S3 DEG C, keeps t4 minute, repeatedly repeat t3, t4 process after power-off;
E () repeatedly repeats the high/low temperature process of (c) (d);
F () is raised to high temperature S2 DEG C from low temperature S3 DEG C again, circuit is worked t1 minute at S2 DEG C, keeps t2 minute, repeatedly repeat t1, t2 process after down circuitry;
In the foregoing circuit course of work, arrange test, substandard product is eliminated.
2. a kind of packaging technology being applicable to small lot circuit according to claim 1, is characterized in that:
For the circuit that will work below 110 DEG C, preferred curing agent is HL-1108 epoxy curing agent;
For the circuit that will work more than 110 DEG C, preferred curing agent is epoxy resin HASUNBOND 739.
3. a kind of packaging technology being applicable to small lot circuit according to claim 1, is characterized in that:
For from Celsius 125 degree to subzero 55 degree of circuit that all will work Celsius, t1=t2=10 minute, S1=25 DEG C, S2=125 DEG C, in step (c) in triplicate;
T3=t4=10 minute, S3 are subzero 55 DEG C Celsius, in step (d) in triplicate;
The high/low temperature process of (c) (d) at least repeats ten times in process step (e).
4. a kind of packaging technology being applicable to small lot circuit according to claim 1, is characterized in that:
For from 110 degree of circuit that all will work to 40 degrees below zero Celsius Celsius, t1=t2=15 minute, S1=25 DEG C, S2=110 DEG C, in step (c) in triplicate;
T3=t4=15 minute, S3 are subzero 40 DEG C Celsius, in step (d) in triplicate;
In (e) step, the high/low temperature process of (c) (d) at least repeats ten times.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510063587.5A CN104658924B (en) | 2015-02-06 | 2015-02-06 | A kind of packaging technology suitable for small lot circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510063587.5A CN104658924B (en) | 2015-02-06 | 2015-02-06 | A kind of packaging technology suitable for small lot circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104658924A true CN104658924A (en) | 2015-05-27 |
| CN104658924B CN104658924B (en) | 2017-07-14 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510063587.5A Expired - Fee Related CN104658924B (en) | 2015-02-06 | 2015-02-06 | A kind of packaging technology suitable for small lot circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104658924B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1477690A (en) * | 2002-08-21 | 2004-02-25 | 南茂科技股份有限公司 | Test method of complex semiconductor packaged structure |
| US20060273313A1 (en) * | 2005-06-01 | 2006-12-07 | Power Digital Card Co., Ltd. & Chien-Yuan Chen | IC packaging technique |
| CN101021547A (en) * | 2006-03-30 | 2007-08-22 | 信息产业部电子第五研究所 | Bare chip test and aging screening temporary packaging carrier |
-
2015
- 2015-02-06 CN CN201510063587.5A patent/CN104658924B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1477690A (en) * | 2002-08-21 | 2004-02-25 | 南茂科技股份有限公司 | Test method of complex semiconductor packaged structure |
| US20060273313A1 (en) * | 2005-06-01 | 2006-12-07 | Power Digital Card Co., Ltd. & Chien-Yuan Chen | IC packaging technique |
| CN101021547A (en) * | 2006-03-30 | 2007-08-22 | 信息产业部电子第五研究所 | Bare chip test and aging screening temporary packaging carrier |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104658924B (en) | 2017-07-14 |
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| Date | Code | Title | Description |
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| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB03 | Change of inventor or designer information | ||
| CB03 | Change of inventor or designer information |
Inventor after: Zhu Xiangbing Inventor after: Zhu Jiajun Inventor after: Shi Yinqiao Inventor after: Zhang Xuefeng Inventor after: Sang Kun Inventor after: Yang Hongyun Inventor after: Chen Jin Inventor before: Zhu Jiajun Inventor before: Zhu Xiangbing Inventor before: Shi Yinqiao Inventor before: Zhang Xuefeng Inventor before: Sang Kun Inventor before: Yang Hongyun Inventor before: Chen Jin |
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| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20170714 Termination date: 20210206 |