CN104241216A - Fan-out type packaging structure with controllable packaging height and manufacturing method of fan-out type packaging structure with controllable packaging height - Google Patents
Fan-out type packaging structure with controllable packaging height and manufacturing method of fan-out type packaging structure with controllable packaging height Download PDFInfo
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- CN104241216A CN104241216A CN201410292899.9A CN201410292899A CN104241216A CN 104241216 A CN104241216 A CN 104241216A CN 201410292899 A CN201410292899 A CN 201410292899A CN 104241216 A CN104241216 A CN 104241216A
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- wiring layer
- chip
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- limit
- fan
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
Abstract
The invention discloses a fan-out type packaging structure with the controllable packaging height and a manufacturing method of the fan-out type packaging structure with the controllable packaging height. The fan-out type packaging structure comprises a chip, a re-wiring layer, a height limiting block and a protruding point, wherein the chip is arranged on the re-wiring layer, and a first distance is reserved between the chip and the re-wiring layer; the height limiting block is arranged on the re-wiring layer, and a second distance is reserved between the height limiting block and the re-wiring layer; the protruding point is arranged on the chip, and a first part of the protruding point is exposed out of the re-wiring layer. First space is formed by the re-wiring layer, the height limiting block and the chip and filled with resin. The second distance is larger than the first distance. According to the fan-out type packaging structure, the height limiting block is used, a high-accuracy plastic packaging die is not needed, and the technical effect of greatly reducing the packaging, manufacturing and machining cost is achieved.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly relate to the controlled fan-out package structure of a kind of packaging height and manufacture method.
Background technology
Along with the development of large scale integrated circuit, circuit is more and more thinner, and 22nm technology enters volume production, the refinement of circuit, causes proposing unprecedented challenge for equipment and process.For the chip density in raising unit are and signal handling capacity.Along with circuit feature sizes constantly reduces, the enhancing of signal handling capacity, chip size constantly reduces, the number of pin of chip input and output gets more and more, i.e. chip I/O quantity increases, and a large amount of I/O quantity of one single chip cause, and one single chip electrode size also constantly reduces.And the restriction that the electrode size of substrate is subject to processing cannot accomplish same size, the size of the metal electrode of chip surface and spacing are all very little, therefore cannot carry out that follow-up encapsulation is necessary plants the work such as ball, therefore, before chip and substrate carry out bonding, wafer is reconstructed, by in the wafer of a chip buried reconstruct, increase chip and seem distance, on the larger surface of reconstruct wafer, by connecting up again, the small electrode of chip surface is carried out fan-out and form the electrode arrangement configurations that can meet Substrate manufacture and require, salient point processing and cutting formation is carried out again on reconstruct wafer, the fan-out structure unit of encapsulation process can be carried out, so-called fan-out technology that Here it is, i.e. chip fan-out technology.
Conventional chip fan-out technology adopts wafer-level packaging method manufacture, first the surface of the chip of well cutting at coating one deck ephemeral key rubber alloy is mounted, plastic packaging again, by chip plastic packaging in resin, the one side forming wafer shape embeds the resin structure of chip, loading plate is separated with resin structure, is having chip side to connect up again, form the reconstruct wafer with electrode fan-out structure.Resin structure now and conventional Silicon Wafer structural similarity, overall dimension is identical, just the high desnity metal electrode of chip surface to be distributed in a larger plane by wiring layer circuit again by the chip electrode in chip face, form the electrode arrangements that some can be suitable with PCB electrode size, form reconstruct crystal circle structure, just chip fan-out structure is formed, to form the encapsulation bonding of follow-up fan out unit and PCB or substrate through salient point processing and cutting.
But by research, those skilled in the art finds that in prior art, existence is following not enough:
This encapsulating structure and manufacture method manufacturing cost higher, after chip attachment, resin filling needs to manufacture high-precision plastic package die, because plastic package die cost of manufacture is high, causes this cost of manufacture high.
Summary of the invention
The fan-out package structure that the embodiment of the present invention provides a kind of packaging height controlled and manufacture method, for solving in prior art the technical problem needing to use high accuracy, the plastic package die of high cost causes cost high, there is the technique effect that high-precision mold, cost need not be used low.
The application provides following technical scheme by an embodiment of the application:
The fan-out package structure that packaging height is controlled, described structure comprises: chip; Wiring layer again, described in described chip is arranged on again on wiring layer, wherein said chip has the first distance apart from described wiring layer again; Limit for height block, described in described limit for height block is arranged on again on wiring layer, wherein said limit for height block has second distance apart from described wiring layer again; Salient point, described salient point is arranged on the chip, and the Part I of described salient point expose described in wiring layer again; Wherein, described wiring layer again, described limit for height block, described chip constitute the first space, and potting resin in described first space; Wherein, described second distance is greater than described first distance.
Further, described wiring layer is again specially a Rotating fields or sandwich construction.
Further, described wiring layer again comprises insulating barrier and line layer.
The application also provides another technical scheme by an embodiment of the application:
A manufacture method for the fan-out package structure that packaging height is controlled, described method comprises: ephemeral key rubber alloy surface chip and limit for height block being attached to loading plate; Plastic sealed board is covered on chip and limit for height block; By resin filling in the first space, and solidify to form overall structure; Remove described plastic sealed board; Remove loading plate and ephemeral key rubber alloy; Make wiring layer again.
Further, described method also comprises: implant salient point.
Further, described method also comprises: cutting forms fan-out packaging structure.
Further, described method also comprises: the mode potting resin adopting the liquid resin of good fluidity to fill at low temperature, then solidifies.
Further, described plastic sealed board is covered on chip and limit for height block after, also comprise: adopt the good resin of high temperature current downflow to carry out the filling embedding of resin, then solidify.
The beneficial effect of the embodiment of the present invention is as follows:
The fan-out package structure that a kind of packaging height that one embodiment of the invention provides is controlled and manufacture method, described structure comprises chip, again wiring layer, limit for height block, salient point, wherein, described in described chip is arranged on again on wiring layer, wherein said chip has the first distance apart from described wiring layer again; Described in described limit for height block is arranged on again on wiring layer, wherein said limit for height block has second distance apart from described wiring layer again; Described salient point is arranged on the chip, and the Part I of described salient point expose described in wiring layer again; Wherein, described wiring layer again, described limit for height block, described chip constitute the first space, and potting resin in described first space; Wherein, described second distance is greater than described first distance.The present invention need not use high accuracy plastic package die by using limit for height block, has the technique effect significantly reducing encapsulation manufacture and processing cost.
Further, the present invention can reach by using the limit for height block of differing heights and manufacture the encapsulating structure of differing heights, and need not adopt different packaging height and make the scheme of different high-precision mold, and then has the low technique effect of cost.
Accompanying drawing explanation
Fig. 1 is the controlled fan-out package structural representation of a kind of packaging height of providing in one embodiment of the invention;
Fig. 2 is the manufacture method schematic flow sheet of the controlled fan-out package structure of a kind of packaging height of providing in one embodiment of the invention;
The schematic diagram of the manufacture method of the fan-out package structure that a kind of packaging height provided in Fig. 3-11 one embodiment of the invention is controlled.
Embodiment
The fan-out package structure that a kind of packaging height that one embodiment of the invention provides is controlled and manufacture method, described structure comprises chip, again wiring layer, limit for height block, salient point, wherein, described in described chip is arranged on again on wiring layer, wherein said chip has the first distance apart from described wiring layer again; Described in described limit for height block is arranged on again on wiring layer, wherein said limit for height block has second distance apart from described wiring layer again; Described salient point is arranged on the chip, and the Part I of described salient point expose described in wiring layer again; Wherein, described wiring layer again, described limit for height block, described chip constitute the first space, and potting resin in described first space; Wherein, described second distance is greater than described first distance.The present invention need not use high accuracy plastic package die by using limit for height block, has the technique effect significantly reducing encapsulation manufacture and processing cost.
For making the object of the application one embodiment, technical scheme and advantage clearly, below in conjunction with the accompanying drawing in the embodiment of the present application, technical scheme in the embodiment of the present application is clearly and completely described, obviously, described embodiment is some embodiments of the present application, instead of whole embodiments.Based on the embodiment in the application, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
[embodiment one]
For enabling those skilled in the art understand the present invention more in detail, describe the present invention below in conjunction with accompanying drawing.
As described in Figure 1, Fig. 1 is a kind of flip-chip plastic package structure with radiator structure in one embodiment of the invention, and wherein, described structure comprises:
Chip 1;
Wiring layer 2 again, described in described chip 1 is arranged on again on wiring layer 2, wherein said chip 1 has the first distance a apart from described wiring layer again 2;
Limit for height block 3, described in described limit for height block 3 is arranged on again on wiring layer 2, wherein said limit for height block 3 has second distance b apart from described wiring layer again 2;
Salient point 5, described salient point 3 is arranged on described chip 1, and the Part I of described salient point 5 expose described in wiring layer 2 again;
Wherein, described wiring layer again 2, described limit for height block 3, described chip 1 constitute the first space, and potting resin 4 in described first space;
Wherein, described second distance b is greater than described first distance a.
Further, described wiring layer again 2 is specially a Rotating fields or sandwich construction.
Further, described wiring layer again 2 comprises insulating barrier and line layer.
Further, because wiring layer 2, chip 1, limit for height block 3 constitute the first space again, and be filled with the first space with resin 4, so, then wiring layer 2 covers the surface of resin 4 and chip 1.
Further, described limit for height block 3 can select different limit for height blocks 3 according to the height of different encapsulating structure, and that is, embodiment provided by the present invention limits the height of resin 4 filling by limit for height block 3, and then determines the height of encapsulating structure.And then, because the height of limit for height block 3 is higher than the height of chip 1, achieve the technique effect part in whole chip 1 except electrode surface all imbedded in resin 4.
[embodiment two]
As Fig. 2-11 shows, the manufacture method of the fan-out package structure that the embodiment of the present invention also provides a kind of packaging height controlled, described method comprises:
Step 110: ephemeral key rubber alloy 7 surface chip 1 and limit for height block 3 being attached to loading plate 6;
Step 120: plastic sealed board 8 is covered on chip 1 and limit for height block 3;
Step 130: resin 4 is filled into again wiring layer 2, in the first space that chip 1, limit for height block 3 are formed, and solidify to form overall structure;
Step 140: remove described plastic sealed board 8;
Step 150: remove loading plate 6 and ephemeral key rubber alloy 7;
Step 160: make again wiring layer 2.
Further, described method also comprises:
Step 170: implant salient point 5.
Further, described method also comprises:
Step 180: cutting forms fan-out packaging structure.
Further, step 130: resin 4 is filled in the first space, and the resin filling solidify to form in overall structure can have two kinds of modes:
The first: the mode potting resin adopting the liquid resin of good fluidity to fill at low temperature, then solidifies.
Specifically, the program is that low temperature is filled, and liquid resin can be end filler underfill.
The second, after forming structure in the step 120, fills under high temperature in step 130, that is: adopt the good resin of high temperature current downflow to carry out the filling embedding of resin, then solidify.
Specifically, the program is high temperature filler.
Further, step 140: the plastic sealed board removed in described plastic sealed board 8 is: the metallic plate of polyfluortetraethylene plate or coating polytetrafluoroethylene.Wherein, metallic plate and the loading plate 6 of limit for height block 3 and described polyfluortetraethylene plate or coating polytetrafluoroethylene form the first space, and in the first space potting resin 4, and solidify to form overall structure.Further, described plastic sealed board 8 has and does not have bonding character with described resin 4, removes so that described plastic sealed board 8 is easier from described resin 4.
Further, then the manufacture method of wiring layer 2 is identical with the wiring method again of fan-out package known in those skilled in the art, and the present invention no longer specifically sets forth.
The fan-out package structure that a kind of packaging height provided by the present invention is controlled and manufacture method have following technique effect:
The fan-out package structure that a kind of packaging height that one embodiment of the invention provides is controlled and manufacture method, described structure comprises chip, again wiring layer, limit for height block, salient point, wherein, described in described chip is arranged on again on wiring layer, wherein said chip has the first distance apart from described wiring layer again; Described in described limit for height block is arranged on again on wiring layer, wherein said limit for height block has second distance apart from described wiring layer again; Described salient point is arranged on the chip, and the Part I of described salient point expose described in wiring layer again; Wherein, described wiring layer again, described limit for height block, described chip constitute the first space, and potting resin in described first space; Wherein, described second distance is greater than described first distance.The present invention need not use high accuracy plastic package die by using limit for height block, has the technique effect significantly reducing encapsulation manufacture and processing cost.
Further, the present invention can reach by using the limit for height block of differing heights and manufacture the encapsulating structure of differing heights, and need not adopt different packaging height and make the scheme of different high-precision mold, and then has the low technique effect of cost.
Further, the present invention is controlled by limit for height block due to packaging height, so different packaging height does not need to make different high-precision molds, has the technique effect that cost is low.
Further, the present invention, by the use of different limit for height block, has applicable small lot batch manufacture, is also suitable for the technique effect of large-scale production.
Further, it is simple that the present invention has technique, is easy to the technique effect of volume production.
Obviously, those skilled in the art can carry out various change and modification to the present invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (8)
1. the fan-out package structure that packaging height is controlled, is characterized in that, described structure comprises:
Chip;
Wiring layer again, described in described chip is arranged on again on wiring layer, wherein said chip has the first distance apart from described wiring layer again;
Limit for height block, described in described limit for height block is arranged on again on wiring layer, wherein said limit for height block has second distance apart from described wiring layer again;
Salient point, described salient point is arranged on the chip, and the Part I of described salient point expose described in wiring layer again;
Wherein, described wiring layer again, described limit for height block, described chip constitute the first space, and potting resin in described first space;
Wherein, described second distance is greater than described first distance.
2. structure as claimed in claim 1, it is characterized in that, described wiring layer is again specially a Rotating fields or sandwich construction.
3. structure as claimed in claim 1, it is characterized in that, described wiring layer again comprises insulating barrier and line layer.
4. a manufacture method for the fan-out package structure that packaging height is controlled, is characterized in that, described method comprises:
Chip and limit for height block are attached to the ephemeral key rubber alloy surface of loading plate;
Plastic sealed board is covered on chip and limit for height block;
By resin filling in the first space, and solidify to form overall structure;
Remove described plastic sealed board;
Remove loading plate and ephemeral key rubber alloy;
Make wiring layer again.
5. method as claimed in claim 4, it is characterized in that, described method also comprises:
Implant salient point.
6. method as claimed in claim 5, it is characterized in that, described method also comprises:
Cutting forms fan-out packaging structure.
7. method as claimed in claim 4, it is characterized in that, described method also comprises:
The mode potting resin adopting the liquid resin of good fluidity to fill at low temperature, then solidifies.
8. method as claimed in claim 4, is characterized in that, described plastic sealed board is covered on chip and limit for height block after, also comprise:
Adopt the good resin of high temperature current downflow to carry out the filling embedding of resin, then solidify.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410292899.9A CN104241216A (en) | 2014-06-25 | 2014-06-25 | Fan-out type packaging structure with controllable packaging height and manufacturing method of fan-out type packaging structure with controllable packaging height |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410292899.9A CN104241216A (en) | 2014-06-25 | 2014-06-25 | Fan-out type packaging structure with controllable packaging height and manufacturing method of fan-out type packaging structure with controllable packaging height |
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| Publication Number | Publication Date |
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| CN104241216A true CN104241216A (en) | 2014-12-24 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201410292899.9A Pending CN104241216A (en) | 2014-06-25 | 2014-06-25 | Fan-out type packaging structure with controllable packaging height and manufacturing method of fan-out type packaging structure with controllable packaging height |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104465602A (en) * | 2014-12-26 | 2015-03-25 | 江苏长电科技股份有限公司 | Inverted PIP packaging structure achieving packaging and rewiring by utilizing frame and manufacturing method thereof |
| CN110517963A (en) * | 2019-09-05 | 2019-11-29 | 合肥矽迈微电子科技有限公司 | A kind of ring membrane structure Shooting Technique |
| CN116682743A (en) * | 2023-05-15 | 2023-09-01 | 珠海妙存科技有限公司 | Memory chip packaging method, memory chip and integrated circuit system |
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| CN102456584A (en) * | 2010-11-02 | 2012-05-16 | 新科金朋有限公司 | Semiconductor device and method of forming pentrable film encapsulant around semiconductor die and interconnect structure |
| CN103811472A (en) * | 2012-11-05 | 2014-05-21 | 三星电子株式会社 | Semiconductor package and manufacturing method thereof |
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| US20040125568A1 (en) * | 2002-12-30 | 2004-07-01 | Advanced Semiconductor Engineering, Inc. | Thermal enhance package and manufacturing method thereof |
| CN1641865A (en) * | 2004-01-09 | 2005-07-20 | 日月光半导体制造股份有限公司 | Flip chip packaging body |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104465602A (en) * | 2014-12-26 | 2015-03-25 | 江苏长电科技股份有限公司 | Inverted PIP packaging structure achieving packaging and rewiring by utilizing frame and manufacturing method thereof |
| CN110517963A (en) * | 2019-09-05 | 2019-11-29 | 合肥矽迈微电子科技有限公司 | A kind of ring membrane structure Shooting Technique |
| CN116682743A (en) * | 2023-05-15 | 2023-09-01 | 珠海妙存科技有限公司 | Memory chip packaging method, memory chip and integrated circuit system |
| CN116682743B (en) * | 2023-05-15 | 2024-01-23 | 珠海妙存科技有限公司 | Memory chip packaging method, memory chip and integrated circuit system |
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Application publication date: 20141224 |