CN103413798B - Chip structure, chip-packaging structure - Google Patents
Chip structure, chip-packaging structure Download PDFInfo
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- CN103413798B CN103413798B CN201310335859.3A CN201310335859A CN103413798B CN 103413798 B CN103413798 B CN 103413798B CN 201310335859 A CN201310335859 A CN 201310335859A CN 103413798 B CN103413798 B CN 103413798B
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 6
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Classifications
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
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- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
- H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
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- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1047—Details of electrical connections between containers
- H01L2225/1064—Electrical connections provided on a side surface of one or more of the containers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
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- H01L2924/1815—Shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
A kind of chip structure, chip-packaging structure, described chip-packaging structure comprises: at least two chip structures, and the sidewall of described chip structure has conductive trough, the stacking setting of described chip structure and the conductive trough position of stacking chip structure is corresponding; Be positioned at the conducting resinl of described conductive trough, utilize described conducting resinl the circuit electricity in stacking chip structure to be connected.Because described conductive trough is formed in the sidewall of insulating barrier, therefore follow-uply directly can not to contact with chip being formed in the conducting resinl in described conductive trough, can not circuit for generating short circuit; And be connected by the metal interconnecting layer being positioned at surface of insulating layer with between contact pad due to described conductive trough, described insulating barrier can not affect the layout design of other metal interconnect structures in chip, do not need the position because considering contact pad and design extra metal interconnect structure, the chip area occupied by metal interconnect structure can be saved, be conducive to the device integration improving chip.
Description
Technical field
The present invention relates to semiconductor fabrication process, particularly a kind of chip structure, chip-packaging structure.
Background technology
Along with semiconductor technology development, the characteristic size of current semiconductor device has become very little, wish that the quantity increasing semiconductor device in the chip structure of two dimension becomes more and more difficult, therefore three-dimension packaging, becomes a kind of method that effectively can improve chip integration by multiple chip stack package.Current three-dimension packaging comprises based on chip-stacked (DieStacking) of wire bonding, encapsulation stacking (PackageStacking) and three-dimensional stacked based on silicon through hole (ThroughSiliconVia, TSV).Wherein, the three-dimensional stacked technology of silicon through hole is utilized to have following three advantages: (1) High Density Integration; (2) shorten the length of electrical interconnection significantly, thus the problems such as the signal delay appeared in two-dimentional system level chip (SOC) technology can be solved well; (3) utilize silicon through hole technology, the chip (as radio frequency, internal memory, logic, MEMS etc.) with difference in functionality can be integrated and realize the multi-functional of packaged chip.Therefore, the described three-dimensional stacked technology of silicon through hole interconnect structure that utilizes becomes a kind of comparatively popular chip encapsulation technology day by day.More three-dimensional stacked technology about silicon through hole please refer to the american documentation literature that publication number is US2012/0083116A1.
But owing to needing to form some silicon through holes in chip based on the three-dimensional stacked technology of silicon through hole, need chip thinning when forming described silicon through hole, but the mechanical strength of thinning rear chip is poor, is easy to deform even damaged; Simultaneously because the metal material of filling in described silicon through hole is copper, the thermal coefficient of expansion of the silicon base of copper and chip differs greatly, therefore stressed zone can be formed at the chip position near silicon through hole, described stress can affect the electric property of semiconductor device, therefore can not form semiconductor device in described stressed zone, the waste of chip area can be caused; Technological requirement simultaneously owing to forming silicon through hole is higher, and process costs is larger.
Summary of the invention
The problem that the present invention solves is to provide a kind of chip structure, chip-packaging structure, can realize three-dimension packaging and technique is simple.
For solving the problem, the invention provides a kind of chip structure, comprising: chip, described chip has first surface and the second surface relative with first surface, and the first surface of described chip has contact pad; Be positioned at the insulating barrier of described chip sidewall, the sidewall of described insulating barrier has conductive trough, and the position of described conductive trough is corresponding with the position of contact pad, and the quantity of described conductive trough is corresponding with the quantity of contact pad; Be positioned at described conductive trough sidewall surfaces, contact pad surface and the metal interconnecting layer of surface of insulating layer, and described conductive trough, contact pad are connected by described metal interconnecting layer.
Optionally, described insulating barrier also covers the first surface of chip, and described insulating layer exposing goes out described contact pad.
Optionally, described insulating barrier is hydrophilic resin lipid layer.
Optionally, described insulating barrier is hydrophobic resin layer, and the surface of described hydrophobic resin layer has hydrophily through surface treatment.
Optionally, the material of described metal interconnecting layer is copper, aluminium or aluminium copper.
Present invention also offers a kind of chip-packaging structure, comprising: the chip structure described at least two, the sidewall of described chip structure has conductive trough, the stacking setting of described chip structure and the conductive trough position of stacking chip structure is corresponding; Be positioned at the conducting resinl of described conductive trough, utilize described conducting resinl the circuit electricity in stacking chip structure to be connected.
Optionally, also comprise: the load film being positioned at described stacking chip structure, utilize described load film by bonding for different chip structures.
Compared with prior art, technical scheme of the present invention has the following advantages:
Because described conductive trough is positioned at the sidewall of insulating barrier, therefore follow-uply directly can not to contact with chip being formed in the conducting resinl in described conductive trough, can not circuit for generating short circuit, and be connected by the metal interconnecting layer being positioned at surface of insulating layer with between contact pad due to described conductive trough, described insulating barrier can not affect the layout design of other metal interconnect structures in chip, do not need the position because considering contact pad and design extra metal interconnect structure, the chip area occupied by metal interconnect structure can be saved, be conducive to the device integration improving chip.
When described at least two chip structure stacked package, owing to being filled with conducting resinl in described conductive trough, described conducting resinl is utilized the circuit electricity in different chip structures to be connected, do not need to form silicon through hole and can make different chip stack packages, require to reduce to the alignment precision of chip-stacked equipment, process costs is lower, and does not need additionally to carry out wire bonding, and the number of plies of chip stack package can be comparatively large, is conducive to the encapsulation and integration degree improving chip-packaging structure.
Accompanying drawing explanation
Fig. 1 is the schematic flow sheet of the chip cutting method of the embodiment of the present invention;
Fig. 2 ~ Figure 13 is the process schematic of the chip cutting method of the embodiment of the present invention;
Figure 14 and Figure 15 is the structural representation of the chip structure of the embodiment of the present invention;
Figure 16 is the schematic flow sheet of the chip packaging method of the embodiment of the present invention;
Figure 17 ~ Figure 20 is the process schematic of the chip packaging method of the embodiment of the present invention.
Embodiment
Because the three-dimensional stacked technical matters cost based on silicon through hole is larger, the waste of chip area can be caused, and need chip thinning, the mechanical strength of chip is deteriorated, therefore the invention provides a kind of chip structure, chip-packaging structure, the sidewall of the chip structure utilizing described cutting method to be formed has conductive trough, when by stacking for multiple chip structure setting, full conducting resinl is filled in described conductive trough, utilize described conducting resinl that the circuit electricity in different chip structures is connected, form chip-packaging structure.Because the present invention does not need to form silicon through hole in chip, the technique forming silicon through hole can be saved, reduce costs; Simultaneously, because described conductive trough is formed in the sidewall of chip structure, only need filled conductive glue in conductive trough that the circuit electricity in different chip structures can be made to connect in the process of encapsulation, require to reduce to the alignment precision of chip-stacked equipment, packaging technology is simple; And existing chip needs again to customize domain according to the position of silicon through hole when utilizing silicon through hole to carry out three-dimension packaging usually, and around silicon through hole, there is stressed zone, the waste of chip area can be caused, and the present invention is not owing to needing to form silicon through hole in chip, more effectively can utilize the area of chip, be conducive to improving chip integration; And the metal interconnecting layer that described conductive trough is connected with electricity between contact pad is positioned at surface of insulating layer, described metal interconnecting layer does not need the area occupying chip, is conducive to the device integration improving chip.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
First the embodiment of the present invention provides a kind of chip cutting method, please refer to Fig. 1, is the schematic flow sheet of the chip cutting method of the present embodiment, specifically comprises:
Step S101, provides wafer, and described wafer comprises some chips and the Cutting Road between chip, and described chip has first surface and the second surface relative with first surface, and the first surface of chip has contact pad;
Step S102, sticks the first scribing film at the crystal column surface that described chip second surface is corresponding;
Step S103, carries out the first cutting along Cutting Road to the chip of wafer, forms the groove running through whole wafer thickness between different chip;
Step S104, forms insulating barrier with the first surface of chip in described groove;
Step S105, in the insulating barrier that groove is corresponding, form the through hole running through described insulating barrier, until expose the first scribing film, the position of described through hole is corresponding with the position of contact pad, and the quantity of described through hole is corresponding with the quantity of contact pad;
Step S106, forms metal interconnecting layer on described contact pad surface, surface of insulating layer and through-hole side wall surface, utilizes described metal interconnecting layer that contact pad is connected with through-hole side wall;
Step S107, the central point along described through hole carries out the second cutting to the insulating barrier in described groove, and described wafer is cut into discrete chip structure, and described through hole is formed conductive trough by after the second cutting at described chip structure sidewall.
Concrete, please refer to Fig. 2 and Fig. 3, Fig. 2 is the plan structure schematic diagram of described wafer, Fig. 3 is the cut-away section structural representation of described wafer, wafer 10 is provided, it is the chip 100 of matrix arrangement and the Cutting Road 120 between chip 100 that described wafer 10 comprises some, and described chip 100 has first surface 101 and second surface on the other side 102, and the first surface 101 of chip 100 has contact pad 103.
Described wafer 10 comprises chip 100 and the Cutting Road 120 between chip 100 of some arrangements in matrix, follow-uply along described Cutting Road 100, wafer is cut into several discrete chips.
Semiconductor device (not shown) and metal interconnect structure (not shown) is formed in described chip 100; described semiconductor device and metal interconnect structure form integrated circuit; described chip 100 surface also has passivation insulation (not shown); utilize described passivation insulation protect IC and chip and external electrical are isolated; described passivation insulation also has the opening exposing described contact pad 103, and the integrated circuit in chip is connected with external circuit with other chips by described contact pad 103.In the present embodiment, for the ease of being connected with the conductive trough electricity of follow-up formation, described contact pad 103 is arranged in a linear at the marginal position of chip, and described straight line parallels with the sideline of rectangular dies.Described contact pad 103 only can be formed in the marginal position on a chip limit, also can be formed in the marginal position on chip two limits, three limits or four limits.In the present embodiment, in order to illustrate conveniently, described contact pad 103 is only formed in the marginal position on a rectangular dies limit.
In other embodiments, described contact pad 103 also can need according to layout design the optional position being arranged on chip, because later use metal interconnecting layer makes contact pad be connected with conductive trough electricity, described metal interconnecting layer is formed in the passivation insulation surface of surface of insulating layer or chip, the layout design of metal interconnect structure in chip can not be affected, do not need the position because considering contact pad and design extra metal interconnect structure, the chip area occupied by metal interconnect structure can be saved, be conducive to the device integration improving chip.
And do not need to form silicon through hole in described chip due to the embodiment of the present invention, therefore do not need to carry out thinning to described wafer, the mechanical strength of described wafer is comparatively large, and wafer or chip fracture or damage are less likely to occur.And owing to not needing to form silicon through hole in described chip, therefore can save the processing step forming silicon through hole, significantly reduce process costs.And because the area of silicon through hole is usually very large and chip position near silicon through hole can form stressed zone, the stress of described stressed zone can affect the electric property of semiconductor device, therefore in the position and stressed zone of silicon through hole, all semiconductor device can not be formed, the waste of chip area can be caused, and the present invention is not owing to needing to be formed silicon through hole, more effectively can utilize the area of chip, be conducive to the device integration improving chip.
Please refer to Fig. 4, stick the first scribing film 131 at the crystal column surface of described chip 100 second surface 102 correspondence.
Be scattered when scribing is cut to prevent chip, before wafer is cut, described first scribing film 131 is sticked at the crystal column surface of chip 100 second surface 102 correspondence, described first scribing film 131 has viscosity and is not easily isolated, it is follow-up when wafer is cut into discrete chip by scribing, described chip is still pasted onto the first scribing film 131 surface, chip can not occur and be scattered, be convenient to the encapsulation of the follow-up chip structure carried out.Described first scribing film 131 is blue film or UV-light photocuring scribing film (UV film) etc.
Please refer to Fig. 5, the chip 100 along Cutting Road 120 pairs of wafers carries out the first cutting, between different chip 100, form groove 105.
The technique of described first cutting is laser cutting or blade cuts.In the present embodiment, blade is utilized to cut along Cutting Road 120 pairs of wafers 10, make to be cut open completely between different chips 100, simultaneously because the crystal column surface of chip 100 second surface 102 correspondence posts the first scribing film 131, described first scribing film 131 is not cut to be opened, therefore described chip 100 is still pasted onto the first scribing film 131 surface, forms the groove 105 running through whole chip thickness between different chip 100.The width of described groove 105 is less than or equal to the width of Cutting Road 120.
Please refer to Fig. 6, in described groove 105, form insulating barrier 106 with the first surface 101 of chip 100.
Described insulating barrier 106 is as the supporting body of the conductive trough of follow-up formation, and due to described conductive trough domestic demand filled conductive glue, described insulating barrier 106 has insulating properties, can by described conducting resinl and chip isolated, both are not directly contacted, avoids circuit for generating short circuit.In the present embodiment, described insulating barrier 106 is hydrophilic resin lipid layer, such as, containing-CONHCH
2oH ,-CONH
2,-COOH ,-COOROH ,-NH
2,-OH ,-SO
3the resin of the hydrophilic radicals such as H.In other embodiments, described insulating barrier 106 also can be hydrophobic resin layer, by carrying out surface treatment to the surface of hydrophobic resin layer, described surface-treated technique comprises plasma, glow discharge, ultra-violet oxidation, concentrated sulfuric acid immersion etc., makes the surface of hydrophobic resin layer have hydrophily.When the surface of described insulating barrier 106 is hydrophily, the follow-up chemical plating process that could utilize forms metal seed layer on described insulating barrier 106 surface, utilizes described metal seed layer to form the metal interconnecting layer connecting contact pad and conductive trough.Meanwhile, the formation process forming described resin bed is simple, and the mechanical strength of resin is higher, can be not easy fracture by protect IC.
In the present embodiment, described insulating barrier 106 is filled full described groove 105 and is formed in the first surface 101 of chip 100, and concrete formation process comprises: form hydrophilic resin lipid layer with the first surface 101 of chip 100 and solidify in described groove 105; Carry out polishing to the hydrophilic resin lipid layer after described solidification polish or return etching, in the hydrophilic resin lipid layer of described chip 100 first surface 101 reserve part thickness, in described groove 105, form described insulating barrier 106 with the hydrophilic resin lipid layer of the first surface 101 of chip 100.Fill full described groove 105 due to described insulating barrier 106 and be formed in the first surface 101 of chip 100, after making the second cutting, described insulating barrier 106 covers first surface 101 and the sidewall surfaces of described chip 100, more effectively can improve the mechanical strength of chip structure.
In the present embodiment, after forming described insulating barrier 106, patterned photoresist layer is formed on described insulating barrier 106 surface, the position of the insulating barrier 106 that described patterned photoresist layer exposes corresponds to the position of contact pad 103, with described patterned photoresist layer for mask, dry etching is carried out to described insulating barrier 106, until expose described contact pad 103, forms metal interconnecting layer so that follow-up on described contact pad 103 surface.Described dry etch process can utilize electron cyclotron to accelerate vibration (ECR) reactor, reactive ion etching (RIE) reactor, magnetic intensified response ion etching (MERIE) reactor or inductively coupled plasma (ICP) reactor etc. and etch, and the etching gas of described dry etching is the etching gas containing the halogens such as fluorine, chlorine, bromine or oxygen element or element sulphur, such as oxygen, C
4f
8, C
4f
8deng, utilize described etching gas and resin bed react thus etch.In other embodiments, laser etching process also can be utilized to be removed by the insulating barrier on described contact pad surface, thus expose described contact pad.
In other embodiments, also described insulating barrier can be etched again to expose described contact pad after formation through hole.
In other embodiments, described insulating barrier is filled full described groove but is exposed the first surface of chip, and concrete formation process comprises: in described groove, form hydrophilic resin lipid layer with the first surface of chip and solidify; Carry out polishing to the hydrophilic resin lipid layer after described solidification polish or return etching, until expose described chip first surface and expose described contact pad surface, hydrophilic resin lipid layer in described groove is described insulating barrier, and after the second cutting, described insulating barrier only covers the sidewall surfaces of described chip.
Please refer to Fig. 7, stick the second scribing film 132 at the crystal column surface of described chip 100 first surface 101 correspondence, and the first scribing film 131(tearing the crystal column surface of chip 100 second surface 102 correspondence off please refer to Fig. 6);
Please refer to Fig. 8, load film 115 is sticked at the crystal column surface of described chip 100 second surface 102 correspondence, etching formation first through hole 108 is carried out to the insulating barrier 106 of described chip 100 second surface 102 correspondence and load film 115, position, the quantity of the position of described first through hole 108, quantity and contact pad 103 are corresponding, and the degree of depth of described first through hole 108 is less than the gross thickness of insulating barrier corresponding to groove 106;
Please refer to Fig. 9, the 3rd scribing film 133 is sticked on described load film 115 surface, tear described second scribing film 132 off, the second etching is carried out at the insulating barrier 106 of described chip 100 first surface 101 to the first through hole 108 correspondence position, remaining insulating barrier 106 bottom described first through hole 108 is worn quarter, forms described through hole 107.
The technique forming described through hole 107 is laser etching process or dry etch process, in the present embodiment, the technique forming described through hole 107 is dry etch process, is formed the through hole 107 running through insulating barrier by twice etching, is conducive to forming the comparatively vertical through hole of sidewall.In other embodiments, laser etching process or dry etch process can also be utilized once to etch and directly insulating barrier corresponding for groove to be carved the through hole worn and formed and run through described insulating barrier.
The plan view shape of described through hole 107 is circular or rectangle, and the follow-up groove evenly being cut into two cylindricalitys by the second cutting technique of described through hole, described two grooves are as the conductive trough of chip structure.In the present embodiment, the plan view shape of described through hole 107 is rectangle.
The position of described through hole 107 is corresponding with the position of contact pad 103, and the quantity of described through hole 107 is corresponding with the quantity of contact pad 103.In the present embodiment, through hole 107 is follow-up is cut into two conductive troughs, due to for a chip structure, a corresponding contact pad of conductive trough, therefore corresponding two contact pads 103 of the through hole 107 between two chips, described two contact pads 103 are positioned at two two adjacent chip surfaces.Described through hole 107 is positioned at the central point of two corresponding contact pad 103 lines.
In the present embodiment, in order to illustrate conveniently, described contact pad 103 is only formed in the marginal position on a chip limit of rectangle, and therefore described through hole 107 is also only formed in insulating barrier corresponding to the groove of chip side.In other embodiments, described through hole also can be formed in the insulating barrier corresponding to groove on chip two limits, three limits or four limits, and the position of described through hole and the position of contact pad corresponding, the quantity of described through hole is corresponding with the quantity of contact pad.
In the present embodiment, the material of described second scribing film 132, the 3rd scribing film 133 is identical with the material of the first scribing film 133, all for being fixed by the chip on wafer, avoids because wafer fracture causes chip to be scattered.In other embodiments, the material of described second scribing film, the 3rd scribing film and the material of the first scribing film also can not be identical.Described load film 115 insulate and has viscosity, and described load film 115 is attached to the second surface 102 of described chip, follow-up when encapsulating chip structure, utilizes described load film 115 by bonding for different chips formation stacked structure.In the present embodiment, described 3rd scribing film 133 and load film 115 are all hydrophobic film, therefore can not form metal seed layer at described 3rd scribing film 133 or load film 115 surface during subsequent chemistry plating inculating crystal layer.
In other embodiments, also first etching formation first through hole can be carried out at the insulating barrier that described chip first surface is corresponding to groove, position, the quantity of the position of described first through hole, quantity and contact pad are corresponding, and the degree of depth of described first through hole is less than the gross thickness of insulating barrier corresponding to groove, then load film is formed at the crystal column surface that described chip second surface is corresponding, at described chip second surface and the insulating barrier of the first through hole correspondence position etch, the remaining insulating barrier of described first via bottoms is carved and wears, form described through hole.
In other embodiments, also load film can not be formed, follow-up when chip structure is encapsulated, utilize the conducting resinl in described conductive trough to be fixed together stacking for different chip structures.
Please refer to Figure 10 and Figure 11, Figure 10 is the cross-sectional view of chip cutting process, Figure 11 is the perspective view of described chip cutting process, metal interconnecting layer 109 is formed on described contact pad 103 surface, through hole 107 sidewall and insulating barrier 106 surface, utilize described metal interconnecting layer 109 that contact pad 103 is connected with through hole 107 sidewall, thus contact pad 103 is connected with the follow-up conducting resinl electricity formed in conductive trough.
In the present embodiment, the concrete technology forming described metal interconnecting layer 109 comprises: utilize chemical plating process or physical gas-phase deposition on described contact pad 103 surface, through hole 107 sidewall and insulating barrier 106 surface form metal seed layer (not shown), the material of described metal seed layer is copper, aluminium, the one wherein such as silver, when utilizing chemical plating process to form metal seed layer, because chemical plating process can only form metal seed layer at hydrophilic material surface, therefore, described metal seed layer can only be formed in described contact pad 103 surface, hydrophilic through hole 107 sidewall and insulating barrier 106 surface, form patterned photoresist layer (not shown) on described metal seed layer surface, described patterned photoresist layer defines the position of the metal interconnecting layer between contact pad and through hole, the metal seed layer surface utilizing electroplating technology, chemical plating process to expose at described patterned photoresist layer forms metal interconnecting layer 109, and the material of described metal interconnecting layer 109 is copper, aluminium or aluminium copper, utilize cineration technics to remove described patterned photoresist layer, expose the metal seed layer of correspondence position, utilize the metal seed layer exposed described in dry etch process or wet-etching technology removal, thickness due to metal seed layer is far smaller than the thickness of metal interconnecting layer, and the metal seed layer exposed described in therefore removing affects the electrology characteristic of metal interconnecting layer hardly.
In the present embodiment, because insulating barrier 106 covers the first surface 101 of chip 100, therefore described metal interconnecting layer 109 is formed in described contact pad 103 surface, through hole 107 sidewall and insulating barrier 106 top surface, utilizes described metal interconnecting layer 109 that contact pad 103 is connected with through hole 107 sidewall electricity.
In other embodiments, because insulating barrier is only formed in groove, therefore described metal interconnecting layer is formed in described contact pad surface, the first surface of chip, insulating barrier top surface and through-hole side wall, utilizes described metal interconnecting layer that contact pad is connected with through-hole side wall electricity.
Please refer to Figure 12 and Figure 13, Figure 12 is the cross-sectional view of chip cutting process, Figure 13 is the perspective view of described chip cutting process, please refer to Figure 10 along described through hole 107() central point the second cutting is carried out to the insulating barrier 106 in described groove, described wafer 10 is cut into discrete chip structure 20, and described through hole 107(please refer to Figure 10) formed conductive trough 110 by after the second cutting at described chip structure 20 sidewall.
The technique of described second cutting is laser cutting or blade cuts, the linear position that described second cutting technique is linked to be along the central point of through hole 107 cuts the insulating barrier 106 in described groove, make described through hole 107 evenly be cut into the conductive trough of two columns, the sidewall of the insulating barrier 106 namely after the second cutting forms conductive trough 110.After the second cutting technique, described wafer 10 is cut into several chip structures, and each chip structure correspondence has a chip 100, and the sidewall of described chip structure is formed with conductive trough 110.
The embodiment of the present invention additionally provides a kind of chip structure, please refer to Figure 14 and Figure 15, Figure 14 is the cross-sectional view of described chip structure 20, Figure 15 is the perspective view of described chip structure 20, comprise: chip 100, described chip 100 has first surface 101 and second surface 102, and the first surface 101 of described chip 100 has contact pad 103; Be positioned at the insulating barrier 106 of described chip 100 sidewall and first surface 101, the sidewall of described insulating barrier 106 has conductive trough 110; Be positioned at described conductive trough 110 sidewall surfaces, contact pad 103 surface and the metal interconnecting layer 109 on surface, insulating barrier top 106, and described conductive trough 110, contact pad 103 utilize described metal interconnecting layer 109 electricity to connect.
In other embodiments, described insulating barrier is only formed in the sidewall of described chip, and described metal interconnecting layer is formed in contact pad surface, the first surface of chip, insulating barrier top surface and conductive trough sidewall surfaces, described metal interconnecting layer is utilized conductive trough, contact pad electricity to be connected.
In the present embodiment, described insulating barrier 106 is hydrophilic resin lipid layer, and in other embodiments, described insulating barrier also can be hydrophobic resin layer, and the surface of described hydrophobic resin layer is after surface treatment, and the surface of hydrophobic resin layer has hydrophily.Because described conductive trough 110 is positioned at the sidewall of insulating barrier 106, though follow-up in described conductive trough 110 filled conductive glue, described conducting resinl also can not directly and chip come in contact, avoid being short-circuited.
In the present embodiment, the second surface 102 of described chip 100 is formed with load film 115, described load film 115 insulate and has viscosity, it is follow-up when described chip structure is encapsulated, utilize described load film 115 by bonding for different chip structures, be conducive to the mechanical strength improving described chip-packaging structure, be conducive to improving rate of finished products.In other embodiments, also can not form load film at the second surface of described chip, the conducting resinl in conductive trough described in later use is by stacking for different chip structures and be fixed together.
The embodiment of the present invention additionally provides a kind of chip packaging method, please refer to Figure 16, is the schematic flow sheet of the chip packaging method of the present embodiment, specifically comprises:
Step S201, provides at least two chip structures, and the sidewall of described chip structure has conductive trough, by stacking for described chip structure setting and the conductive trough position of stacking chip structure is corresponding;
Step S202, fills full conducting resinl in described conductive trough, utilizes described conducting resinl the circuit electricity in stacking chip structure to be connected.
Concrete, please refer to Figure 17 and Figure 18, Figure 17 is the cross-sectional view of described chip package process, Figure 18 is the perspective view of described chip package process, at least two chip structures 20 are as shown in Figure 14 and Figure 15 provided, the sidewall of described chip structure 20 has conductive trough 110, by the stacking setting of described chip structure 20 and conductive trough 110 position of different chip structure 20 is corresponding.
In the present embodiment, because conductive trough 110 position of different chip structure 20 is corresponding, and the conductive trough 11 of each chip structure 20 is connected with the contact pad 103 on corresponding chip 100 surface, therefore in conductive trough 110, different chips can be carried out electricity connection by filled conductive glue.
In the present embodiment, all have load film 115 between different chip structure 20, described load film 115 utilizes described load film 115 by bonding for different chip structures 20, is conducive to the mechanical strength improving described chip-packaging structure, is conducive to improving rate of finished products.In other embodiments, do not have load film between described different chip structure, the conducting resinl in conductive trough described in later use is by stacking for different chip structures and be fixed together.
In the present embodiment, three stacking settings of chip structure 20, in other embodiments, can also by two or more than three the stacking setting of chip structure 20 and encapsulate.Chip structure due to the embodiment of the present invention utilizes the conducting resinl in conductive trough different chip electricity to be connected when encapsulating, therefore the number of plies that chip structure is stacking is unrestricted, compared to the chip stack structure based on wire bonding, chip-packaging structure of the present invention can improve encapsulation and integration degree greatly.
Please refer to Figure 19 and Figure 20, Figure 19 is the cross-sectional view of described chip-packaging structure, Figure 20 is the perspective view of described chip-packaging structure, filled conductive glue 111 in described conductive trough 110, utilizes described conducting resinl 111 the circuit electricity in stacking chip structure 20 to be connected.
Described conducting resinl 111 includes organic polymer matrix and conducting particles, described conducting particles generally includes the electric conducting materials such as carbon, metal, metal oxide, by being mixed in described organic polymer matrix by conducting particles, thus described conducting resinl is made to have the electric conductivity close with metal.In the present embodiment, described conducting resinl 111 just fills full described conductive trough 110 completely, and in other embodiments, the surface of described conducting resinl 111 is higher or lower than the sidewall surfaces of described insulating barrier 160, and conducting resinl 111 electric isolation in different conductive trough.
In the present embodiment, fill full conducting resinl 111 in described conductive trough 110 after, make the chip structure of described multiple-level stack be packaged into a chip-packaging structure described conducting resinl 111 solidification, described chip-packaging structure utilizes the conducting resinl 111 in conductive trough 110 the integrated circuit electricity in different chip to be connected.
After forming described chip-packaging structure, can also carry out plastic packaging to described chip-packaging structure, the conducting resinl 111 and the extraneous electric isolation that expose described in making, avoid described chip-packaging structure to be short-circuited.
The embodiment of the present invention additionally provides a kind of chip-packaging structure, please refer to Figure 19 and Figure 20, Figure 19 is the cross-sectional view of described chip-packaging structure, Figure 20 is the perspective view of described chip-packaging structure, comprise: at least two chip structures 20 as shown in Figure 14 and Figure 15, the sidewall of described chip structure 20 has conductive trough 110, the stacking setting of described chip structure 20 and conductive trough 110 position of stacking chip structure 20 is corresponding; Be positioned at the conducting resinl 111 of described conductive trough 110, utilize described conducting resinl 111 the circuit electricity in stacking chip structure 20 to be connected.
In the present embodiment, between different chip structure 20, all there is load film 115, utilize described load film 115 by bonding for different chip structures 20, be conducive to the mechanical strength improving described chip-packaging structure, be conducive to improving rate of finished products.In other embodiments, also can not have load film between described different chip structure, the conducting resinl in conductive trough described in later use is by stacking for different chip structures and be fixed together.
Chip-packaging structure due to the embodiment of the present invention only needs filled conductive glue in conductive trough that the circuit electricity in different chip structures can be made to connect, the alignment precision of chip-stacked equipment requires to reduce, packaging technology is simple, and the stacking number of plies of the chip structure of the embodiment of the present invention is unrestricted, compared to the chip stack structure based on wire bonding, chip-packaging structure of the present invention can improve encapsulation and integration degree greatly.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (7)
1. a chip structure, is characterized in that, comprising:
Chip, described chip has first surface and the second surface relative with first surface, and the first surface of described chip has contact pad;
Be positioned at the insulating barrier of described chip sidewall, the sidewall of described insulating barrier has conductive trough, and the position of described conductive trough is corresponding with the position of contact pad, and the quantity of described conductive trough is corresponding with the quantity of contact pad;
Be positioned at described conductive trough sidewall surfaces, contact pad surface and the metal interconnecting layer of surface of insulating layer, and described conductive trough, contact pad are connected by described metal interconnecting layer.
2. chip structure as claimed in claim 1, it is characterized in that, described insulating barrier also covers the first surface of chip, and described insulating layer exposing goes out described contact pad.
3. chip structure as claimed in claim 1 or 2, it is characterized in that, described insulating barrier is hydrophilic resin lipid layer.
4. chip structure as claimed in claim 1 or 2, it is characterized in that, described insulating barrier is hydrophobic resin layer, and the surface of described hydrophobic resin layer has hydrophily through surface treatment.
5. chip structure as claimed in claim 1, it is characterized in that, the material of described metal interconnecting layer is copper, aluminium or aluminium copper.
6. a chip-packaging structure, is characterized in that, comprising:
At least two chip structures as claimed in claim 1, the sidewall of described chip structure has conductive trough, the stacking setting of described chip structure and the conductive trough position of stacking chip structure is corresponding;
Be positioned at the conducting resinl of described conductive trough, utilize described conducting resinl the circuit electricity in stacking chip structure to be connected.
7. chip-packaging structure as claimed in claim 6, is characterized in that, also comprise: the load film between described stacking chip structure, utilize described load film by bonding for different chip structures.
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| CN108389912B (en) * | 2018-01-12 | 2020-02-28 | 武汉高芯科技有限公司 | Uncooled infrared detector chip and packaging structure and preparation method thereof |
| CN111863640B (en) * | 2020-07-28 | 2021-11-23 | 南通通富微电子有限公司 | Chip packaging method |
| CN111863719B (en) * | 2020-07-28 | 2022-07-19 | 南通通富微电子有限公司 | Chip interconnection method |
| CN111863641B (en) * | 2020-07-28 | 2022-06-21 | 南通通富微电子有限公司 | Chip packaging method |
| CN111863793B (en) * | 2020-07-28 | 2022-07-12 | 南通通富微电子有限公司 | Semiconductor packaging device and chip interconnection method |
| CN111863717B (en) * | 2020-07-28 | 2022-07-15 | 南通通富微电子有限公司 | Chip interconnection method |
| CN111863795A (en) * | 2020-07-28 | 2020-10-30 | 南通通富微电子有限公司 | Semiconductor packaging body and chip packaging body |
| CN113540064A (en) * | 2021-07-16 | 2021-10-22 | 芯知微(上海)电子科技有限公司 | Wafer level packaging structure and packaging method |
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| KR100945504B1 (en) * | 2007-06-26 | 2010-03-09 | 주식회사 하이닉스반도체 | Stack package and method for manufacturing of the same |
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Address after: Jiangsu province Nantong City Chongchuan road 226006 No. 288 Patentee after: Tongfu Microelectronics Co., Ltd. Address before: 226006 Jiangsu Province, Nantong City Chongchuan District Chongchuan Road No. 288 Patentee before: Fujitsu Microelectronics Co., Ltd., Nantong |