CN203941896U - A kind of wafer level chip fan-out packaging structure - Google Patents
A kind of wafer level chip fan-out packaging structure Download PDFInfo
- Publication number
- CN203941896U CN203941896U CN201420342396.3U CN201420342396U CN203941896U CN 203941896 U CN203941896 U CN 203941896U CN 201420342396 U CN201420342396 U CN 201420342396U CN 203941896 U CN203941896 U CN 203941896U
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- chip
- wafer level
- wiring layer
- packaging structure
- metal coupling
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- Expired - Lifetime
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 47
- 239000002184 metal Substances 0.000 claims abstract description 78
- 229910052751 metal Inorganic materials 0.000 claims abstract description 78
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 56
- 239000010703 silicon Substances 0.000 claims abstract description 56
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 51
- 230000008878 coupling Effects 0.000 claims abstract description 41
- 238000010168 coupling process Methods 0.000 claims abstract description 41
- 238000005859 coupling reaction Methods 0.000 claims abstract description 41
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 229910000679 solder Inorganic materials 0.000 claims abstract description 15
- 150000003376 silicon Chemical class 0.000 claims abstract description 5
- 238000002161 passivation Methods 0.000 claims description 14
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 10
- 229910052802 copper Inorganic materials 0.000 claims description 10
- 239000010949 copper Substances 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 4
- 238000000034 method Methods 0.000 abstract description 19
- 239000004065 semiconductor Substances 0.000 abstract description 3
- 238000004382 potting Methods 0.000 abstract description 2
- 238000005538 encapsulation Methods 0.000 description 8
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 239000002390 adhesive tape Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910010272 inorganic material Inorganic materials 0.000 description 2
- 239000011147 inorganic material Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 239000011368 organic material Substances 0.000 description 2
- 239000005022 packaging material Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
- H01L2924/15155—Shape the die mounting substrate comprising a recess for hosting the device the shape of the recess being other than a cuboid
- H01L2924/15156—Side view
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The utility model discloses a kind of wafer level chip fan-out packaging structure, belong to semiconductor packaging field.It arranges shallow silicon cavity (111) and in silicon wafer surface, dielectric layer (120) and wiring layer I (131) is again set in turn on Silicon Wafer, then on the surface of the I of wiring layer again (131) of the upper surface of this silicon substrate (110), metal coupling (140) is set, chip to be packaged (210) upside-down mounting that is prepared with chip surface metal salient point (220) is placed into shallow silicon cavity (111) inner, whole Silicon Wafer is carried out to plastic packaging, and expose the upper surface of metal coupling (140), upper surface at plastic-sealed body (150) arranges wiring layer II (132) again again, the output rerouting of metal coupling (140) is become to array and places solder ball (170).The utility model has been avoided the offset problem of chip to be packaged in plastic package process, and has reduced the warpage issues of disk in potting process, has promoted the reliability of encapsulating products.
Description
Technical field
The utility model relates to a kind of wafer level chip fan-out packaging structure, belongs to semiconductor packaging field.
Background technology
Wafer-level Chip Scale Package is on whole wafer, to connect up and solder ball Solder bumping again, is finally cut into a kind of production method of single chips again.Final package dimension and the chip size of this kind of encapsulation are suitable, can realize miniaturization and the lightweight of encapsulation, in portable set, have a wide range of applications.Development along with semiconductor silicon technique, the critical size of chip is more and more less, in order to reduce costs, tends to select the more advanced higher chip fabrication technique of integrated level when carrying out chip manufacturing, this just makes the size of chip more and more less, and the I/O density of chip surface is also more and more higher.But meanwhile the manufacturing process of printed circuit board (PCB) and surface mounting technology do not have greatly improved.For the higher chip of this I/O density ratio, if carry out wafer level packaging, in order to ensure chip to be packaged and printed substrate, can form interconnection must be low-density packaging pin by highdensity I/O fan-out, that is carries out the encapsulation of wafer level chip fan-out.
At present, most importantly the eWLP being developed by company of Infineon in the encapsulation of wafer level chip fan-out encapsulates, this encapsulation technology mainly comprises following technical process: first by chip 2 fronts by adhesive tape bonding in substrate wafer, carry out wafer scale plastic packaging, substrate wafer is peeled off, then in chip 2 fronts, connected up again, form again wiring layer 3, and plant solder ball 5, finally packaging body is cut into single.This encapsulation technology is owing to adopting adhesive tape to carry out bonding, in the pyroprocess of plastic packaging, its bonding force is difficult to ensure card, this just causes chip 2 under impact of plastic packaging material mould stream, can produce displacement in plastic packaging process, thereby affects follow-up Wiring technique again, thus the difficult to govern control of packaging technology and yield not high.In addition, chip 2 is directly embedded in plastic-sealed body 1, different from plastic-sealed body 1 thermal coefficient of expansion due to chip 2, in encapsulation process, the variation of temperature will certainly produce stress, make disk be prone to larger angularity, thereby affect the reliability of encapsulating products, and in use, due to the existence of stress, also be prone to the inefficacy that chip 2 comes off in plastic-sealed body 1, affect encapsulating products reliability in use.
Summary of the invention
From the above, the purpose of this utility model is to overcome the deficiency of above-mentioned wafer level chip fan-out encapsulation, a kind of wafer level chip fan-out packaging structure is provided, to avoid the offset problem of chip to be packaged in plastic package process, and reduce the warpage issues of disk in potting process, promote encapsulating products reliability in use.
The purpose of this utility model is achieved in that
A kind of wafer level chip of the utility model fan-out packaging structure, comprising:
One silicon substrate, is provided with recessed shallow silicon cavity at this upper surface;
One dielectric layer, covers the surface of upper surface and the shallow silicon cavity of this silicon substrate;
Wiring layer I, is optionally arranged at the surface of this dielectric layer again and again, and along shallow silicon cavity bottom, extends upwardly to the upper surface of the silicon substrate of homonymy;
At least one chip to be packaged, is provided with several chip surface metal salient points in this front, and by this chip surface metal salient point upside-down mounting to realizing electric interconnection with wiring layer I again in this shallow silicon cavity;
At least one metal coupling, is fixed on the surface of the I of wiring layer again of the upper surface of this silicon substrate;
One plastic-sealed body, this chip to be packaged of plastic packaging, this metal coupling and this be the space at wiring layer I place again, and exposes the upper surface of this metal coupling; And
Wiring layer II, is arranged at the surface of this plastic-sealed body, and forms electric interconnection with this metal coupling again and again;
One passivation layer, covers this surface of wiring layer II again, and several passivation layer openings is optionally set, and in this passivation layer opening, solder ball is set, and realizes electric interconnection with wiring layer II again.
The degree of depth of shallow silicon cavity described in the utility model is 100 microns to 200 microns.
The upper surface of metal coupling described in the utility model is higher than the back side of chip to be packaged.
The height of metal coupling described in the utility model is 50 to 100 microns.
Rounded or the polygon of the cross section of metal coupling described in the utility model, and its boundary dimensions is greater than 80 microns.
Metal coupling described in the utility model is arranged in array.
The material of metal coupling described in the utility model and/or chip surface metal salient point is copper.
The degree of depth of shallow silicon cavity described in the utility model is 100 microns to 200 microns.
Rounded or the polygon of the cross section of chip surface metal salient point described in the utility model, and its boundary dimensions is greater than 60 microns.
The height of chip surface metal salient point described in the utility model is 15 microns to 35 microns.
Chip surface metal salient point described in the utility model is arranged in array.
The encapsulating structure of the present utility model back side has silicon substrate to support, and etching shallow silicon cavity be used for carrying chip to be packaged, the combination of shallow silicon cavity and metal coupling, chip surface metal salient point, effectively compressed taking up room of chip to be packaged, the plastic-sealed body that plastic packaging is formed is thinner, is conducive to reduce the chip to be packaged impact different from plastic-sealed body thermal coefficient of expansion.
The utility model beneficial effect is:
The utility model carries out wafer level plastic packaging with thinner plastic-sealed body when carrying out plastic packaging, reduced the chip to be packaged impact different from plastic-sealed body thermal coefficient of expansion, chip to be packaged is wrapped in plastic packaging material completely simultaneously, it is with wiring layer I again, wiring layer II refers to metal coupling, chip surface metal salient point by Bump(again) interconnected, not only avoided the offset problem of chip to be packaged in plastic package process, and reduced the angularity of whole disk, improved the reliability of encapsulating products.
For above-mentioned feature and advantage of the present utility model can be become apparent, special embodiment below, and coordinate appended graphic being described in detail below.
Accompanying drawing explanation
Fig. 1 is existing wafer level chip fan-out packaging structure schematic diagram;
Fig. 2 is the generalized section of the embodiment mono-of a kind of wafer level chip of the utility model fan-out packaging structure;
Fig. 3 is the generalized section of the embodiment bis-of a kind of wafer level chip of the utility model fan-out packaging structure;
Fig. 4 is the schematic diagram for the treatment of fan-out chip and shallow silicon cavity, solder ball position relationship and number relation of a kind of wafer level chip of the utility model fan-out packaging structure.
Main element symbol description
Silicon substrate 110
Shallow silicon cavity 111
Dielectric layer 120
Wiring layer I 131 again
Wiring layer II 132 again
Metal coupling 140
Plastic-sealed body 150
Plastic packaging opening 151
Passivation layer 160
Passivation layer opening 161
Solder ball 170
Chip 210 to be packaged
Chip surface metal salient point 220
Scolding tin cap 230.
Embodiment
Now will with reference to accompanying drawing, the utility model be described more fully hereinafter, exemplary embodiment of the present utility model shown in the drawings, thus the disclosure conveys to those skilled in the art fully by scope of the present utility model.Yet the utility model can be realized in many different forms, and should not be interpreted as being limited to the embodiment setting forth here.
Embodiment mono-, referring to Fig. 2
A kind of wafer level chip of the utility model fan-out packaging structure, its upper surface at silicon substrate 110 is provided with recessed shallow silicon cavity 111, is generally inverted trapezoidal.The degree of depth of shallow silicon cavity 111 is 100 microns to 200 microns, to carry chip 210 to be packaged.At the upper surface of silicon substrate 110 and the surface coverage dielectric layer 120 of shallow silicon cavity 111, this dielectric layer 120 is organic or inorganic material, mainly plays insulating effect.The surface selectivity of dielectric layer 120 wiring layer I 131 is again set, wiring layer I 131 extends upwardly to the upper surface of the silicon substrate 110 of homonymy along the bottom of shallow silicon cavity 111 again, then wiring layer I 131 by wafer level again Wiring technique can realize single or multiple lift and distribute.The front of chip 210 to be packaged is provided with several chip surface metal salient points 220, one end of chip surface metal salient point 220 is connected with the input/output terminal of chip 210 to be packaged respectively, and a not only chip surface metal salient point 220 of the input/output terminal correspondence of each chip 210 to be packaged.The cross section of chip surface metal salient point 220 is conventionally rounded, and its diameter is not more than 60 microns, and it is highly 15 microns to 35 microns, is micro metal salient point.Chip surface metal salient point 220 is conducting metal, conventionally adopts copper, makes chip surface copper bump.The other end of chip surface metal salient point 220 has scolding tin cap 230.
Chip 210 to be packaged is by 220 upside-down mountings of chip surface metal salient point to realizing electric interconnection with wiring layer I 131 again in shallow silicon cavity 111, and scolding tin cap 230 works the effect of being connected and fixed.Wiring layer I 131 selectivity between the input/output terminal of two chips 210 to be packaged adjacent one another are is discontinuous again.The metal coupling 140 that several cylindrical shapes are set on the surface of the I of wiring layer again 131 of the upper surface of silicon substrate 110, its diameter is not less than 80 microns.The upper surface of metal coupling 140 is higher than the back side of chip 210 to be packaged, enough height space are provided to chip 210 to be packaged.As 50 to 100 microns of general height of take metal coupling 140 are as good.The material of metal coupling 140 is conducting metal, is generally copper, makes copper post projection.Treat packaged chip 210, metal coupling 140 and again the space at wiring layer I 131 places adopt plastic package process to carry out plastic packaging, form plastic-sealed body 150, the upper surface flush of the upper surface of plastic-sealed body 150 (being generally abradant surface) and metal coupling 140.Wiring layer II 132 is again set on the surface of plastic-sealed body 150, and forms electric interconnection with metal coupling 140.Again wiring layer II 132 by wafer level again Wiring technique can realize single or multiple lift and distribute.At the surface coverage passivation layer 160 of wiring layer II 132 again, and several passivation layer openings being arranged in array 161 are optionally set, for solder ball 170, by passivation layer opening 161 and wiring layer II 132 again, form electric interconnections.The solder ball 170 forming is generally also arranged in array.
Embodiment bis-, referring to Fig. 3
A kind of wafer level chip of the utility model fan-out packaging structure, its upper surface at silicon substrate 110 is provided with recessed shallow silicon cavity 111, and the degree of depth of shallow silicon cavity 111 is 100 microns to 200 microns.At the upper surface of silicon substrate 110 and the surface coverage dielectric layer 120 of shallow silicon cavity 111, this dielectric layer 120 is organic or inorganic material, mainly plays insulating effect.The surface selectivity of dielectric layer 120 wiring layer I 131 is again set, wiring layer I 131 extends upwardly to the upper surface of the silicon substrate 110 of homonymy along the bottom of shallow silicon cavity 111 again, then wiring layer I 131 by wafer level again Wiring technique can realize single or multiple lift and distribute.The front of chip 210 to be packaged is provided with several chip surface metal salient points 220, one end of chip surface metal salient point 220 is connected with the input/output terminal of chip 210 to be packaged respectively, and a not only chip surface metal salient point 220 of the input/output terminal correspondence of each chip 210 to be packaged.The cross section of chip surface metal salient point 220 is conventionally rounded, and its diameter is not more than 60 microns, and it is highly 15 microns to 35 microns, is micro metal salient point.Chip surface metal salient point 220 is conducting metal, conventionally adopts copper, makes chip surface copper bump.The other end of chip surface metal salient point 220 has scolding tin cap 230.
Chip 210 to be packaged is by 220 upside-down mountings of chip surface metal salient point to realizing electric interconnection with wiring layer I 131 again in shallow silicon cavity 111, then wiring layer I 131 selectivity between the input/output terminal of two chips 210 to be packaged adjacent one another are is discontinuous.The metal coupling 140 that several cylindrical shapes are set on the surface of the I of wiring layer again 131 of the upper surface of silicon substrate 110, its diameter is not less than 80 microns.The upper surface of metal coupling 140 is higher than the back side of chip 210 to be packaged, enough height space are provided to chip 210 to be packaged.As 50 to 100 microns of general height of take metal coupling 140 are as good.The material of metal coupling 140 is conducting metal, is generally copper, makes copper post projection.Treat packaged chip 210, metal coupling 140 and again the space at wiring layer I 131 places adopt plastic package process to carry out plastic packaging, form plastic-sealed body 150.Plastic-sealed body 150 leaves certain thickness h in the top of metal coupling 140, and offers plastic packaging opening 151, only exposes the upper surface of metal coupling 140.This thickness h is determined by actual process design, is generally 10 to 20 microns.
Wiring layer II 132 is again set on the surface of plastic-sealed body 150, and forms electric interconnection with metal coupling 140.Again wiring layer II 132 by wafer level again Wiring technique can realize single or multiple lift and distribute.At the surface coverage passivation layer 160 of wiring layer II 132 again, and several passivation layer openings being arranged in array 161 are optionally set, for solder ball 170, by passivation layer opening 161 and wiring layer II 132 again, form electric interconnections.The solder ball 170 forming is generally also arranged in array.
A kind of wafer level chip of the utility model fan-out packaging structure can be more than one at the number of the chip to be packaged 210 of same shallow silicon cavity 111 interior settings, as shown in Figure 4, in shallow silicon cavity 111, be arranged side by side two chips 210 to be packaged, the function of these two chips 210 to be packaged can be identical, also can be different.The number of chip 210 to be packaged and the relative position in shallow silicon cavity 111 design according to actual needs.Several solder ball 170 are for meeting the needs that are connected of wafer level chip fan-out packaging structure and wiring board.
A kind of wafer level chip of the utility model fan-out packaging structure, chip 210 upside-down mountings to be packaged are after shallow silicon cavity 111, because the space between chip 210 to be packaged and shallow silicon cavity 111 is narrower and small, layer of structure is more complicated, generally, need to adopt the end to fill out the space that technique first treats between the shallow silicon cavity 111 of packaged chip 210 with end filler fills, with the empty plastic packaging that prevents that direct plastic packaging from may exist, and then carrying out wafer scale plastic packaging, this technical process and encapsulating structure are also contained in the utility model patent.
A kind of wafer level chip of the utility model fan-out packaging structure is not limited to above preferred embodiment, if the cross section of chip surface metal salient point 220 is except can be rounded, other polygon such as triangle, quadrangle can, as long as the size border of its cross section is not more than 60 microns; The cross section of metal coupling 140 except can be rounded, other polygons such as triangle, quadrangle also can, as long as the size border of its cross section is not more than 80 microns; Solder ball 170 can be also other connector, to realize with wiring board, is connected.The flexible setting of the number of metal coupling 140 and solder ball 170, position, shape etc., provides more design spaces to wafer level chip fan-out packaging structure.Therefore any those skilled in the art are not within departing from spirit and scope of the present utility model; any modification, equivalent variations and the modification above embodiment done according to technical spirit of the present utility model, all fall in the protection range that the utility model claim defines.
Claims (10)
1. a wafer level chip fan-out packaging structure, comprising:
One silicon substrate (110), is provided with recessed shallow silicon cavity (111) at this upper surface;
One dielectric layer (120), covers the surface of upper surface and the shallow silicon cavity (111) of this silicon substrate (110);
Wiring layer I (131), is optionally arranged at the surface of this dielectric layer (120) again and again, and along shallow silicon cavity (111) bottom, extends upwardly to the upper surface of the silicon substrate (110) of homonymy;
At least one chip to be packaged (210), is provided with several chip surface metal salient points (220) in this front, and by this chip surface metal salient point (220) upside-down mounting to realizing electric interconnection with wiring layer I (131) again in this shallow silicon cavity (111);
At least one metal coupling (140), is fixed on the surface of the I of wiring layer again (131) of the upper surface of this silicon substrate (110);
One plastic-sealed body (150), this chip to be packaged (210) of plastic packaging, this metal coupling (140) and this be the space at wiring layer I (131) place again, and exposes the upper surface of this metal coupling (140); And
Wiring layer II (132), is arranged at the surface of this plastic-sealed body (150), and forms electric interconnection with this metal coupling (140) again and again;
One passivation layer (160), covers this surface of wiring layer II (132) again, and several passivation layers (160) opening is optionally set, and in this passivation layer (160) opening, solder ball (170) is set, and realizes electric interconnection with wiring layer II (132) again.
2. a kind of wafer level chip fan-out packaging structure as claimed in claim 1, is characterized in that: the degree of depth of described shallow silicon cavity (111) is 100 microns to 200 microns.
3. a kind of wafer level chip fan-out packaging structure as claimed in claim 2, is characterized in that: the upper surface of described metal coupling (140) is higher than the back side of chip to be packaged (210).
4. a kind of wafer level chip fan-out packaging structure as claimed in claim 3, is characterized in that: the height of described metal coupling (140) is 50 to 100 microns.
5. a kind of wafer level chip fan-out packaging structure as claimed in claim 4, is characterized in that: the rounded or polygon of the cross section of described metal coupling (140), and its boundary dimensions is greater than 80 microns.
6. a kind of wafer level chip fan-out packaging structure as described in any one in claim 1 to 5, is characterized in that: described metal coupling (140) is arranged in array.
7. a kind of wafer level chip fan-out packaging structure as described in any one in claim 1 to 5, is characterized in that: the material of described metal coupling (140) and/or chip surface metal salient point (220) is copper.
8. a kind of wafer level chip fan-out packaging structure as claimed in claim 7, is characterized in that: the rounded or polygon of the cross section of described chip surface metal salient point (220), and its boundary dimensions is greater than 60 microns.
9. a kind of wafer level chip fan-out packaging structure as claimed in claim 8, is characterized in that: the height of described chip surface metal salient point (220) is 15 microns to 35 microns.
10. a kind of wafer level chip fan-out packaging structure as claimed in claim 9, is characterized in that: described chip surface metal salient point (220) is arranged in array.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420342396.3U CN203941896U (en) | 2014-06-26 | 2014-06-26 | A kind of wafer level chip fan-out packaging structure |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420342396.3U CN203941896U (en) | 2014-06-26 | 2014-06-26 | A kind of wafer level chip fan-out packaging structure |
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| CN203941896U true CN203941896U (en) | 2014-11-12 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107644861A (en) * | 2017-10-27 | 2018-01-30 | 无锡吉迈微电子有限公司 | Chip cloth wire encapsulation construction and its realizes technique again |
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2014
- 2014-06-26 CN CN201420342396.3U patent/CN203941896U/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107644861A (en) * | 2017-10-27 | 2018-01-30 | 无锡吉迈微电子有限公司 | Chip cloth wire encapsulation construction and its realizes technique again |
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