CN104241144A - Chip plastic package structure manufacturing method - Google Patents
Chip plastic package structure manufacturing method Download PDFInfo
- Publication number
- CN104241144A CN104241144A CN201410293059.4A CN201410293059A CN104241144A CN 104241144 A CN104241144 A CN 104241144A CN 201410293059 A CN201410293059 A CN 201410293059A CN 104241144 A CN104241144 A CN 104241144A
- Authority
- CN
- China
- Prior art keywords
- chip
- plastic
- plastic package
- package structure
- pcb board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004033 plastic Substances 0.000 title claims abstract description 70
- 229920003023 plastic Polymers 0.000 title claims abstract description 70
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 238000000034 method Methods 0.000 claims abstract description 45
- 239000011347 resin Substances 0.000 claims abstract description 22
- 229920005989 resin Polymers 0.000 claims abstract description 22
- 238000004806 packaging method and process Methods 0.000 claims abstract description 17
- 238000003825 pressing Methods 0.000 claims description 6
- 238000007711 solidification Methods 0.000 claims description 6
- 230000008023 solidification Effects 0.000 claims description 6
- 239000007788 liquid Substances 0.000 claims description 3
- 238000004382 potting Methods 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 abstract description 3
- 230000000694 effects Effects 0.000 description 12
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 238000011031 large-scale manufacturing process Methods 0.000 description 2
- 230000001105 regulatory effect Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- -1 polytetrafluoroethylene Polymers 0.000 description 1
- 229920001343 polytetrafluoroethylene Polymers 0.000 description 1
- 239000004810 polytetrafluoroethylene Substances 0.000 description 1
- 230000011218 segmentation Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
The invention discloses a chip plastic package structure manufacturing method and relates to the technical field of semiconductors. The method includes the steps that a chip and height limiting blocks are attached to the surface of a PCB; the chip is arranged on the PCB in a bonding mode through a lead, the space formed by the chip, the height limiting blocks and the PCB is filled with plastic package resin, a plastic package structure is formed through press fit of a plastic package plate, and curing is performed; a plastic package plate is removed; the plastic package structure is cut to form independent plastic package devices. Due to the use of the height limiting blocks, a high-precision packaging mold is not needed, and the low-cost advantage is achieved.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly relate to a kind of manufacture method of chip plastic package structure.
Background technology
In technical field of semiconductors, conventional chip bonding is surperficial to pcb board, the mode of wherein comparatively conventional leaded bonding.
But by research, those skilled in the art finds that in prior art, existence is following not enough:
Although conventional process of the prior art is simple and be easy to volume production, needs to make high-precision mould, and for different packaging height, need to manufacture different moulds, because Mold Making is with high costs, cause this cost of manufacture high.
Summary of the invention
The embodiment of the present invention provides a kind of manufacture method of chip plastic package structure, the technical problem that plastic package structure and method manufacturing cost for solving wire bonding mode in prior art are high, has lower-cost technique effect.
The application provides following technical scheme by an embodiment of the application:
A manufacture method for chip plastic package structure, described method comprises:
Chip and limit for height block are mounted on pcb board surface;
By described chip by wire bonding on described pcb board;
Plastic packaging resin is filled in the space formed to described chip, described limit for height block and described pcb board, and forms plastic package structure with plastic sealed board pressing, solidification;
Remove described plastic sealed board;
Described plastic package structure is cut into independent plastic device.
Further, described filling plastic packaging resin also comprises:
Adopt the mode potting resin that the liquid resin of good fluidity is filled at low temperature.
Further, described filling plastic packaging resin also comprises:
The condition of high temperature is warmed up to by needing the entire system of plastic packaging;
Carry out resin filling at high operating temperatures.
Further, described method also comprises:
Described chip and described limit for height block are pasted onto the same side of described pcb board by the mode of paster.
Further, described method also comprises:
Described limit for height block is bonded on described pcb board.
The beneficial effect of the embodiment of the present invention is as follows:
The manufacture method of a kind of chip plastic package structure that one embodiment of the invention provides, wherein method comprises chip and limit for height block is mounted on pcb board surface; By chip by wire bonding on pcb board; Plastic packaging resin is filled in the space formed to chip, limit for height block and pcb board, and forms plastic package structure with plastic sealed board pressing, solidification; Remove described plastic sealed board; Described plastic package structure cuts into independent plastic device.The present invention, by the use of limit for height block, need not use high-precision encapsulating mould and then reach lower-cost technique effect.
Further, different package thickness can be regulated according to the height of limit for height block, and the high accuracy encapsulating mould of differing heights need not be used, there is lower-cost technique effect.
Further, by the use of different limit for height block, there is applicable small lot batch manufacture, be also suitable for the technique effect of large-scale production.
Further, limit for height block is directly attached on pcb board, has without the need to extra manufacture craft and equipment, the simple technique effect of technique.
Accompanying drawing explanation
The flow chart of the manufacture method of a kind of chip plastic package structure that Fig. 1 provides for one embodiment of the invention;
The schematic diagram of the manufacture method of a kind of chip plastic package structure that Fig. 2-6 provides for one embodiment of the invention.
Embodiment
A kind of chip plastic package structure that one embodiment of the invention provides and method, wherein method comprises chip and limit for height block is mounted on pcb board surface; By described chip by wire bonding on described pcb board; Plastic packaging resin is filled in the space formed to described chip, described limit for height block and described pcb board, and forms plastic package structure with plastic sealed board pressing, solidification; Remove described plastic sealed board; Described plastic package structure cuts into independent plastic device.The present invention, by the use of limit for height block, need not use high-precision encapsulating mould and then reach lower-cost technique effect.
For making the object of the application one embodiment, technical scheme and advantage clearly, below in conjunction with the accompanying drawing in the embodiment of the present application, technical scheme in the embodiment of the present application is clearly and completely described, obviously, described embodiment is some embodiments of the present application, instead of whole embodiments.Based on the embodiment in the application, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
[embodiment one]
For enabling those skilled in the art understand the present invention more in detail, describe the present invention below in conjunction with accompanying drawing.
As shown in figures 2-6, the embodiment of the present invention also provides a kind of manufacture method of chip plastic package structure, and described method comprises:
Step 110: chip 1 and limit for height block 5 are mounted on pcb board 2 surface;
Step 120: described chip 1 is bonded on described pcb board 2 by lead-in wire 3;
Step 130: plastic packaging resin 4 is filled in the space formed with described pcb board 2 to described chip 1, described limit for height block 5, and forms plastic package structure with plastic sealed board 6 pressing, solidification;
Step 140: remove described plastic sealed board 6;
Step 150: described plastic package structure is cut into independent plastic device.
Further, fill plastic packaging resin described in step 130 also to comprise:
Adopt the mode potting resin that the liquid resin of good fluidity is filled at low temperature.
Further, fill plastic packaging resin described in step 130 also to comprise:
The condition of high temperature is warmed up to by needing the entire system of plastic packaging;
Carry out resin filling at high operating temperatures.
Further, described method also comprises: described chip 1 and described limit for height block 5 are pasted onto the same side of pcb board 2 by the mode of paster.
Further, described method also comprises: described limit for height block 5 is by being bonded on described pcb board 2.
Further, described limit for height block 5 can be the materials such as metal, plastics, silicon.Described limit for height block 4 also can be other shapes such as circular, square.Described limit for height block 4 can adopt stickup that the mode of bonding also can be adopted to be arranged on described pcb board 2.
Further, described limit for height block can be at least three limit for height blocks 5, and described at least three limit for height blocks 5 form the first plane [not shown]; Described pcb board 2 has the second plane [not shown]; Described first plane and the second plane are parallel plane.Specifically, become the principle in faces according to 3, form the first plane by least three limit for height blocks 5, and then form parallel cavity with the second plane of pcb board 2, be convenient in the future be divided into identical independent unit.
Further, the described plastic package structure back side can arrange salient point, also can not arrange salient point.
Further, plastic sealed board 6 can be or polyfluortetraethylene plate, or surface scribbles the metallic plate of polytetrafluoroethylene.
Further, the chip plastic package structure structure as shown in Figure 6 that after step 150, cutting is formed.
A kind of chip plastic package structure provided by the present invention and manufacture method have following technique effect:
A kind of chip plastic package structure that one embodiment of the invention provides and method, wherein method comprises and described chip and described limit for height block is mounted on described pcb board surface; By chip described in described wire bonding and described pcb board; Fill plastic packaging resin, and form plastic package structure with plastic sealed board pressing, solidification; Remove described plastic sealed board; Described plastic package structure cuts into independent plastic device.The present invention, by the use of limit for height block, need not use high-precision encapsulating mould and then reach lower-cost technique effect.
Further, different package thickness can be regulated according to the height of limit for height block, and the high accuracy encapsulating mould of differing heights need not be used, there is lower-cost technique effect.
Further, by the use of different limit for height block, there is applicable small lot batch manufacture, be also suitable for the technique effect of large-scale production.
Further, limit for height block is directly attached on described pcb board, has without the need to extra manufacture craft and equipment, the simple technique effect of technique.
Further, the first plane formed by least three limit for height blocks forms parallel cavity with the second plane of pcb board, achieves the reasonable structure of encapsulating structure, is also convenient to the technique effect of effective segmentation.
Obviously, those skilled in the art can carry out various change and modification to the present invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (5)
1. a manufacture method for chip plastic package structure, is characterized in that, described method comprises:
Chip and limit for height block are mounted on pcb board surface;
By described chip by wire bonding on described pcb board;
Plastic packaging resin is filled in the space formed to described chip, described limit for height block and described pcb board, and forms plastic package structure with plastic sealed board pressing, solidification;
Remove described plastic sealed board;
Described plastic package structure is cut into independent plastic device.
2. the method for claim 1, is characterized in that, described filling plastic packaging resin also comprises:
Adopt the mode potting resin that the liquid resin of good fluidity is filled at low temperature.
3. the method for claim 1, is characterized in that, described filling plastic packaging resin also comprises:
The condition of high temperature is warmed up to by needing the entire system of plastic packaging;
Carry out resin filling at high operating temperatures.
4. the method for claim 1, is characterized in that, described method also comprises:
Described chip and described limit for height block are pasted onto the same side of described pcb board by the mode of paster.
5. the method for claim 1, is characterized in that, described method also comprises:
Described limit for height block is bonded on described pcb board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410293059.4A CN104241144A (en) | 2014-06-25 | 2014-06-25 | Chip plastic package structure manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410293059.4A CN104241144A (en) | 2014-06-25 | 2014-06-25 | Chip plastic package structure manufacturing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104241144A true CN104241144A (en) | 2014-12-24 |
Family
ID=52228992
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410293059.4A Pending CN104241144A (en) | 2014-06-25 | 2014-06-25 | Chip plastic package structure manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104241144A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106098644A (en) * | 2016-08-11 | 2016-11-09 | 华天科技（西安）有限公司 | Chip-packaging structure that a kind of DAF film is combined with cushion block and manufacture method thereof |
| CN108093571A (en) * | 2018-01-19 | 2018-05-29 | 广东欧珀移动通信有限公司 | Assemble method, circuit board assemblies, display screen and the electronic equipment of circuit board assemblies |
| CN108093564A (en) * | 2018-01-18 | 2018-05-29 | 广东欧珀移动通信有限公司 | Circuit board and preparation method thereof and electronic equipment |
| CN108260293A (en) * | 2018-01-19 | 2018-07-06 | 广东欧珀移动通信有限公司 | Assemble method, circuit board assemblies, display screen and the electronic equipment of circuit board assemblies |
-
2014
- 2014-06-25 CN CN201410293059.4A patent/CN104241144A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106098644A (en) * | 2016-08-11 | 2016-11-09 | 华天科技（西安）有限公司 | Chip-packaging structure that a kind of DAF film is combined with cushion block and manufacture method thereof |
| CN108093564A (en) * | 2018-01-18 | 2018-05-29 | 广东欧珀移动通信有限公司 | Circuit board and preparation method thereof and electronic equipment |
| CN108093571A (en) * | 2018-01-19 | 2018-05-29 | 广东欧珀移动通信有限公司 | Assemble method, circuit board assemblies, display screen and the electronic equipment of circuit board assemblies |
| CN108260293A (en) * | 2018-01-19 | 2018-07-06 | 广东欧珀移动通信有限公司 | Assemble method, circuit board assemblies, display screen and the electronic equipment of circuit board assemblies |
| CN108093571B (en) * | 2018-01-19 | 2020-05-19 | Oppo广东移动通信有限公司 | Circuit board assembly assembling method, circuit board assembly, display screen and electronic equipment |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20141224 |