CN104582286A - Manufacturing method for Burn-in semiconductor test board - Google Patents
Manufacturing method for Burn-in semiconductor test board Download PDFInfo
- Publication number
- CN104582286A CN104582286A CN201410857339.3A CN201410857339A CN104582286A CN 104582286 A CN104582286 A CN 104582286A CN 201410857339 A CN201410857339 A CN 201410857339A CN 104582286 A CN104582286 A CN 104582286A
- Authority
- CN
- China
- Prior art keywords
- bga
- test board
- burn
- golden finger
- area
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
The invention relates to a manufacturing method for a Burn-in semiconductor test board. The manufacturing method includes the procedure of adopting a transparent micro-adhesion film for protecting the BGA region of an ultra-high board size, the thickness method of a lamination structure of a gold finger region, the procedure of manufacturing a technology edge through combination of flow stopping blocks and flow stopping points and the mode of independently measuring expanding and shrinking of each BGA unit of a BGA and drilling of each BGA unit of the BGA through positioning. The problems that the Burn-in semiconductor test board is high in requirement for aligning of the BGA, has the requirement for the thickness of the gold finger board and is prone to wrinkling are solved, and the manufacturing methods of difficult points are optimized so that a higher product yield can be achieved.
Description
Technical field
The present invention relates to semiconductor test board and make field, particularly relate to a kind of manufacture method of burn-in semiconductor test board.
Background technology
Semiconductor test board, as the pcb board of high added value, filters out qualified product for measuring semiconductor wafer, generally can be divided into ATE test board, probe-card test board and burn-in test board.Consult Fig. 1, wherein burn-in semiconductor test board has overlength size (long limit > 20inch), golden finger, little pitch (0.4mm or 0.5mm, require cabling in BGA) array BGA (4*4 or 5*4) and this BGA all need to fill socket, the appearance requirement such as the pad base material at present for BGA scratches, pad defect are also more and more stricter, therefore make semiconductor test board manufacture difficulty higher than the making of common pcb board part.In the prior art; because of the feature of Burn-in semiconductor test board; making it make difficult point is mainly reflected in following: first; overlength board size produced problem: in the transmittance process after outer graphics operation; easily there is the problem of figure scratching or wipe card face, and after treatment in operation without any plate face figure safeguard measure.Second, golden finger area produced problem: the internal layer design of the golden finger area of burn-in semiconductor test plate generally is base material, the method of existing design laminated construction thickness is: lamination design thickness range=complete thickness range-outer electro-coppering Layer thickness-solder mask thickness range, this laminated construction easily causes golden finger area thickness of slab not up to standard, partially thick or partially thin, adopt common process limit simultaneously, i.e. choker bar or choked flow point, consult Fig. 2 and Fig. 3, when carrying out pressing working procedure, after easily causing lamination pressing there is the problem that Copper Foil is wrinkling in golden finger area.3rd, the alignment issues of array BGA: each BGA unit is 0.4mm spacing (pitch), and cabling in BGA, conventional is 3 holes or 4 hole location drilling modes at present, this mode has been difficult to the contraposition requirement ensureing 0.4mm spacing (pitch), use the target hole measurement X of edges of boards, the harmomegathus of Y-direction, the stretching for the drilling of all BGA of whole plate is holed, and also cannot ensure the boring contraposition effect of all BGA.Consult Fig. 4, in actual fabrication process, pcb board part can cause the inner figure of plate after pressing to occur harmomegathus because of the bonding on the semi-solid preparation limit of internal layer, boring drilling stretching traditional method be then measure edges of boards 4 targets 30 ' between distance to calculate its overall harmomegathus value, i.e. length direction 2, overall harmomegathus value is measured in 2, short direction, and for the overall drilling that stretches, this kind of harmomegathus surveys the BGA boring contraposition being unfavorable for little pitch.
Summary of the invention
The object of the invention is to overcome above-mentioned the deficiencies in the prior art part and a kind of design optimization that makes is provided, and improving the manufacture method of the Burn-in semiconductor test board of product non-defective unit.
For solving the problems of the technologies described above, the invention provides following technical scheme:
A kind of manufacture method of Burn-in semiconductor test board; comprise: the laminating step of golden finger area and the making step of technique edges on the protection step of BGA area in transport process, this test board on this test board, and the step of the independent location survey harmomegathus of each BGA and boring.
In the embodiment optimized further; on this test board, the protection step of BGA area in transport process comprises: after this test board plate body surface treatment procedure, chooses and is pasted onto in the BGA area of this plate with transparent micro-mucous membrane of this BGA area comparable size.
In the embodiment optimized further, this transparent micro-mucous membrane has adhesive faces, this adhesive faces is pasted onto in the BGA area of this plate.
In the embodiment optimized further, this transparent micro-mucous membrane product eventually inspection time can to tear the operation of testing, again this transparent micro-mucous membrane can be sticked at operation BGA area being carried out protect after treating examination and test of products operation.
In the embodiment optimized further, the adhesive faces of this transparent micro-mucous membrane is provided with diaphragm.In the embodiment optimized further, on this test board, the laminating step of golden finger area comprises: the lamination procedure of this test board and the operation etched in the golden finger area of this test board; It is thick that this golden finger area is etched with the every one deck internal layer layers of copper adding golden finger area, is specially: every one deck internal layer layers of copper of lamination design thickness of slab=complete thickness of slab-outer electro-coppering thickness-solder mask thickness+golden finger area is thick.
In the embodiment optimized further, the making step of the technique edges of this golden finger area comprises: the half of technique edges in plate of this golden finger area makes the operation that becomes choked flow point and this technique edges are made into choker bar operation near edges of boards.
In the embodiment optimized further, internal layer every layer process limit choked flow point of this golden finger area is more than or equal to 1 inch apart from golden finger edge, and all the other technique edges are set to choker bar.
In the embodiment optimized further, the step of the independent location survey harmomegathus of this each BGA and boring, comprising:
Increase by four single targets in each BGA unit surrounding of the array BGA of each internal layer, these four targets for the harmomegathus value of also measure local after pressing, then make this single BGA unit drilling for this single BGA unit boring by the local harmomegathus value recorded.
In the embodiment optimized further, also comprise: use X ray perforating press to go out these four single target holes of each BGA unit and the operation of also measure local harmomegathus value; The operation of holing is carried out in the independent drilling using the local harmomegathus value of each BGA unit area to make.
After adopting technique scheme, the present invention at least has following beneficial effect:
The manufacture method of a kind of Burn-in semiconductor test board of the present invention adopts the scuffing and pad defect that prevent BGA area from occurring in transport process to the safeguard measure of overlength board size BGA area; The laminated construction of golden finger area and the design of technique edges, when solving golden finger area thickness of slab problem not up to standard, lamination there is the wrinkling problem of Copper Foil in unbalance stress; And the independent location survey harmomegathus of each BGA unit of BGA array and the mode of boring, solve a difficult problem for the BGA array measurement boring of Small Distance (Pitch) plate.The manufacture method design optimization of a kind of Burn-in semiconductor test board of the present invention, improve the non-defective unit of product.
Accompanying drawing explanation
Fig. 1 is the structural representation of Burn-in semiconductor test board in prior art.
Fig. 2 is golden finger area choked flow point technique edges structural representation in prior art.
Fig. 3 is golden finger area choker bar technique edges structural representation in prior art.
Fig. 4 is the schematic diagram that the harmomegathus in prior art BGA array measurement length direction carries out overall drilling stretching mode.
Fig. 5 is laminated construction schematic diagram in one of them embodiment of the present invention.
Fig. 6 is the structural representation on golden finger area Optimization Technology limit of the present invention.
Fig. 7 is the schematic diagram of the independent BGA drilling of the present invention for each BGA unit boring harmomegathus metering system.
Wherein description of reference numerals: 10, choker bar, 20, choked flow point, 30, target, 40, BGA unit.
Embodiment
It should be noted that, when not conflicting, the embodiment in the application and the technical characteristic in embodiment can be combined with each other, and are described in further detail the present invention below in conjunction with the drawings and specific embodiments.
The present invention is a kind of manufacture method of Burn-in semiconductor test board; consult Fig. 5 to Fig. 7; to comprise on this test board the laminating step of golden finger area and the making step of technique edges on the protection step of BGA area in transport process, this test board, and the step of the independent location survey harmomegathus of each BGA and boring.
Burn-in semiconductor test board has overlength board size; on this test board, the protection step of BGA area comprises: after plate body surface treatment; select the transparent micro-mucous membrane with BGA area comparable size; the wherein one side of this transparent micro-mucous membrane is provided with diaphragm; this diaphragm is torn; expose adhesive faces; adhesive faces is directly affixed on BGA towards the BGA area of plate; product eventually inspection time this transparent micro-mucous membrane of can tearing test, to be tested qualified after again this transparent micro-mucous membrane can be sticked in BGA area and carry out follow-up packing of product delivery.
The laminating step of golden finger area and the making step of technique edges on this test board, wherein also comprise the design on the design and processes limit of laminated construction.
On this test board, the laminating step of golden finger area comprises, the lamination procedure of this test board and the operation etched in the golden finger area of this test board; The every one deck internal layer layers of copper adding golden finger area in the thickness approach of this laminated construction is thick, and concrete method is optimized for: every one deck internal layer layers of copper of lamination design thickness of slab=complete thickness of slab-outer electro-coppering thickness-solder mask thickness+golden finger area is thick.
Add because internal layer golden finger area is that base material easily causes thickness of slab partially thin and the thickness of slab offset designed in the Thickness Design optimization of this laminated construction, concrete is designed to: lamination design thickness range=complete thickness range-outer electro-coppering Layer thickness-solder mask thickness range+gold finger plate thickness compensating value, lamination design thickness of slab value=(scope of design minimum value+scope of design maximum)/2.Whether cupric is relevant for the number of plies of offset and plate and internal layer golden finger area.The internal layer of this test board can also comprise dielectric layer.
The making step of the technique edges of this golden finger area: this technique edges is the combination design of choker bar 10 and choked flow point 20.The half of technique edges in plate of golden finger area is designed to choked flow point 20, is designed to choker bar 10 near edges of boards.Design and be conducive to gummosis in bonding processes at the choked flow point 20 in plate, and improve the wrinkling problem of Copper Foil of the golden finger area closed; Design and be conducive to strip thickness control at the choker bar 10 near edges of boards, be conducive to preventing gummosis from too much causing edges of boards partially thin.The superposition in golden finger area internal layer You Tong district, when avoiding lamination, unbalance stress occurs that Copper Foil is wrinkling.
The choked flow point 20 on the every layer process limit of internal layer of golden finger area is more than or equal to 1 inch (inch) apart from golden finger edge, and all the other regions are all set to choker bar 10.
The step of the independent location survey harmomegathus of each BGA and boring:
The method of the independent drilling of local harmomegathus is adopted for Small Distance (Pitch) array BGA, namely each BGA surrounding of the array BGA of each internal layer increase target be used for pressing after also measure local harmomegathus, then make independent BGA drilling by the local harmomegathus recorded and hole for each BGA.Concrete method flow is successively: inner figure design increases the operation of target 30 in array BGA unit 40 region surrounding; Carry out the operation of inner figure making; Lamination operation; X ray perforating press is used to go out four target 30 holes of each array BGA unit 40 and the operation of also measure local harmomegathus value; The independent drilling using the local harmomegathus value in each array BGA unit 40 region to make is holed.Design four targets 30 in the BGA surrounding of 0.4mmpitch, make the independent drilling of each BGA for lamination backlash hole measurement harmomegathus.
Relative to prior art, the manufacture method of a kind of Burn-in semiconductor test board of the present invention adopts the safeguard measure to overlength board size BGA area, the scuffing preventing BGA area to occur in process of transfer order and pad defect; The laminated construction of golden finger area and the optimal design of technique edges, when solving golden finger area thickness of slab excessive problem, lamination there is the wrinkling problem of Copper Foil in unbalance stress; And the mode of the independent location survey harmomegathus of each BGA of BGA array and boring, solve a difficult problem for the BGA array measurement boring of Small Distance (Pitch) plate.The manufacture method of the present invention to semiconductor test board is optimized, and improves the qualification rate of product.
Simultaneously, the present invention is conducive to the making qualification rate promoting burn-in semiconductor test board, be mainly reflected in that Copper Foil is wrinkling, thickness of slab exceeds standard, scrappage that internal layer short circuit and BGA scratch significantly declines, the essential information of below producing plates for certain 12 layers is that situation is scrapped in the actual production of example:
Table 1
Table 2
Refer to table 1 and table 2, table 1 is certain 12 layers essential information of producing plate; Table 2 is qualification rate statistical forms of the production of burn-in semiconductor test board.Can find out that the qualification rate of burn-in semiconductor test board can be improved more than 70% by manufacture method of the present invention from above-mentioned two tables, greatly reduce production cost.
Although illustrate and describe embodiments of the invention, for the ordinary skill in the art, be appreciated that and can carry out multiple change, amendment, replacement and modification to these embodiments without departing from the principles and spirit of the present invention, scope of the present invention is limited by claims and equivalency range thereof.
Claims (10)
1. the manufacture method of a Burn-in semiconductor test board; it is characterized in that comprising: the laminating step of golden finger area and the making step of technique edges on the protection step of BGA area in transport process, this test board on this test board, and the step of the independent location survey harmomegathus of each BGA and boring.
2. the manufacture method of Burn-in semiconductor test board as claimed in claim 1; it is characterized in that; on this test board, the protection step of BGA area in transport process comprises: after this test board plate body surface treatment procedure, chooses and is pasted onto in the BGA area of this plate with transparent micro-mucous membrane of this BGA area comparable size.
3. the manufacture method of Burn-in semiconductor test board as claimed in claim 2, it is characterized in that, this transparent micro-mucous membrane has adhesive faces, this adhesive faces is pasted onto in the BGA area of this plate.
4. the manufacture method of Burn-in semiconductor test board as claimed in claim 3; it is characterized in that; this transparent micro-mucous membrane product eventually inspection time can to tear the operation of testing, again this transparent micro-mucous membrane can be sticked at operation BGA area being carried out protect after treating examination and test of products operation.
5. the manufacture method of Burn-in semiconductor test board as claimed in claim 4, it is characterized in that, the adhesive faces of this transparent micro-mucous membrane is provided with diaphragm.
6. the manufacture method of Burn-in semiconductor test board as claimed in claim 1, it is characterized in that, on this test board, the laminating step of golden finger area comprises: the lamination procedure of this test board and the operation etched in the golden finger area of this test board; It is thick that this golden finger area is etched with the every one deck internal layer copper adding golden finger area, is specially: every one deck internal layer layers of copper of lamination design thickness of slab=complete thickness of slab-outer electro-coppering thickness-solder mask thickness+golden finger area is thick.
7. the manufacture method of Burn-in semiconductor test board as claimed in claim 1, it is characterized in that, the making step of the technique edges of this golden finger area comprises: the technique edges of this golden finger area half in plate makes the operation that becomes choked flow point and this technique edges are made into choker bar operation near edges of boards.
8. the manufacture method of Burn-in semiconductor test board as claimed in claim 7, is characterized in that, internal layer every layer process limit choked flow point of this golden finger area is more than or equal to 1 inch apart from golden finger edge, and all the other technique edges are set to choker bar.
9. the manufacture method of Burn-in semiconductor test board as claimed in claim 1, it is characterized in that, the step of the independent location survey harmomegathus of this each BGA and boring, comprising:
Increase by four single targets in each BGA unit surrounding of the array BGA of each internal layer, these four targets for the harmomegathus value of also measure local after pressing, then make this single BGA unit drilling for this single BGA unit boring by the local harmomegathus value recorded.
10. the manufacture method of Burn-in semiconductor test board as claimed in claim 9, is characterized in that, also comprise: use X ray perforating press to go out these four single target holes of each BGA unit and the operation of also measure local harmomegathus value; The operation of holing is carried out in the independent drilling using the local harmomegathus value of each BGA unit area to make.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410857339.3A CN104582286B (en) | 2014-12-31 | 2014-12-31 | The preparation method of Burn in semiconductor test boards |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410857339.3A CN104582286B (en) | 2014-12-31 | 2014-12-31 | The preparation method of Burn in semiconductor test boards |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104582286A true CN104582286A (en) | 2015-04-29 |
| CN104582286B CN104582286B (en) | 2017-11-17 |
Family
ID=53097179
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410857339.3A Expired - Fee Related CN104582286B (en) | 2014-12-31 | 2014-12-31 | The preparation method of Burn in semiconductor test boards |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104582286B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113543482A (en) * | 2021-06-11 | 2021-10-22 | 广州广合科技股份有限公司 | Method for managing and controlling thickness of circuit board production |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1477690A (en) * | 2002-08-21 | 2004-02-25 | 南茂科技股份有限公司 | Test method of complex semiconductor packaged structure |
| US20080054260A1 (en) * | 2004-09-02 | 2008-03-06 | Takashi Ishitobi | Semiconductor Integrated Circuit Device, Method For Testing The Semiconductor Integrated Circuit Device, Semiconductor Wafer And Burn-In Test Apparatus |
| CN103325693A (en) * | 2013-05-16 | 2013-09-25 | 华天科技（西安）有限公司 | Encapsulation piece using plastic package technology to optimize FCBGA encapsulation and manufacturing technology of encapsulation piece |
-
2014
- 2014-12-31 CN CN201410857339.3A patent/CN104582286B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1477690A (en) * | 2002-08-21 | 2004-02-25 | 南茂科技股份有限公司 | Test method of complex semiconductor packaged structure |
| US20080054260A1 (en) * | 2004-09-02 | 2008-03-06 | Takashi Ishitobi | Semiconductor Integrated Circuit Device, Method For Testing The Semiconductor Integrated Circuit Device, Semiconductor Wafer And Burn-In Test Apparatus |
| CN103325693A (en) * | 2013-05-16 | 2013-09-25 | 华天科技（西安）有限公司 | Encapsulation piece using plastic package technology to optimize FCBGA encapsulation and manufacturing technology of encapsulation piece |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113543482A (en) * | 2021-06-11 | 2021-10-22 | 广州广合科技股份有限公司 | Method for managing and controlling thickness of circuit board production |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104582286B (en) | 2017-11-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102036511B (en) | Method for classifying and compensating nonlinear variation of core boards for manufacturing multilayer circuit boards | |
| CN104570421B (en) | Display panel and display device | |
| CN105044940B (en) | A kind of panel and its test method | |
| US10610972B2 (en) | Laser cutting base and laser cutting device | |
| CN104582285B (en) | The preparation method of the printed circuit board (PCB) of low warpage high-flatness | |
| CN105372857A (en) | Glass substrate, liquid crystal display panel and liquid crystal display device | |
| CN105282983A (en) | Lead wire etching technology with gold fingers with three surfaces wrapped by gold | |
| CN105376963A (en) | Method for grabbing internal layer compensation coefficients | |
| CN104582286A (en) | Manufacturing method for Burn-in semiconductor test board | |
| CN104470227A (en) | Method for improving high multilayer circuit board slice position and BGA position plated-through hole copper thickness unevenness | |
| CN203941362U (en) | Liquid crystal panel | |
| CN112954881B (en) | Detection method for repeated cutting of flexible plate | |
| CN105611752A (en) | Manufacture method adopting inner layer pattern transfer exposure | |
| CN203136321U (en) | Aligning device and printed circuit board | |
| CN107613645A (en) | A kind of wiring board gong band processing method | |
| CN207443205U (en) | A kind of multi-layer flexible circuit board of anti-stacked fault position | |
| CN201491385U (en) | Circuit jointed board | |
| CN202178918U (en) | Copper-clad plate capable of controlling CORE expansion-contraction layer deviation | |
| CN204859738U (en) | Circuit board with module of counterpointing between layer | |
| CN105188265A (en) | Improved FPC boring examination method | |
| CN207095504U (en) | A kind of structure for HDI plates detection laser drill precision | |
| CN205050112U (en) | Touch -control display panel and test system | |
| CN107613651A (en) | A kind of justifying FPC processing technologys | |
| CN202231953U (en) | Internal layer error-proofing printed circuit board | |
| CN207869481U (en) | Harmomegathus target and PCB board |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20171117 Termination date: 20211231 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |