CN1475810A

CN1475810A - Cable testing device and method

Info

Publication number: CN1475810A
Application number: CNA021365512A
Authority: CN
Inventors: 毕毓龙
Original assignee: ZTE Corp
Current assignee: ZTE Corp
Priority date: 2002-08-16
Filing date: 2002-08-16
Publication date: 2004-02-18
Anticipated expiration: 2022-08-16
Also published as: CN100416284C

Abstract

A device and method for testing electric cable is disclosed. Said method includes generating standard test vector in the test vector generating and testing device, connecting a segment of standard cable respectively to JTAG devices A and B to obtain standard test output vectors, connecting the cable to be tested respectively to said JTAG devices A and B to obtain its test output vectors, and comparing obtained both output vestor tables with each other to determine if the cable to be tested is good.

Description

A kind of cable test device and method

Technical field

The invention belongs to measurement mechanism and method class, relate in particular to the proving installation and the method for cable.

Background technology

In communication apparatus (or other electronic equipment), used a large amount of cables, as the backboard cable etc., each module that is used for connected system inside is transmitted communication signal.Usually to carry out on off test and short-circuit test to this cable.Because this cable detection is often by production firm oneself definition, promptly every cable core should be distinguished which pin of stube cable two ends plug, and these are all defined by manufacturer oneself, so such diversity that has just formed wireline test.

Usually on manufacturing line, the manufacturer that has is the method for utilization manual test, promptly utilizes multimeter that each root core of cable inside is carried out on off test, and this is the very low method of testing of a kind of efficient.Although the manufacturer that has has designed the testing apparatus of oneself,, utilize MCU to send test vector because inside has used single-chip microcomputer (as 8051 etc.) to do main control MCU.Be that a kind of new cable of every increase just needs to generate the new test vector of a cover, so all upgradings possibly of software and hardware.In the face of miscellaneous cable, this equipment still lacks dirigibility.

Also have, on patent website, see and utilize LED to identify the cable break-make and utilize MCU to make two kinds of methods of cable testing equipment:

One, the method for utilizing LED to come test cable adds a LED exactly at the two ends of cable.When to cable testing equipment two ends making alive,, otherwise then do not work if cable general rule LED is bright.Also be useful on the LED of sign cable short circuit in the testing apparatus.Obviously, need a large amount of LED on this equipment, intuitive is very poor.Especially when the cable core number was very big, the LED on the equipment can be multiplied, and was a kind of relatively more clumsy method for designing.

Its two, utilize MCU to design the method for cable testing equipment, it has introduced the notion of test vector, does not send but test vector is not serial, but sends by the bus parallel of MCU.This method has been enumerated an example, is to design with 8051.Have only 8 because of being limited by 8051 highway width, so if bus is not expanded, this method for designing itself can only be tested the cable of 8 cores at most.Test cable if desired, then need the expansion bus width, and increase expansion parallel port chip greater than 8 cores.Such as saying, for a kind of cable (this is a kind of backboard cable of often using in the communication facilities) of 96 cores, just need add 96 ÷ 8=12 expansions parallel ports and corresponding driving circuit, the circuit design more complicated that will seem like this, reliability also can descend.The upgrading, software may also will be upgraded on hardware, regenerate to be applicable to that big core counts the test vector of cable.Certainly, can introduce the enough big MCU of highway width, but cost can increase greatly, and the MCU highway width of Mainstream Packs can not surpass 64 at present, therefore equally can't satisfy big core yet and count the needs that cable is measured in this design the inside yet.

Summary of the invention

The purpose of this invention is to provide a kind of cable test device and method, solve an above-mentioned difficult problem, to satisfy the needs that any cable is tested fast.

The object of the present invention is achieved like this: a kind of cable test device is generated and checkout equipment by test vector, and cable test module is formed, cable test module is made of JTAG device A, cable plug A, JTAG device B, cable plug B, test vector generates and an end and JTAG device A, the cable plug A of checkout equipment are linked in sequence, and test vector generates and the other end and JTAG device B, the cable plug B of checkout equipment are linked in sequence.

A kind of method of testing of cable test device comprises the following steps:

1, in test vector generation and checkout equipment, generate the standard input test vector;

2, the two ends of a segment standard cable of tested cable are generated with test vector respectively and checkout equipment in the cable plug A of JTAG device A and the cable plug B of JTAG device B couple together;

A. import the standard input test vector by test vector generation and testing apparatus to cable test module;

B. with of the boundary scan unit serial transmission of standard input test vector, until each boundary scan unit of JTAG device A and JTAG device B is all filled up at JTAG device A and JTAG device B;

C. JTAG device A is carried out one and write out operation, and then JTAG device B is carried out one read in operation, the data that JTAG device A is write out are read into the inner boundary scanning unit the inside of JTAG device B;

D. continue to make the inner data serial transmission in the boundary scan unit of JTAG device B of JTAG device B boundary scan unit, until output JTAG device B;

E. received the output data of JTAG device B by test vector generation and checkout equipment, these data are the standard testing output vector of a segment standard cable of tested cable;

3, the two ends of tested cable are generated with test vector respectively and checkout equipment in the cable plug A of JTAG device A and the cable plug B of JTAG device B couple together;

E. received the output data of JTAG device B by test vector generation and checkout equipment, these data are the test output vector of tested cable;

4, generate and checkout equipment by test vector, the standard testing output vector of a segment standard cable of the test output vector of tested cable and this cable is compared, if both are identical, the annexation of then tested cable inside is correct; Otherwise, promptly know the connection error of tested cable inside, i.e. short circuit or open circuit.

Because the present invention has adopted above technical scheme, thereby has following advantage:

1, the chip-count of use is few, has only used two JTAG devices, and hardware design is very simple, so have incomparable advantage at aspects such as reliability, price, portability.

2, simplicity of design, the reliability height, cheap, equipment is small and exquisite, and is easy to maintenance, has adaptivity, and soft, hardware need not be upgraded basically, just can satisfy the needs that any big core is counted wireline test.

Description of drawings

Fig. 1 is the basic principle schematic of a kind of boundary scan technique of the present invention;

Fig. 2 is a kind of schematic block diagram of utilizing boundary scan technique to carry out wireline test of the present invention;

Fig. 3 is the schematic block diagram of a kind of cable test device of Fig. 2;

Fig. 4 is the schematic flow sheet of a kind of wireline test method of the present invention;

Fig. 5 is the test environment example schematic of a kind of cable test device of the present invention.

Among the figure:

1, test vector generates and checkout equipment 2, cable test module 3, JTAG device A

4, JTAG device B 5, boundary scan unit 6, serial data input pin (TDI)

7, serial data output pin (TDO) 8, cable plug A 9, cable plug B

10, cable under test

Embodiment

Below in conjunction with accompanying drawing enforcement of the present invention is done as detailed below:

In Fig. 1, existing large scale integrated circuit all provides the mechanism of JTAG mouth and boundary scan.In such integrated circuit, each pin is all corresponding one by one with a boundary scan unit of JTAG device inside.

Be provided with two JTAG device A3 and JTAG device B4 in the drawings with JTAG mouth.By controlling its JTAG mouth, one group of serial data can be input to the JTAG device A3 from serial data input pin (TDI) (Serial Data In) 6, after these group data are passed through each boundary scan unit (Boundary-Scan Cell) 5 of JTAG device A3 inside more successively, transferred out by serial data output pin (TDO) 7 at last from JTAG device A3.Because boundary scan unit 5 is positioned at the outermost border (because outer limit has been exactly a pin again) of device, the process of such serial data serial transmission in each boundary scan unit 5 just is called boundary scan.

Among the figure, the serial data output pin 7 of JTAG device A3 is connected with the serial data input pin 6 of JTAG device B4.If data continue serial transmission, data can be enclosed in the boundary scan unit 5 of JTAG device B4 in serial transfer one, and the serial data output pin 7 from JTAG device B4 transfers out at last.

Lift an example again, the pin of JTAG device A3 and the pin of JTAG device B4 are connected, and might as well be called pin a and pin b to these two pins respectively.When serial data transmission during, can allow data from the output of a pin, so data will be transferred to pin b from pin a by the JTAG mouth of control JTAG device A3 to the boundary scan unit 5 of the pin a of JTAG device A3.Then, by the JTAG mouth of control JTAG device B4, the inner boundary that the data on the pin b is read into pin b correspondence scans first 5 the insides again.Then, these data continue to transmit in each boundary scan unit of JTAG device B4, up to exporting from serial data output pin 7.At this moment, just can be checked through the data that transmit from pin a at serial data output pin 7 places of JTAG device B4.If check less than, illustrate that then the connection between a and the b has been broken, short circuit phenomenon has perhaps taken place.

Here it is boundary scan and the ultimate principle of in on-line testing, using thereof.

In Fig. 2, cable test device is generated by test vector and checkout equipment 1 and cable test module 2 are formed.Cable test module 2 is made of JTAG device A3, cable plug A8, JTAG device B4, cable plug B9.Test vector generates and an end and JTAG device A3, the cable plug A8 of checkout equipment 1 are linked in sequence, and test vector generates and the other end and JTAG device B4, the cable plug B9 of checkout equipment 1 are linked in sequence.During detection, cable under test 10 is connected between cable plug A8 and the cable plug B9.

In Fig. 3, shown a JTAG device that 9 pins are arranged.As we can see from the figure, serial input data is first serial data input pin (TDI) 6 inputs from JTAG device 3A3, enter into boundary scan unit 5 the insides of JTAG device A3 inside,---being last pin---the corresponding boundary scan unit 5 that enters into the 9th the serial data output pin (TDO) 7 of JTAG device A3 at last is then from serial data output pin (TDO) 7 outputs.The serial data output pin (TDO) 7 of JTAG device A3 links to each other with the serial data input pin (TDI) 6 of JTAG device B4.So data continue transmission in the boundary scan unit 5 of JTAG device B4 inside, export from the serial data output pin (TDO) 7 of JTAG device B4 at last.

In test, at first import a string data to JTAG device A3, with this string data all boundary scan units of JTAG device A3 and JTAG device B4 are filled up.Such as the data of input finally are to insert 0 in first boundary scan unit the inside of JTAG device A3, and insert 1 in other all boundary scan unit 5 the insides.Control the JTAG mouth of two devices then, allow them all carry out an operation of writing out, data are written out to above separately the pin.If first pin of JTAG device A3 is connected by cable core with some pins of JTAG device B4, the pin 3 that connects JTAG device B4 such as the pin one of JTAG device A3, so because the pin one of JTAG device A3 output 0, pin 3 outputs 1 of JTAG device B4, two signal wires promptly obtain signal 0 with once.And then control JTAG device A3 and JTAG device B4 carry out and read in action, and the pin 3 of JTAG device B4 just has been read into inner boundary scan unit 5 the insides to 0.And then control JTAG device A3 and JTAG device B4 proceed the serial transmission action of data, the data of 9 boundary scan unit 5 the insides of JTAG device B4 inside are all exported from serial data output pin (TDO) 7, in output data, on the shared position of the pin 3 of JTAG device B4, data 0 should be arranged so.If do not have annexation between the pin 3 of the pin one of JTAG device A3 and JTAG device B4, so since the output of the output of JTAG device A3 pin one and JTAG device B4 pin 3 can't line with, the data at pin 3 places of JTAG device B4 still should be 1 (before action are read in execution), so from the test data of JTAG device B4 output, the pin 3 shared locational data of JTAG device B4 should be 1 at last.From top description as can be seen, on the output data of JTAG device B4, just can judge two annexations between the pin.

In like manner, if the pin of JTAG device A3 is not to link to each other with the pin 3 of JTAG device B4, but link to each other with the pin of other JTAG device B4, that pin should be one 0 on the shared position in output data so; If any pin of JTAG device A3 pin one discord JTAG device B4 is connected, data on the JTAG device A3 pin one can not pass on the JTAG device B4 when action is write out in execution so, just can not influence the output data of JTAG device B4 yet, because beginning most when when data are filled out by all inner boundary scanning units 5 of JTAG device A3 and JTAG device B4, fill out 0 in the boundary scan unit 5 of the pin one correspondence of JTAG device A3, what all the other were filled out all is 1.If the data of JTAG device A3 pin one (being data 0) can't pass to JTAG device B4 from cable core, JTAG device B4 only can go 1 output that begins most to its inside is filled out.

Be test data above at the pin one input of JTAG device A3.After this pin examination is finished, can import similar test data to the pin two of JTAG device A3, promptly in the boundary scan unit 5 of pin two correspondence, insert data 0, boundary scan unit 5 the insides at other all insert 1, and then carry out and to write out, to read in and action such as serial transmission, by checking the output data of JTAG device B4, just can know that the pin two of JTAG device A3 is connected with that pin of JTAG device B4.

Repeat above-mentioned action, just know the annexation between JTAG device A3 and all pins of JTAG device B4.

From the above mentioned, the serial test data of this each input is exactly required test vector.From top description process, can see, in the wireline test process, need each, all pins of JTAG device A3 and JTAG device B4 and inner boundary scanning unit 5 thereof are all covered to the cable testing equipment input test vector; The output vector that generates according to different test vectors just can be known the annexation of cable or know whether cable connects correct then.

In Fig. 4, the operating process of wireline test method is specific as follows:

1, generate the standard testing vector, and standard output test vector;

2, begin test, and the output test vector, and judge whether test vector result and standard testing vector be identical;

3, judge whether test vector result and standard testing vector be identical:

If then cable is correct,

If not, then cable is incorrect,

And, continue to do this class wireline test;

4, this class wireline test is tested:

If, then do to begin test again,

If not, then carry out the new cable test;

5, new cable is tested,

If, then generate the standard testing vector, and standard output test vector,

If not, then test process finishes.

In said process, when will test, at first to look for the standard cable of one section tested cable to tested cable, generate the standard output test vector table of the tested cable of this section (standard cable) with the standard testing vector.Then, when tested cable is tested, as long as, generate the output test vector table of tested cable according to exporting test vector epiphase method together with the generation standard.At last,, compare,, tested cable non-fault is described then, otherwise illustrate that this cable has fault (short circuit or open circuit) if come to the same thing with the standard of standard cable output test vector table the output test vector table of tested cable.

In Fig. 5, show and utilize a computer to generate and checkout equipment 1 that computer is also as control desk simultaneously as the wireline test vector.Computer inside is provided with test procedure, finishes such as JTAG mouth control, generates test vector, carries out action such as output vector detection.Simultaneously,, and provide man-machine interface, tell the situation of user's wireline test as control desk.

Wherein, cable test module 2 can be connected to form by EPLD chip and some cable plug A8, the cable plug B9 of two 144 pin.The connector of a JTAG mouth also is provided on cable test module 2, and it is used for the JTAG mouth of EPLD is connected to the parallel port of computer.

The JTAG mouth of computer control EPLD is controlled by the parallel port.What connect computer parallel port and EPLD JTAG mouth usefulness is that cable EPLD logic is downloaded line.In fact this root stube cable does not need to download line with special EPLD logic.Because control JTAG mouth mainly needs four signal wire: TDI, serial data output pin (TDO) 7, TCK and the TMS of JTAG mouth, so just can make a cable by oneself, just passable as long as this root cable can guarantee that these four signal wires can be connected on the data line of computer parallel port.

TDI is the data line of test vector input, and serial data output pin (TDO) the 7th, the data line of test vector output, TCK are the clock lines of control JTAG mouth, and TMS is the control signal wire of control JTAG mouth internal state machine.How control data writes out the JTAG etc. that reads in, resets in the 5 the inside serial transmissions of boundary scan unit, input as for these four lines, it can be referring to the IEEE.1194.1 standard, perhaps with reference to the handbook of JTAG device, the handbook of all JTAG devices all provides these data basically.The parallel port can be found by the data of PC in the address of computer inside, and this also is a standard.

Claims

1. the device of a wireline test, it is characterized in that, cable test device is generated and checkout equipment by test vector, and cable test module is formed, cable test module is made of JTAG device A, cable plug A, JTAG device B, cable plug B, test vector generates and an end and JTAG device A, the cable plug A of checkout equipment are linked in sequence, and test vector generates and the other end and JTAG device B, the cable plug B of checkout equipment are linked in sequence.

2. a kind of cable test device according to claim 1 is characterized in that, cable test module is connected to form by EPLD chip and some cable plug A8, the cable plug B9 of two 144 pin.

3. the method for testing of a kind of cable test device according to claim 1 comprises the following steps:

1) in test vector generation and checkout equipment, generates the standard input test vector;

2) two ends of a segment standard cable of tested cable are generated with test vector respectively and checkout equipment in the cable plug A of JTAG device A and the cable plug B of JTAG device B couple together;

3) two ends of tested cable are generated with test vector respectively and checkout equipment in the cable plug A of JTAG device A and the cable plug B of JTAG device B couple together;

4) generated and checkout equipment by test vector, the standard testing output vector of a segment standard cable of the test output vector of tested cable and this cable is compared, if both are identical, the annexation of then tested cable inside is correct; Otherwise, promptly know the connection error of tested cable inside, i.e. short circuit or open circuit.