CN1475034A - 经降低线间电容及串话噪声的半导体器件 - Google Patents
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Abstract
本发明揭示一种晶体管器件(200)，该晶体管器件(200)含有设置于栅极(204)与漏极及源极线之间的绝缘材料，其中，该绝缘材料的介电常数等于或小于3.5。因此，可降低该栅极与该漏极及源极线之间的电容，由此改善降低了串话噪声的场效晶体管(200)的信号性能。
Description
技术领域
本发明涉及VLSI(超大规模集成电路半导体器件)，特别是涉及超高密度电路的半导体器件中的线间(line-to-line)电容及串话(cross talk)噪声。
背景技术
集成电路(IC)的制造过程涉及许多半导体器件的制造，例如单一基材上绝缘栅极场效应的晶体管。为具有提高的集成密度及改进的器件性能，举例来说，对于信号处理时间及功率损耗而言，半导体器件的部件(feature)尺寸正在稳定地减小。减小的部件尺寸具有各种优点，例如高封装密度及晶体管的切换期间由于减短的沟道长度导致的(电信号)升降的时间较短。然而，若部件尺寸进一步减小时，此类优点可能会受到如更高的互连电阻及相邻线间的耦合电容等缺点所抵销。再者，提高的电阻和/或电容耦合也会使沿该连接件传导的电气信号速度减缓。这一般可称为互连延迟(interconnect delay)。
大体而言，在部件尺寸，例如，栅极长度，为0.18μm量级的器件中，互连延迟开始主宰整体器件延迟，所以0.18μm及更小的器件部件将导致衰退的器件性能，因此将会限制，例如，CPU(中央处理器)的时钟频率。现代超高密度电路中，不仅互连延迟是重要的问题，而且局部互连件的形成，即用以连接场效晶体管的漏极及源极区域的互连件也是。现代集成电路的设计标准中，例如，在超高密度CMOS(互补金属氧化物半导体)电路中，要求栅极与局部互连件之间要有介于10至250nm的小距离。若形成个别局部互连件的开孔时发生轻微失准时，此类距离甚至又更短。
为了清晰见，说明了典型的现有技术流程，并参考图1a和1b以详细说明在现代集成电路的互连件的形成中所涉及的部分问题。本领域的技术人员将易于理解，说明现有技术加工的图都是概略图，以明显的线显示的过渡(区)和边界可能并不代表真实器件中的明显的过渡(区)。而且，典型的现有工艺流程的说明指标准制造过程而没有指出用于这些过程的典型参数值，因为单个加工步骤可被相应改进以满足具体的涉及要求。
图1a显示具体制造阶段时的场效晶体管器件的概略剖面示意图。在半导体基材1中，以浅跨绝缘区(trans-isolations)2界定晶体管区域。栅极4于基材1上形成并且由栅极绝缘层3隔离。在栅极绝缘层3附近形成轻掺杂区5。本领域的技术人员将明了该栅极4可由DUV(深紫外线)掩膜技术形成，然后，再由离子植入形成轻掺杂区5。
图1b概略地显示更先进的制造阶段的场效晶体管的剖面示意图。侧壁间隔物7形成并且沿着该晶体管的宽度延伸，将该方向界定为垂直于图1b图式平面的方向，使邻近该栅极4的侧壁。另一方面，该栅极4的侧面尺寸通常指长边。例如，该栅极4的宽度，即，图1b所示的侧壁间隔物7之间的距离，通常指该晶体管的栅极长度。此外，形成漏极及源极区域6。该侧壁间隔物7的形成可由二氧化硅或氮化硅或氧氮化硅层沉积及随后的各向异性蚀刻执行。此类材料的介电常数k通常介于3.9至6之间，视所用沉积工艺的类型而定。形成该侧壁间隔物7之后，由离子植入及本领域的技术人员熟知的快速热退火形成高度掺杂源极。
图1c显示另一先进制造阶段的晶体管器件的概略剖面示意图。介电材料8的间层于该结构上形成并且包括至少分别部分地暴露出漏极及源极表面的开孔9。形成该开孔9及间层8的典型工艺流程一般称为局部互连(LI)工艺顺序，通常包含以下步骤。首先，利用化学气相沉积(CVD)以TEOS(四乙氧基硅酸盐)沉积介电材料间层(ILD)8。接着，该ILD8的表面由化学机械抛光(CMP)而平面化。之后，由标准掩膜及蚀刻技术形成呈通孔(vias)或线(lines)形式的开孔9。大体上，由图1c可见到该开孔9形成期间的轻微失准，所以，通常该开孔9至该栅极4的距离都无法精确地达到一致。
图1d概略地显示图1c中开孔9填满金属，例如钨，的晶体管器件，以便提供连至该漏极及源极区域6的电气连接。然后，执行另一CMP工艺使该ILD8及该开孔9中的金属变平。本领域的技术人员将明了可在金属填满开孔9之前沉积薄的阻挡层(未示出)。
在现代超高密度半导体电路中栅极4与开孔9中的金属之间的距离介于20至250nm。此距离甚至还可更小，根据开孔9形成期间所发生的任何量级的失准而定。该金属与该栅极之间形成的寄生电容和该金属与该栅极之间的距离成反比，因此，切换晶体管的时间常数将会随着该金属与该栅极之间距离缩短而增加。而且，漏极与源极区域之间的串话噪声也将随着距离缩短而增加。结果，超高密度半导体电路中，稳定地缩短晶体管长度，即，栅极长度，所获得的益处至少有部分将会被源极及漏极线与栅极之间缩短的距离所抵销，因此造成增加的寄生电容及串话噪声。
回顾以上所述，需要漏极及源极区域与栅极之间具有低电容的改进场效晶体管以改善超高密度半导体电路的器件性能。
发明揭示
根据本发明的一个实施方案，在制于基材上的集成电路中设置一场效晶体管，该场效晶体管包括有沿该晶体管宽度方向延伸的相对侧壁的栅极，该栅极于基材上形成并且由栅极绝缘层与基材分隔，至少部分于漏极区域形成的漏极线，该漏极线电连接至该漏极区，至少部分于源极区域形成的源极线，该源极线电连接至该源极，该漏极线与该源极线电绝缘并且由与该栅极由侧壁间隔物隔开，该侧壁间隔物包括介电常数等于或小于0.35的材料。
根据本发明的一个实施方案，在制于基材上的集成电路中设置一场效晶体管，该场效晶体管包括有沿该晶体管宽度方向延伸的相对侧壁的栅极，该栅极于基材上形成并且由栅极绝缘层与基材分隔，至少部分于漏极区域形成的漏极线，该漏极线电连接至该源极，该漏极线至少部分于漏极区域上形成，至少部分于源极区域形成的源极，该源极线电连接至该源极，该漏极线与该源极线呈电绝缘并且与该栅极由侧壁间隔物隔开，其中漏极线与该栅极之间的距离与该侧壁间隔物的介电常数的比率，以及该源极线与该栅极之间的距离与该侧壁间隔物的介电常数的比率都等于或小于0.35nm-1。
根据本发明又一实施方案，提供一制造场效晶体管的方法，包括以下的步骤：提供一有表面的基材，在该基材中形成活性区域，在该基材上形成栅极，该栅极由栅极绝缘层与基材形成电绝缘，形成邻接于该栅极的介电侧壁间隔物并且依该晶体管的宽度方向沿着该栅极延伸，该侧壁由介电常数等于或小于3.5的材料组成，在邻接于该栅极的活性区域中形成漏极及源极，在该基材上沉积绝缘层，分别地，至少部分形成开孔于漏极及源极区域，以导电性材料填满该开孔以形成漏极线及源极线，其中该侧壁间隔物有助于该栅极与该漏极线及该源极线间的电绝缘和空间上隔离。
因为该漏极区域或该源极区域与该栅极之间的电容取决于该侧壁间隔物的介电常数“k”并且与该漏极线或该源极线与该栅极之间的间隔成反比，超高密度半导体电路中通过减小所述距离而增加的该电容可由低k材料形成的侧壁间隔物而获得有效地补偿。与现有技术中包含由介电常数介于3.9至6之间的氧化硅、氮化硅或氧氮化硅形成的侧壁间隔物的器件相反，本发明提供由介电常数介于3.5至1.3以下的材料制成的侧壁间隔物的场效晶体管。因此，本发明能使晶体管器件减得更小，从而避免由提高的栅极与源极之间和/或栅极与漏极之间的电容及串话噪声而造成器件性能的衰退。
附图简单说明
由以下的详细说明对照附图，将可使本发明其它的优点更加显而易见，其中：
图1a概略地显示一具体制造阶段的场效晶体管的剖面图；
图1b概略地显示一先进制造阶段中场效晶体管器件的剖面图，该图说明根据典型的现有工艺形成的侧壁间隔物；
图1c概略地显示沉积介电材料间层且在该介电材料间层中形成开孔之后的场效晶体管的剖面图；
图1d概略地显示在图1c中所说明的间层的开孔中形成漏极及源极线的制造阶段的场效晶体管的剖面图；
图2a概略地显示依据本发明一具体制造阶段的场效晶体管的剖面图；以及
图2b概略地显示图2a的场效晶体管在另一先进制造阶段中剖面图。
尽管本发明参照如下详细说明中说明的具体实施方案以及附图而加以说明，但要了解以下的详细说明以及附图并不会使本发明限于所揭示的具体实施方案，所述的具体实施方案仅例示本发明各实施方案，本发明的范围由权利要求界定。
实施方式
由以下的详细说明及权利要求将使本发明的其它的优点及目的更加显而易见。而且，要注意尽管本发明对照如以下详细说明所述的具体实施方案加以说明，但要了解以下的详细说明并不会使本发明限于该特定具体实施方案所揭示的，所述的具体实施方案仅例示本发明各实施方案，本发明的范围由权利要求界定。
图2a概略地显示依据本发明的一特定制造阶段的场效晶体管200的剖面图。图2a中，浅沟槽绝缘层202形成于基材201中，该基材201可以是一适当的半导体基材，例如硅或绝缘性基材，例如玻璃，并且由该基材201界定该晶体管200的活性区域。该晶体管200的活性区域中，形成含有轻掺杂区域205的漏极及源极区域206。栅极204位于该晶体管200的活性区域上并且经由栅极绝缘层203与该晶体管200隔离。侧壁间隔物207沿着该栅极204的相应侧壁形成并且沿着该晶体管200的宽度方向延伸。
如图2a所说明用于形成该场效晶体管200的部件的工艺流程可包含以下的步骤。等标准栅极形成之后，例如，参照图1a至1d所说明的，由离子植入形成轻掺杂区域205之后，该侧壁间隔物207由介电常数等于或小于3.5的材料沉积而成。适用于侧壁间隔物207的材料包含氧氟化硅(F-SiO2，k＝2.6至3.5)、氢硅倍半环氧乙烷(hydrogensilsesquioxane，HSQ)、氟化聚酰亚胺、聚对二甲苯、聚萘、聚四氟乙烯(p-TFE)、甲基硅倍半环氧乙烷(methylsilsesquioxane，MSQ)、全氟环丁烯、纳米多孔二氧化硅(nano porous silica)以及混成硅倍半环氧乙烷(hybrid silsesquioxane)。HSQ及氟化氧化物分别具有3.0及3.5的k值，然而有机聚合物如聚对二甲苯则具有3.0以下的k值。k值大于2.0的有纳米多孔二氧化硅薄膜、多孔质聚合物及P-TFE。此类低k材料可由，例如，等离子体强化的CVD或高密度等离子体CVD沉积。因为通常沉积工艺的类型都会影响被沉积层的k值，所以特定材料的各个低k值皆可由使用不同的沉积方法或由改变该沉积方法的参数值而获得，这已从如氧化硅等先前间隔物材料加工中获知。
图2b概略地显示图2a中先进制造阶段的场效晶体管200。在栅极204及该侧壁间隔物207上方，形成绝缘层208，漏极及源极线210邻接于该绝缘层。该漏极及源极线210可形成导孔、线路或二者组合的形式，视设计需要而定。如上述所指出的，该漏极及源极线210也可称为局部互连件。
如上述参照图1a至1d，绝缘层208形成于该结构上，然后被平面化，且形成部分暴露漏极和源极区206的开口209。之后，可沉积薄的阻挡层(未示出)，例如硅化钴或硅化钛层，以覆盖开孔209的表面。接着，以金属，例如钨，填注该开孔209，再用CMP使所得的结构平面化。栅极204及漏极或源极线210之间的距离，亦称为距离“d”，视用于漏极及源极线210的开孔209形成期间的对准精确度而定。因为晶体管长度尺寸正在稳定的减小，所以现代集成电路中的距离211通常介于10至250nm，发生某程度失准时甚至更小。
栅极204与漏极及源极线210之间的电容正比于k/d，其中“k”位于源极及漏极线210与栅极204之间的材料的介电常数。要注意k/d比必须乘以电场常数ε0(8.8542×10-12As/Vm)才能获得绝对值。因此，根据本发明减短的距离“d”由较低的“k”值补偿，由此使用如现有技术的更小的距离“d”不会造成该晶体管器件性能的恶化。对于低k材料的材料类型和/或沉积工艺的类型可经选择以调节侧壁间隔物207的“k”值以便源极线的“k”值与距离“d”的比率，以及漏极线的“k”值与距离“d”的比率都等于或小于0.35nm-1，或使用绝对值时，约等于或小于3.099×10-3As/Vm2。这表示本发明建议，例如，最小距离“d”为10nm需要“k”值等于或小于3.5的介电材料，距离“d”为8nm需要“k”值为2.8的材料，等等。因此，根据本发明，对施加于该场效晶体管的栅极、漏极及源极的规定电压，可选择该侧壁间隔物材料的“k”值使对于取决于设计标准及工艺精确度的最小距离“d”、栅极与漏极及源极线210之间的电容等于或小于3.099×10-3As/Vm2。
而且，尽管本发明已说明钨为用于漏极及源极线210的金属，然而，要注意任何适当的材料，如铜、铝等，亦可使用。再者，本发明在栅极长度等于或小于0.2μm的晶体管器件中特别有用，因为此类晶体管器件通常具有250nm或更小的线与栅极距离。
尽管本发明参照半导体基材，如硅，上形成的场效晶体管而加以说明，但要注意本发明亦可应用于任何适当基材上形成的任何场效晶体管。例如，该场效晶体管可以SOI(氧化物上覆硅)器件的形式形成，或可以形成于绝缘性基材或如III-V或II-VI半导体等其它半导体基材上。
上述的具体实施方案仅供说明，而本发明可以本领域的技术人员所已知并得益于本文所教示的不同但等效的方法加以修改及实现。例如，上述加工步骤可依不同顺序执行。再者，除了以下权利要求所说明的以外，本文所示的结构或设计并没有限制。因此很明显，以上揭示的具体实施方案可变化或修改，并且所有此类变化都包含于本发明的范围及精神内。因此，本文所欲保护的范围如权利要求所提出者。
Claims (17)
1.一种场效晶体管器件(200)，其位于基材上所制造的集成电路中，其包括：
一栅极(204)，含有沿着所述晶体管(200)的宽度方向延伸的相对侧壁，所述栅极(204)于基材(201)上方形成且由栅极绝缘层(203)与基材(201)隔离；
一漏极线，至少有部分在漏极区域上方形成，所述漏极线电连接至所述漏极区域；以及
一源极线，至少有部分在源极区域上方形成，所述源极线电连接至所述源极区域，所述漏极线及源极线呈电性绝缘的状态且由介电常数等于或小于3.5的材料组成的侧壁间隔物(207)与所述栅极(204)隔离。
2.如权利要求1所述的场效晶体管器件，其中，所述侧壁间隔物(207)包括由氧氟化硅、氢硅倍半环氧乙烷、氟化聚酰亚胺、聚对二甲苯、聚萘、聚四氟乙烯、甲基硅倍半环氧乙烷、全氟环丁烯、纳米多孔二氧化硅以及混成硅倍半环氧乙烷材料组中的一种。
3.如权利要求1所述的场效晶体管器件，其中，所述栅极的长度小于0.2μm。
4.如权利要求1所述的场效晶体管器件，其中，所述漏极线及所述源极线包括钨、铝及铜中的一种。
5.如权利要求1所述的场效晶体管器件，其中，所述基材(201)是半导体基材。
6.一种场效晶体管器件(200)，其位于基材上所制造的集成电路中，其包括：
一栅极(204)，含有沿着所述晶体管的宽度方向延伸的相对侧壁，所述栅极(204)于基材(201)上方形成且由栅极绝缘层(203)与基材(201)隔离；
一漏极线，至少有部分在漏极区域上方形成，所述漏极线电连接至所述漏极区域；以及
一源极线，至少有部分在源极区域上方形成，所述源极线电连接至所述源极区域，所述漏极线及源极线与所述栅极由一侧壁间隔物(207)电绝缘且空间上隔离，其中所述漏极线和所述栅极之间距离与所述侧壁间隔物(207)的介电常数的比率乘电场常数ε0，与所述源极线和所述栅极之间距离与所述侧壁间隔物(207)的介电常数的比率乘电场常数ε0皆等于或小于3.099×10-3 As/Vm2。
7.如权利要求6所述的场效晶体管器件，其中，所述侧壁间隔物(207)包括由氧氟化硅、氢硅倍半环氧乙烷、氟化聚酰亚胺、聚对二甲苯、聚萘、聚四氟乙烯、甲基硅倍半环氧乙烷、全氟环丁烯、纳米多孔二氧化硅以及混成硅倍半环氧乙烷材料组中的一种。
8.如权利要求6所述的场效晶体管器件，其中，所述栅极的长度小于0.2μm。
9.如权利要求6所述的场效晶体管器件，其中，所述漏极线及所述源极线包括钨、铝及铜中的一种。
10.如权利要求6所述的场效晶体管器件，其中，所述基材为半导体基材。
11.如权利要求6所述的场效晶体管器件，其中，所述基材为绝缘基材。
12.一种制造场效晶体管的方法，其包括以下的步骤：
制备有表面的基材(201)；
在所述基材(201)中形成一活性区域；
在所述基材(201)上形成栅极(204)，所述栅极(204)由栅极绝缘层(203)与所述基材(201)形成电绝缘；
形成邻接于所述栅极(204)的介电侧壁间隔物(207)并且依所述晶体管的宽度方向沿着所述栅极延伸，所述侧壁间隔物(207)由介电常数等于或小于3.5的材料组成；
在邻接于所述栅极的活性区域中形成漏极及源极；
在所述基材(201)上沉积绝缘层(208)；
分别在所述漏极及源极区域至少部分形成开孔；以及
以导电性材料填注所述开孔以形成漏极线及源极线，其中，所述侧壁间隔物(207)有助于所述栅极与所述漏极线和所述源极线间的电隔离和空间上隔离。
13.如权利要求12所述的方法，其中，所述侧壁间隔物(207)包括由氧氟化硅、氢硅倍半环氧乙烷、氟化聚酰亚胺、聚对二甲苯、聚萘、聚四氟乙烯、甲基硅倍半环氧乙烷、全氟环丁烯、纳米多孔二氧化硅以及混成硅倍半环氧乙烷材料组中的一种。
14.如权利要求12所述的方法，其中，所述栅极(204)的长度小于0.2μm。
15.如权利要求12所述的方法，其中，所述漏极线及所述源极线包括钨、铝及铜中的一种。
16.如权利要求12所述的方法，其中，所述基材(201)为半导体基材。
17.如权利要求12所述的方法，其中，所述基材为绝缘基材。
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| CN102456736A (zh) * | 2010-10-29 | 2012-05-16 | 上海宏力半导体制造有限公司 | 一种沟槽式场效应管及其制备方法 |
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| Publication number | Publication date |
|---|---|
| EP1334522A1 (en) | 2003-08-13 |
| JP2004514294A (ja) | 2004-05-13 |
| WO2002041405A1 (en) | 2002-05-23 |
| CN1275331C (zh) | 2006-09-13 |
| AU2001296630A1 (en) | 2002-05-27 |
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