CN1474441A - 倒装片组装的底层填充封胶处理及其装置 - Google Patents

倒装片组装的底层填充封胶处理及其装置 Download PDF

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CN1474441A
CN1474441A CNA02127651XA CN02127651A CN1474441A CN 1474441 A CN1474441 A CN 1474441A CN A02127651X A CNA02127651X A CN A02127651XA CN 02127651 A CN02127651 A CN 02127651A CN 1474441 A CN1474441 A CN 1474441A
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heat
substrate
resistant film
support plate
slotted eye
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吴东升
徐家雄
黄富裕
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HUATAI ELECTRONICS CO Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/921Connecting a surface with connectors of different types
    • H01L2224/9212Sequential connecting processes
    • H01L2224/92122Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting

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  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

一种倒装片组装的底层填充封胶处理工艺及其装置,主要是先以一开有槽孔的载板来承载基板,此基板已焊上数排的倒装片(倒装晶片),其基板顶面紧靠载板的底面,而基板上的晶片则嵌于载板的槽孔内,再于载板的顶面与底面各以一适当大小的耐热胶片覆贴,使载板中央所设置的槽孔被基板的顶面与上耐热胶片的底面包覆而成一封闭空间,续于上耐热胶片及相对于载板的顶面开一浇道,以将底层填充胶灌于上述封闭空间的浇道内,并于载板的彼侧(即该封闭空间同一面的彼侧)开设一排气道,以将封闭空间内的空气抽出,使该底层填充胶快速充满该封闭空间,待该底层填充胶冷却后撕去顶面耐热胶片,并利用载板上所设计的定位孔切割成适当的倒装片来组装模块。

Description

倒装片组装的底层填充封胶处理及其装置
技术领域
本发明关于应用于新世代半导体组装技术中的倒装片组装(FlipChip Package)技术,主要是在集成电路的倒装片组装接合时,在其倒装片与其所焊接的基板间的空间内灌入底层填充胶(Under Fill)的新的处理工艺。
技术背景
一般而言,在传统的倒装片组装技术之中,底层充填胶体的组装在处理的加工应用上(如图1所示),是将倒装片装配于基板后,使用点胶的方式于该倒装片边缘(1~2边)灌入胶体,使藉由毛细现象将液态胶材吸入,并由未灌胶的一边排出空气,以填灌晶片与基板间的间隙,然后再作热硬化处理。
上述的填胶技术并不易应用于面积较大或凸块密度高的晶片,于填胶过程中在晶片与基板之间容易产生孔洞(void)的问题,填胶作业后,晶片周围的填充物高度不易控制,假使填充物高度不及晶片厚度一半者,经过性赖度测试后容易产生填充胶体龟裂,尤其是在晶片的角落处最为严重;且传统的技术一次只能处理单一晶片的填胶作业,有产能低且提高成本的缺点。另外,现有的点胶技术利用毛细管原理填胶,其所产生的流动力有限,不易应用于面积大的晶片。又在晶片凸块密度高的情形下,其间隙过小,不易填胶,且若晶片上的凸块为非对封称分布时,更易影响填胶物流速,使填充条件不易控制。因此,必须对传统的点胶处理加以改进。
发明内容
有鉴上述现有点胶处理的缺点,本发明的首要目的是提供一种新的倒装片组装的底层充填封装胶的处理工艺,以一载板框覆基板及晶片,并以两片片适当大小的上、下耐热胶片覆盖载板的顶面及底面以形成一包含底层空间的长条密闭空间,在该空间内一端灌胶、另一端抽出空气,从而使得底层充填胶快速充填整排晶片与基板之间,晶片周围的填充物高度易控制又呈一致性,且不易产生气泡,提高加工良率及生产能力,进而提升产品的竞争力。
本发明的次要目的是应用上述的新颖的处理工艺,将与多片晶片倒装片接合的基板一次填充底层充填胶完毕,省去逐一点胶并等候冷却的宝贵时间,提高处理效率。
附图说明
图1A-1C是现有技术中应用于倒装片组装的底层充填胶的传统点胶处理工艺的示意图。
图2是本发明的结构示意图。
图3A-3D是本发明的处理工艺。
现有技术中:
1’.基板           11’.脚垫
2’.晶片           21’.凸块
3’.底层填充胶
4’.助焊剂
本发明中:
1.载板
11.槽孔            12.浇道
13.抽气道           14.定位孔
2.上耐热胶片
21.灌胶孔           22.抽气孔
3.下耐热胶片
4.包覆空间
5.底层填充胶
6.基板              61.脚垫
7.晶片              71.凸块        72.助焊剂
8.注射器
9.抽取器
具体实施方式
现配合附图及较佳实施例说明上述的处理工艺及其装置:参考图2所示,本发明使用一载板1、一上耐热胶片2、一下耐热胶片3来包覆一基板6(基板6己与晶片7接合完成),以形成一类似模穴的包覆空间4,并在其包覆空间4内一端灌入底层填充胶5,同时一端抽出其包覆空间4内的空气,其中:
载板1为一比欲加工的基板6宽的硬板,且在其中央开设有一槽孔11,该槽孔11的宽度与长度均略小于基板6,但不得窄于基板6上的晶片7的宽度,在其槽孔11的窄边中心分别设有一向外延伸出的浇道12与抽气道13,且载板1上依需要设有定位孔14。
上耐热胶片2,为一具粘性的高耐热片,剪裁适当长度及宽度后,贴覆于载板1的顶面,整个覆盖住槽孔11、浇道12及抽气道13,并在对应浇通12末端之处开设一灌胶孔12,及对应抽气道13的位置设一抽气孔22。
下耐热胶片3,为一具粘性的高耐热片,可自载板1的底面进行包覆。依上述构件,其处理工艺为:
a)先将晶片7的凸块71使用助焊剂72加以热处理后焊于基板6上,且同一基板6可连接数枚晶片7(如图a所示)。
b)将焊毕的晶片7及基板6置于载体1内的槽孔11下方,使其基板6的顶缘抵住槽孔11的底缘,而基板6上的晶片7则位于槽孔11内,然后以上耐热胶片2贴于载板1的顶面,并完全覆盖住其槽孔11,其上耐热胶片2的底缘贴于晶片7的顶缘,且其灌胶孔21恰位于浇道12的正上方,其抽气孔22恰位于抽气道12正上方;同时以下耐热胶片3覆贴于基板6底面与载板1底面,将基板6完全包覆于载板1下方,使由槽孔11形成的四周围、基板6顶面形成的底面及上耐热胶片2底面形成的顶面组成一包覆空间4(如图3b所示)。
c)以灌胶注射器8对准上耐热胶片2的灌胶孔21,同时以抽取器9对准上耐热胶片2的抽气孔22,以适当的速度,同步将底层填充胶5灌入包覆空间4并抽出包覆空间内的空气(如图3c所示)。
d)热硬化处理后,撕去上耐热胶片2及下耐热胶片3,使完成底层充填胶5的封胶作业,并依载板1上的定位孔14予以裁切成适当的单一模块(如图3d所示)。
 依前所述,本发明可一次制作一条基板上的晶片底层填胶的作业,并使填胶区暂处于包覆密闭的空间之中,一端灌胶一端抽出空气,使填胶作业迅速完成,完全没有现有点胶处理工艺的缺陷。
虽然以一较佳实施倒对本发明进行了以上的说明,然其并非用以限定本发明,任何本专业技术人员在不脱离本发明的精神和范围的情况下,当可作各种更动与润饰,因此本发明的保护范围应同时参酌后附的权利要求来界定。

Claims (2)

1.一种倒装片组装的底层填充封胶处理工艺,主要步骤为:
a)先将晶片的凸块使用助焊剂加以热处理后焊于基板上;
b)将焊妥的晶片及基板置于载板内的槽孔下方,使其基板的顶缘抵住槽孔的底缘,而基板上的晶片则位于槽孔内,之后,以上耐热胶片贴于载板顶面,完全覆盖住其槽孔,其上耐热胶片的底缘贴于晶片的顶缘,且其灌胶孔恰位于浇道的正上方、其抽气孔恰位于抽气道正上方;同时以下耐热胶片覆贴于基板底面与载板底面,将基板完全包覆于载板下方,使由槽孔形成的外围、基板顶面为底、上耐热胶片底面为顶形成一包覆空间;
c)以灌胶注射器对准上耐热胶片的灌胶孔,同时以抽取器对准上耐热胶片的抽气孔,将底层填充胶灌入包覆空间并抽出包覆空间内的空气;
热硬化处理后,撕去上耐热胶片及下耐热胶片,使完成底层充填胶的对胶作业,并依载板上的定位孔予以裁切成适当的单一模块。
2.一种用于权利要求1中的倒装片组装的底层填充封胶处理工艺的装置,其使用一载板、一上耐热胶片、一下耐热胶片来包覆一己完成与晶片接合的基板,形成一包覆空间,并在其包覆空间内一端灌入底层填充胶,同时一端抽出其包覆空间内的空气,其中:
载板,为一较基板为宽的硬板,并于其中央开设有一槽孔,该槽孔的宽度与长度均略小于基板,但较宽于基板上的晶片宽度,在其槽孔的窄边中心分别设有一向外延伸出的浇道与抽气道,且载板上依需要设有定位孔;
上耐热胶片,为一具粘性的高耐热片,剪裁适当长度及宽度后,贴覆于载板顶面,将槽孔、浇道及抽气道整个覆盖住,并在对应浇道末端处开设一灌胶孔,及对应抽气道末端的位置设一抽气孔;
下耐热胶片,为一具粘性的高耐热片,可自载板底面进行包覆。
CNA02127651XA 2002-08-06 2002-08-06 倒装片组装的底层填充封胶处理及其装置 Pending CN1474441A (zh)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102153954A (zh) * 2011-04-11 2011-08-17 福州华映视讯有限公司 多对象的黏合方法及黏合机台
CN102364677A (zh) * 2011-10-09 2012-02-29 常熟市华海电子有限公司 一种倒装芯片封装结构
CN102610533A (zh) * 2011-01-20 2012-07-25 群成科技股份有限公司 注射封胶系统及其方法
CN101788359B (zh) * 2008-11-10 2014-04-30 伊顿公司 具有整体密封板的测压模块和测压模块的组装方法

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101788359B (zh) * 2008-11-10 2014-04-30 伊顿公司 具有整体密封板的测压模块和测压模块的组装方法
CN102610533A (zh) * 2011-01-20 2012-07-25 群成科技股份有限公司 注射封胶系统及其方法
CN102610533B (zh) * 2011-01-20 2014-08-27 群成科技股份有限公司 注射封胶系统及其方法
CN102153954A (zh) * 2011-04-11 2011-08-17 福州华映视讯有限公司 多对象的黏合方法及黏合机台
CN102153954B (zh) * 2011-04-11 2013-11-20 福州华映视讯有限公司 多对象的黏合方法及黏合机台
CN102364677A (zh) * 2011-10-09 2012-02-29 常熟市华海电子有限公司 一种倒装芯片封装结构

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