CN1471135A - Method for preparing deep submicron gate - Google Patents

Abstract

The method includes following procedures. (1) Complex film of silicon nitride and silicon dioxide is deposited on the substrate. The pattern of glue film is created by photoetch, making one edge locate at middle of source and drain of the part. The exposed part of silicon dioxide is etched so as to form lateral erosion. (2) Evaporating metal and removing metal on the glue by peeling off technique. (3) Window graph with linewidth in deep submicro is formed by using the plasma to etch the silicon nitride gap between metal edge and silicon dioxide since speed of etching silicon dioxide is lower than the speed of etching silicon nitride in this condition. (4) A grid window graph is formed by etching on the window in deep submicro. (5) Evaporating the grid metal. (6) The grid is formed. Based on need, silicon nitride under the grid possible to be reserved or removed.

Description

The method for preparing deep submicron gate

Technical field

The invention belongs to technical field of semiconductors, be meant a kind of method for preparing deep submicron gate especially.

Background technology

The preparation of deep submicron gate is a key technology of making microwave and ultrahigh speed monolithic integrated circuit.The time shortening that it can make the electronics in High Electron Mobility Transistor (HEMT) or metal-semiconductor field effect transistor (MESFET) device get over raceway groove, drain junctions electric capacity reduces, thereby improves the frequency characteristic of device and monolithic integrated circuit.

Be generally the acquisition deep submicron gate, adopt the method for electron beam exposure to prepare.And because electron beam exposure efficiency is very low, especially for the exposure of large scale slice, thin piece, its production efficiency is more apparent serious.And electron beam exposure apparatus costs an arm and a leg, and causes production cost very high.

Summary of the invention

The objective of the invention is to, a kind of method for preparing deep submicron gate is provided, it uses integrated circuit common apparatus and technology, the deep submicron gate of preparation HEMT or MESFET, and the frequency characteristic of raising device and monolithic integrated circuit is enhanced productivity, and reduces cost.

A kind of method for preparing deep submicron gate of the present invention is characterized in that, comprises the steps:

1) deposit silicon nitride and silicon dioxide composite membrane on substrate; Photoetching generates the glued membrane figure, leaks middle on one side make it be positioned at device source; The expose portion of corrode silicon dioxide also makes the formation lateral erosion;

2) evaporated metal; By stripping technology, remove the metal on the glue;

3) using plasma etching, utilize the masking action and the silicon dioxide etch rate principle slower of metal pair plasma etching than silicon nitride etch speed, etch silicon nitride in the slit that borders on silicon dioxide on the metal edges edge forms the graph window with deep-submicron live width yardstick;

4) adopt photoetching process, alignment forms the up-small and down-big grid window glue pattern of a broad on the window with deep-submicron live width yardstick between leaking in above-mentioned device source;

5) behind the grid groove corrosion, evaporation grid metal;

6) peel off the back and form grid, also can be as required, keep or remove silicon nitride below the grid.

Wherein substrate is compound semiconductor materials such as GaAs, indium phosphide or gallium nitride.

Description of drawings

For further specifying technology contents of the present invention, below in conjunction with drawings and Examples the present invention is done a detailed description, wherein:

Fig. 1 is a flow chart of the present invention.

Embodiment

See also shown in Figure 1ly, it is as follows to adopt this programme to form deep submicron gate lines device technology process: shown in Fig. 1 (1), at first go up at substrate (for example GaAs (GaAs), indium phosphide (InP) epitaxial wafer or ion inject sheet) and form isolated island 1; Then, shown in Fig. 1 (2), the photolithographic source leakage graphic, evaporation is peeled off and alloy forms source leakage graphic 2.

Deposit silicon nitride (SiN) and silicon dioxide (SiO ₂) layer 3, shown in Fig. 1 (3).Resist coating also exposes, develops, and plasma goes processing such as primer, obtains the glue pattern 4 shown in Fig. 1 (4), one side make the centre that just is positioned at the device source leakage of this figure.

Behind the post bake, erode the SiO of deposit ₂Layer and part Si N layer are shown in Fig. 1 (5).

The thin metal of vertical evaporation soaks with acetone then, peels off and removes photoresist and the metal above it, shown in Fig. 1 (6).

Slice, thin piece inserted carry out etching in the plasma etching machine, utilize the masking action of metal pair plasma etching and SiN SiO ₂Higher etch rate ratio is at metal and SiO ₂Etch the window of a deep-submicron among the SiN of boundary, as Fig. 1 (7).

Then, wideer grid window of alignment on the window of the deep-submicron that is positioned at the centre that device source leaks is shown in Fig. 1 (8).

Below identical with common process, promptly evaporation grid metal behind corrosion grid groove is peeled off the grid metal that the back forms device with acetone, shown in Fig. 1 (9).

In order to reduce the electric capacity that the grid metal causes because of SiN below the both wings, remove all or part of SiN below the grid metal both wings with plasma etching, as Fig. 1 (10).

Be developed into GaAs HEMT device and circuit that grid window live width is the 0.15-0.2 micron in this way, verified that this method is feasible.Conventional long its mutual conductance of GaAs HEMT of 1 micron grid of making and adopts long its mutual conductance of GaAs HEMT of 0.15 micron grid of this invention formation can reach 530mS/mm generally about 300mS/mm.

As corrosion SiO ₂The degree of depth more shallow (tens nanometers), under the situation of the thin metal also very thin (only tens nanometers) of vertical evaporation, the grid window live width of acquisition also can be too narrow to tens nanometer.Realize best way of the present invention

The formation technology of the deep submicron gate lines described in the present invention is: at first finish deposit SiN and SiO on GaAs (or InP) the HEMT epitaxial substrate that leaks metal formation technology in device isolation and source ₂, shown in Fig. 1 (3), its thickness is respectively 1500 , 1000 , and using plasma chemical gas-phase deposition enhanced (PECVD) generates this multilayer film at 280-300 ℃.

Be coated with positive photoresist (for example S9912) then and carry out rotine exposure, development, plasma goes processing such as primer, obtains the glue pattern as Fig. 1 (4) shown in, one side this figure just in alignment with the centre position of device source leakage or near.

Behind the post bake, fall the SiO of deposit with wet etching ₂Layer is as Fig. 1 (5).Corrosive liquid is the dilute aqueous solution that contains HF.

The thin metal of vertical evaporation is an aluminium, and thickness is 500-600 .Soak with acetone then, peel off and remove photoresist and the metal above it, as Fig. 1 (6).

Slice, thin piece inserted utilize carbon tetrafluoride (CF in the plasma etching machine ₄) wait gas to carry out etching SiN, because the masking action of metal pair plasma etching and SiN are to SiO ₂Higher etch rate ratio is at metal and SiO ₂Etch the window of a deep-submicron and even nanometer among the SiN of boundary, as Fig. 1 (7).

Then, gluing, photoetching, development, be positioned at centre that device source leaks or near the window of deep-submicron above alignment generate a wideer grid window, as Fig. 1 (8).

Below identical with common process, promptly evaporation grid metal behind corrosion grid groove is peeled off the grid metal that the back forms device with acetone, as Fig. 1 (9).

In order to reduce the grid metal, use SF because of the electric capacity that SiN below the both wings causes ₆All or part of SiN below the plasma etching removal grid metal both wings is as Fig. 1 (10).

Claims (2)

1, a kind of method for preparing deep submicron gate is characterized in that, comprises the steps:

1) deposit silicon nitride and silicon dioxide composite membrane on substrate; Photoetching generates the glued membrane figure, leaks middle on one side make it be positioned at device source; The expose portion of corrode silicon dioxide also makes the formation lateral erosion;

2) evaporated metal; By stripping technology, remove the metal on the glue;

3) using plasma etching, utilize the masking action and the silicon dioxide etch rate principle slower of metal pair plasma etching than silicon nitride etch speed, etch silicon nitride in the slit that borders on silicon dioxide on the metal edges edge forms the graph window with deep-submicron live width yardstick;

4) adopt photoetching process, alignment forms the up-small and down-big grid window glue pattern of a broad on the window with deep-submicron live width yardstick between leaking in above-mentioned device source;

5) behind the grid groove corrosion, evaporation grid metal;

6) peel off the back and form grid, also can be as required, keep or remove silicon nitride below the grid.

2, the method for preparing deep submicron gate according to claim 1 is characterized in that, wherein substrate is compound semiconductor materials such as GaAs, indium phosphide or gallium nitride.

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