CN1420693A - Method for controlling multichannel, and circuit for carrying out same - Google Patents

Abstract

A realization circuit of matching control for multichannel phase modulated by radio communication baseband includes digital modulation module, multichannel analog processing module and adaptive phase matching control module. Its method includes detecting the phase error of phase delay or leading between each adaptive phase matching channel and reference channel using error detection circuit and outputting pulse signal correspondingly, converting the increase or decrease of each pulse signal duty ratio into the increase or decrease of voltage output capacity using phase error accumulator, converting the voltage capacity into delay control logic signal of matching channel of relevant adaptive phase using logic control circuit of phase error, sending the delay control logic signal to the filter of relevant adaptive phase matching channel in multichannel analog processing module to realize the multichannel adaptive phase regulation through changing the delay of relevant channel.

Description

The multichannel phase match control method of wireless communication baseband modulation and realization circuit

Invention field

The present invention relates to a kind of wireless communication baseband modulation technique, particularly a kind of control method and realization circuit that adopts adaptive technique multichannel baseband modulation in the radio communication to be carried out fine phase control, its circuit design then is particularly suitable for being made into integrated circuit (IC) chip.

Technical background

In existing wireless communication baseband modulating system, the phase matched between multichannel is that the manufacturing process by integrated circuit on the wireless communication baseband modulation chip guarantees.Though integrated circuit has the better matching property energy to device closely, the interchannel coupling for being formed by a plurality of circuit modules then is difficult to guarantee its matching precision.

Particularly be extensive use of phase modulation technique in the Modern wireless communication, when the phase place of interchannel signal not simultaneously, signal phase deviation can occur or noise margin is reduced in decode procedure, the corresponding error rate that has improved system and cause communication speed to reduce, therefore each channel signal phase matched precision of control is crucial in baseband modulation.

Illustrate a kind of principle structure of channel wireless radio multi communication baseband modulation integrated circuit (IC) chip among Fig. 1.Mainly comprise digital modulation module (DIGITAL MODULATION) 11, gain adjustment (GAINADJUSTMENT) module 12, simulation process module (ANALOG PROCESS) 13 and auxiliary circuit module (AUXILIARY CIRCUIT) 14.Need to prove: the channel wireless radio multi communication baseband modulation integrated circuit (IC) chip that tradition is used does not generally have designing gain adjusting module 12, is technical scheme of the present invention for convenience of description and a kind of up-to-date circuit structure that exemplifies.

Gain regulation module 12 wherein is provided with a plurality of treatment channel (as Q), is used for multichannel gain error control (GAIN ERROR CONTROL), realizes the adjustment of multichannel gain-adaptive coupling.Selecting passage such as I passage in the gain regulation module 12 is the benchmark passage.

Simulation process module 13 wherein also correspondence is provided with a plurality of treatment channel (as Q), and each treatment channel is by digital to analog converter (DAC) 131 (as the 12-14 bit), filter (FILTER) 132 and analog line driver (DRIVER) 133 formation that is linked in sequence.

Input data (DATA INPUT) are finished digital modulation after entering the digital modulation module 11 of chip internal, mode with parallel (12～14bits position) multichannel (Q) data-signal sends gain regulation module 12 to, parallel (as 12～14 bits) of the synchronous circuit output in the gain regulation module 12, multichannel (Q) data-signal send simulation process module 13, in simulation process module 13, finish digital-to-analogue conversion respectively by a plurality of (Q) simulation process passage of correspondence, filtering and power drive, export in the mode of multichannel (Q) analog signal then, the multichannel OUTPUT I of output, ..., the OUTPUT Q signal is delivered to the back level processor.

The logic input terminal of this chip (LOGIC INPUT) is mainly used in to be controlled the various functions of chip, and auxiliary circuit module 14 is mainly finished functions such as voltage reference.

According to schematic structure as can be seen the main feature of this multichannel integrated chip circuit baseband modulation be:

(1). the modulation to the data input signal is finished with digital form, and for the radio communication in modern times, the digital baseband modulation has advantages such as precision height, response speed is fast, antijamming capability is strong;

(2). do not proofread and correct for the unmatched situation of each interchannel phase place that partly produces by simulation process, just with the integrated circuit fabrication process consistency preferably characteristics with the ERROR CONTROL of Q interchannel phase place in certain scope;

(3). because the integrated circuit fabrication process error is a random distribution, cause chip performance to be offset within the specific limits, make the consistency of each chip parameter relatively poor;

(4). if adopt laser-adjusting and melt aluminium, melt bearing calibration such as polysilicon silk, need chip be tested, and test process needs by precision instrument, thereby increased the difficulty and the cost of chip testing;

(5). laser-adjusting has only large-scale semiconductor company just to have the ability to do, and is not suitable for general manufacturer and adopts;

(6) even. calibrated precision, but circuit chip still may produce skew after long-time the use, cause the chip electric property to reduce.

In sum, the multichannel phase of the radio communication quadrature modulation Base-Band Processing integrated chip circuit of obvious structure shown in Figure 1 coupling guarantees that technology is not fill part, and the utmost point has improved necessity.

Summary of the invention

The objective of the invention is to design in a kind of wireless communication baseband modulation between multichannel the match control method of phase place and realize circuit, be suitable in the high frequency baseband modulation technology of wireless communication system, using, especially in high performance wireless communication system, use, use in the chip design as GPRS (GPRS) pattern of GSM, guarantee interchannel phase error adjustment precision, error can not occur adjusting because of service time is long.

The technical scheme that realizes the object of the invention is such: a kind of multichannel phase match control circuit of wireless communication baseband modulation, comprise importing the digital modulation module that data are carried out digital modulation and exported the parallel multi-channel data, with parallel multi-channel data subchannel is carried out digital-to-analogue conversion, filtering and power drive and exports the multichannel analog processing module of multi-channel analog signal, it is characterized in that:

Also include multi-channel adaptive phase matched control module and digital sine wave generator; Multi-channel adaptive phase matched control module is linked in sequence by phase error detection circuit, phase error summation circuit and phase error logic control circuit and constitutes; The phase error detection circuit subchannel is connected with the power driving circuit of multichannel analog processing module, and phase error logic control circuit subchannel is connected with the filter of multichannel analog processing module; Digital sine wave generator connects described digital modulation module.

Described phase error detection circuit comprises the drift bucking circuit and the XOR gate of first voltage comparator, second voltage comparator, voltage comparator; An input of first, second voltage comparator connects reference power supply, another input of first, second voltage comparator connects the simulation of multichannel analog processing module benchmark passage respectively and exports the simulation output that reaches arbitrary other passages except that the benchmark passage, the output of first, second voltage comparator connects two inputs of XOR gate respectively, and the drift bucking circuit of voltage comparator connects another input port of first, second voltage comparator.

Described phase error summation circuit is the charge pump of the switching capacity pattern that connected to form by operational amplifier, reference current source, electronic control switch, electric capacity and switching capacity equivalent resistance network.

Described phase error summation circuit is the charge pump that utilizes recursive technique to realize that is connected to form by operational amplifier, reference current source, electronic control switch and electric capacity.

Described phase error Logic control module is linked in sequence by resitstance voltage divider, voltage comparator matrix, combinational logic module and latch and constitutes.

Also include the multichannel gain regulation module, subchannel is connected between described digital modulation module and the multichannel analog processing module.

Described digital modulation module, multichannel gain regulation module, multichannel analog processing module, multi-channel adaptive phase matched control module and digital sine wave generator are produced on the integrated circuit (IC) chip.

The technical scheme that realizes the object of the invention still is such: a kind of multichannel phase match control method of radio communication base band modulation circuit is characterized in that comprising following treatment step:

A. circuit powers on and enters initial phase;

B. the digitized sine wave signal is sent into digital modulation module and carry out digital modulation, and send the multichannel analog processing module to the mode correspondence of parallel multi-channel data, subchannel, order are carried out digital-to-analogue conversion, filtering and power drive, the sinusoidal wave analog signal of output multichannel;

C. selecting a passage in the multichannel is the benchmark passage, other passages are self adaptation phase matched passage, the sinusoidal wave analog signal of benchmark passage output and the sinusoidal wave analog signal of other self adaptation phase matched passages output are sent into multi-channel adaptive phase matched control module, detect each self adaptation phase matched passage and interchannel phase lag of benchmark or leading phase error and corresponding output pulse signal by phase error detection circuit, by phase error accumulator with the increase of each pulse signal duty ratio or reduce to convert the increase of voltage output variable to or reduce and voltage is converted to the delay logic control signal of corresponding self adaptation phase matched passage by the phase error logic control circuit;

D. the delay logic control signal is given the filter of the corresponding self adaptation phase matched of multichannel analog processing module passage, change the delay of corresponding self adaptation phase matched passage, make signal in this self adaptation phase matched passage Phase advance or after move, realize corresponding self adaptation phase matched channel phases and benchmark channel phases the coupling.

E. finish initial phase, the delay logic control signal of each passage of locking phase error logic control circuit output places off position with multi-channel adaptive phase matched control module.

The circuit power-up initializing stage of described steps A further comprises:

A1. with in the multichannel analog processing module except that the benchmark passage delay logic control signal of each self adaptation phase matched passage median filter be changed to default value;

A2. the data input with digital modulation module switches to the sinusoidal wave binary data input that is produced by circuit internal digital sine-wave generator.

Among the described step B, comprise that also sending the first correspondence of the parallel multi-channel data of digital modulation module output to the multichannel gain regulation module carries out self adaptation phase matched passage and the adjustment of the interchannel gain coupling of benchmark, will send the multichannel analog processing module to through the adjusted parallel multi-channel data correspondence of gain coupling again.

Among the described step C, the phase error that detects two signals further comprises following treatment step:

C1. by the drift bucking circuit of phase error detection circuit by voltage comparator and comparator, two sinusoidal wave analog quadrature modulation signals with benchmark passage and a self adaptation phase matched passage output, common-mode voltage during respectively with channel modulation signal processing separately is that benchmark compares, and the common-mode voltage that changes into so that modulation signal is handled separately is the two ways of digital signals of zero crossing;

C2. by XOR gate two ways of digital signals is carried out logical operation, obtain the phase error digit pulse that reflection two channel phases are leading or lag behind;

C3. be 90 when spending at the signal phase difference of two passages, the phase error digit pulse duty ratio of XOR gate output is 1: 1, and described output pulse is no unnecessary phase place in one-period;

C4. depart from 90 when spending at the signal phase difference of two passages, the phase error digit pulse duty ratio of XOR gate output increases or reduces.

Described phase error detection is a closed loop, and error that the phase error of detection is produced by the single frequency sinusoidal ripple signal in an above cycle on average obtains by asking after adding up again.

Among the described step C phase error that detects being carried out phase error adds up, be by electronic switch control charge pump, by phase-error pulse to electric capacity carry out N time the charging and discharge process in average effect, when the charge pump current size is linearly proportional with electric capacity, the accumulation result of phase error is linear, when charge pump current size and electric capacity do not have linear scale and concerns, utilize iterative algorithm to carry out phase error and add up.

Also comprise an iteration count is arranged to the N digit counter; the every adjustment of described self adaptation phase matched passage is once then once subtracted 1 operation to the N digit counter; send (RESET) signal that resets simultaneously described electric capacity is reset to common mode reference voltage (VCOM), when N equals zero, finish.

The delay logic control signal that among the described step C voltage is converted to corresponding self adaptation phase matched passage further comprises:

C5. resistance string is reference with common mode reference voltage (VCOM), the upper limit reference voltage (VCOM+VREF) of comparator matrix and the lower limit reference voltage (VCOM-VREF) of comparator matrix are carried out dividing potential drop, generate the benchmark voltage of each voltage comparator in the comparator matrix;

C6. the voltage (VOUT) that each voltage comparator is exported the phase error summation circuit in the comparator matrix compares with corresponding benchmark voltage, the voltage (VOUT) of phase error summation circuit output surpasses the voltage comparator of benchmark voltage, and the output logic state turnover takes place;

C7. by the logical combination unit logic state of comparator matrix output is carried out encoding process, produce corresponding channel delay logic control signal;

C8. after initial phase finished, latch stores channel delay logic control signal was until the circuit power down.

The delayed control signal that among the described step C voltage is converted to corresponding self adaptation phase matched passage further comprises:

C9. by the upper voltage limit comparator upper limit reference voltage (VCOM+VREF) of comparator matrix and the voltage (VOUT) of phase error summation circuit output are carried out voltage ratio, the lower limit reference voltage (VCOM-VREF) of comparator matrix and the voltage (VOUT) of phase error summation circuit output are carried out voltage ratio by the lower voltage limit comparator;

C10. when the voltage (VOUT) of phase error summation circuit output is higher than the upper limit reference voltage (VCOM+VREF) of comparator matrix, the output logic state of upper voltage limit comparator overturns, by follow-up combinational logic module the phase error of accumulative total is done add operation, when the voltage (VOUT) of phase error summation circuit output is lower than the lower limit reference voltage (VCOM-VREF) of comparator matrix, the output logic state of lower voltage limit comparator overturns, by the phase error subtraction of follow-up combinational logic module, produce corresponding channel delay control signal to accumulative total;

C11. after initial phase finished, latch stores channel delay control signal was until the circuit power down.

Among the described step c10, also comprise and utilize the RESET value that the combinational logic module is carried out reset operation, when the RESET value is " 1 ", finish at phase error adjustment when prepass, beginning is adjusted at the phase error of next passage or is finished whole initialization adjustment processes.

The end initial phase of described step e comprises the data input that the data input of digital modulation module is switched to the receiving circuit outside from the sinusoidal wave binary data input of receiving circuit inside.

Described initial phase is adjusted required precision by a timer according to phase matched and is carried out length control.

The advantage of the inventive method is: increased self adaptation phase matched circuit in base band modulation circuit, can realize the coupling adjustment of multichannel phase automatically when power-up initializing, do not needed extra test and correction means; The adjustment of phase place can be carried out at integrated circuit, is suitable for different manufacturing process; The adjustment of phase place is adaptive, and the error of each integrated circuit all can be in the control corresponding scope; Carry out because of after being adjusted at circuit and powering on of phase place, control precision can not change along with the prolongation of service time.

The present invention provides a kind of multi-channel adaptive phase matched control circuit of being made up of phase error detection circuit, phase error summation circuit and phase error logic control circuit for wireless communication baseband modulation class circuit, can make up with digital modulator, multichannel gain regulation module, multichannel analog processing module and the digital sine wave generator that adds and timer, form radio communication base band modulation circuit, can finish the Adaptive matching control and adjustment of each interchannel phase error in the circuit.

The inventive method utilizes low frequency signal to carry out phase error detection in the power-up initializing stage, add up and logic control, normal modulation signal after initial phase finishes then can work in high-frequency region, therefore is suitable for using in the multichannel high frequency base band modulation circuit of radio communication; Simultaneously, the precision height of adjustment error can not occur adjusting along with the prolongation of time.Circuit of the present invention is adapted at high performance system, uses in the GPRS pattern integrated circuit (IC) design as GSM.

Description of drawings

Fig. 1 is the baseband modulation integrated circuit theory diagram of radio communication quadrature modulation;

Fig. 2 is the wireless communication baseband IC of modulating theory diagram that adopts the multi-channel adaptive phase matched;

Fig. 3 is the circuit structure theory diagram of phase error detection circuit among Fig. 2;

Fig. 4 is the circuit structure diagram of phase error detection circuit shown in Figure 3;

Fig. 5 is a phase error detection waveform schematic diagram, phase-detection waveform schematic diagram when comprising by the no phase error shown in Fig. 5 a, phase-detection waveform schematic diagram when lagging behind the I passage and the phase-detection waveform schematic diagram when being ahead of the I passage by the Q passage shown in Fig. 5 c by the Q passage shown in Fig. 5 b;

Fig. 6 is the phase accumulator circuit structural representation that utilizes the switching capacity pattern to realize among Fig. 2;

Fig. 7 is the phase accumulator circuit structural representation that utilizes recursive schema to realize among Fig. 2;

Fig. 8 is a phase error additive effect waveform schematic diagram, the phase-accumulated effect waveform schematic diagram when comprising the phase-accumulated effect waveform schematic diagram when lagging behind the I passage by the Q passage shown in Fig. 8 a and being ahead of the I passage by the Q passage shown in Fig. 8 b;

Fig. 9 is that the phase error logic control element is realized circuit structure diagram for first kind among Fig. 2;

Figure 10 is that the phase error logic control element is realized circuit structure diagram for second kind among Fig. 2.

Embodiment

For making purpose of the present invention, technical scheme and advantage clearer, below with reference to the accompanying drawing embodiment that develops simultaneously, the present invention is described in more detail.

Referring to Fig. 2, the radio communication quadrature modulation baseband processing circuitry that illustrates among the figure, adopted the automatic matching technique of self-adapting multi-channel phase place of the present invention, and can be made into integrated circuit (IC) chip, have the baseband processing chip that multichannel phase mates the radio communication quadrature modulation of calibration result automatically thereby form.

Same Fig. 1 of structure of (GAINADJUSTMENT) module 22, simulation process module (ANALOG PROCESS) 23 and auxiliary circuit module (AUXILIARY CIRCUIT) 26 is adjusted in the digital modulation module that is comprised (DIGITAL MODULATION) 21, gain.Gain regulation module 22 wherein is provided with a plurality of treatment channel (as Q), one of them passage that gain adjustment circuit 224 is not set is benchmark passage (as passage I), the benchmark passage is connected to form by pre-attenuator circuit 221 and delay circuit 222, each is connected to form other passages by pre-attenuator circuit 221 and gain adjustment circuit 224, among the figure 223 is synchronous circuits, is used for that multichannel binary system is adjusted data and carries out Synchronous Processing; Simulation process module 23 also is provided with a plurality of treatment channel (as Q), and each treatment channel is by digital to analog converter (DAC) 231 (as 12～14 bits), filter (FILTER) 232 and analog line driver (DRIVER) 233 formation that is linked in sequence.

The present invention has increased self adaptation phase matched control module 24, timer 27 and digital sine wave generator 25 on the basis of above-mentioned basic structure.

The data-signal (circuit powers on when entering initial phase) of outer input data DATA INPUT signal (initial phase finishes the back) or 25 outputs of internal digital sine-wave generator, enter the digital modulator 21 of circuit inside, finish digital modulation, after carrying out the control of multichannel gain error coupling in the mode of parallel multi-channel data through gain regulation module 22, deliver to simulation process module 23, after finishing digital-to-analogue conversion, filtering and power drive, with multichannel analog output signal OUTPUT I ..., the mode of OUTPUT Q gives the back level processor.The logic input (LOGIC INPUT) of circuit is controlled the various functions of circuit, and auxiliary circuit 26 is finished functions such as voltage reference.

Self-adapting multi-channel phase matched control module 24 is by phase error (leading or lag behind) testing circuit 241, phase error summation circuit 242 and phase error logic control circuit 243 formation that is linked in sequence.Phase error (leading or hysteresis) testing circuit 241, detect the phase error of simulation process module 23 multichannel analog output signals (two sine wave signals), and converting phase-error pulse output to, detected phase-error pulse is delivered in the phase error summation circuit 242.Phase error summation circuit 242 is exported the increase of pulse duty factors or is reduced to export the voltage (amplitude) that increases or reduce according to phase error (leading or hysteresis) testing circuit 241.Output voltage passes to phase error logic control circuit 243, calculating with the benchmark passage is the phase parameter that other passages of reference need be adjusted, and then the delay of respective channel filter 232 in the control simulation process module 23, thereby the phase adaptation coupling of finishing between the inner multichannel of circuit is adjusted.

Digital sine wave generator 25 produces the sine wave signal of low frequency, use for phase-detection and adjustment in system initialisation phase, promptly when circuit powered on, the low-frequency sine signal that is produced by digital sine wave generator 25 sent digital modulation module 21 to carry out digital modulation, the adjustment of multichannel gain-adaptive, multichannel analog processing and multichannel phase Adaptive matching; After initial phase finished, self-adapting multi-channel phase matched control module 24 quit work, and only kept the phase place of each passage and adjusted parameter; 27 of timers are used to control self-adapting multi-channel phase matched control module 24 in the operating time of initial phase, and the operating time of initial phase is adjusted required precision according to phase place and carries out length control.

Referring to Fig. 3, be the theory diagram of phase error detection circuit 241 among Fig. 2, comprise that (OFFSETCANCELL) circuit 2413 and XOR circuit 2414 are offset in the drift of the first high-accuracy voltage comparator 2411, the second high-accuracy voltage comparator 2412, voltage comparator.The first high-accuracy voltage comparator 2411 is connected reference voltage VREF with an input of the second high-accuracy voltage comparator 2412, another input connects the analog output signal OUTPUT I of benchmark passage and the analog output signal OUTPUT Q of any one passage (merotype gating from Q passage obtains when utilizing) respectively, 2414 pairs two high accuracy voltage comparators 2411 of XOR circuit, the logic state signal of 2412 outputs carries out the XOR operation, and the drift of voltage comparator is offset (OFFSET CANCELL) circuit 2413 and is used for two high- accuracy voltage comparators 2411,2412 drift voltage suppresses.

In conjunction with referring to Fig. 4, corresponding with theory diagram shown in Figure 3.First, second high-accuracy voltage comparator (COM) has identical circuit structure, OUTPUT I and OUTPUT Q are the simulation output of the two-way orthogonal demodulation signal of benchmark passage and any one other passage, common-mode voltage when VCOM I and VCOM Q are the inner I of circuit, Q channel modulation signal processing, opAMP is an operational amplifier, INV is an inverter, XOR is an XOR gate, and SA and SB are electronic switch.

Two operational amplifier opAMP, capacitor C A and CB, electronic switch SA and SB constitute the drift voltage bucking circuit (OFFSET CANCELL) of comparator.OUTPUT I and OUTPUT Q are connected with the positive input terminal of two voltage comparators, VCOM I is connected with the negative input end of two voltage comparators with VCOM Q, and the negative input end with two operational amplifier opAMP is connected respectively, the positive input terminal of two operational amplifier opAMP is respectively by switch S B and OUTPUT I, OUTPUT Q connects, switch S A is with two input short circuits of operational amplifier opAMP, output with operational amplifier opAMP simultaneously is connected with capacitor C A, switch S B is connected the output of operational amplifier opAMP respectively with capacitor C B, simultaneously the drift voltage OFFSET of sampling is inserted an input port of two voltage comparators, make the drift voltage (OFFSET) of voltage comparator obtain the decay identical with the gain of operational amplifier.

Analog quadrature modulation signal OUTPUT I and OUTPUT Q are that reference voltage compares with VCOM I and VCOM Q respectively, and final to produce with common-mode voltage separately be the numeral output of zero crossing.These two numeral outputs are finished the phase-detection of OUTPUT I and two signals of OUTPUT Q in XOR gate XOR after inverter INV is anti-phase, the CHLOGIC logic level signal of output reflection inter-channel phase difference.

In conjunction with referring to Fig. 5, phase detection result when being no phase error shown in Fig. 5 a, when the output OUTPUT I of passage I (CH1) and Q (CHQ) and OUTPUT Q phase difference are 90 when spending, the output pulse of two voltage comparators (COM1 OUTPUT and COM2 OUTPUT) rising edge and trailing edge differed for 1/4 cycle separately, again after anti-phase and XOR is handled, pulse no unnecessary phase place in one-period of final output.

Shown in Fig. 5 b the phase detection result of Q passage when lagging behind the I passage.If simulation output OUTPUTQ lags behind unnecessary phase place of OUTPUT I, then after treatment, in one-period, phase difference can appear.Phase difference was represented with the time difference.When phase difference was Δ T, the performance in the one-period then was 4 * Δ T.

Shown in Fig. 5 c the phase detection result of Q passage when being ahead of the I passage.The output of simulation shown in figure OUTPUT Q is ahead of unnecessary phase place of OUTPUT I.

Can see that from the comparison of Fig. 5 b and Fig. 5 c the phase difference that OUTPUT Q lags behind OUTPUT I is opposite with the phase difference polarity that OUTPUT Q is ahead of OUTPUT I.Though the polarity of phase difference can obtain by definition, be relative phase difference owing to what in this circuit design, utilize, therefore the polarity to single phase difference can not add definition.

When OUTPUT Q is ahead of OUTPUT I, phase difference can appear equally, and the polarity of phase difference opposite when lagging behind OUTPUT I with OUTPUT Q.Therefore this phase error detection circuit 241 is the leading or hysteresis testing circuits of a phase place.

The characteristics of phase error detection circuit of the present invention 241 shown in Figure 4 can be described: the phase difference that can detect two orthogonal signalling by Fig. 5; Can discern the polarity of two orthogonal signalling phase differences.

The present invention has designed two kinds of circuit embodiments for phase error summation circuit 242, is respectively the phase error accumulator implementation of switching capacity pattern shown in Figure 6 and the phase error accumulator scheme of utilizing recursive schema to realize shown in Figure 7.All connecting buffer by charge pump forms.

Fig. 6 is the phase accumulator of a switching mode, op1, op2, op3, op4 are operational amplifier, op1 positive input termination reference voltage V REF, negative input end is connected with capacitor C 1, switch SW 1 and transistor M1 source electrode, and the op1 output is connected transistor M2 with transistor M1 grid, M3, M4, M5 constitutes benchmark (CASCODE) current source, M2, the grid of M3 is connected with bias voltage VBIASP, source electrode respectively with M4, the drain electrode of M5 connects.Transistor M4, the source electrode of M5 is connected with power vd D, and grid is connected with the drain electrode of M1, M2, and the drain electrode of M3 is connected with capacitor C 4 through switch SW 6, constitutes the charge circuit of capacitor C 4.

Switch SW 3 is connected capacitor C 4 with voltage VCOM, control when effective at RESET, and the voltage on the capacitor C 4 is flushed to VCOM (as VCOM1, VCOMQ) in advance.

Operational amplifier op4 is connected with resistance R 1, R2 and transistor M11, and output is the reference voltage of benchmark with the power supply.The positive input terminal of op4 is connected with VREF, and negative input end is connected with the source electrode of resistance R 1 and M11, and output is connected with the grid of M11, and the drain electrode of transistor M11 is connected with the positive input terminal of resistance R 2 and operational amplifier op3.

The output of operational amplifier op3 is connected with the grid of transistor M10, and negative input end is connected with source electrode, capacitor C 3 and the switch SW 5 of transistor M10, and SW5 connects SW4 and capacitor C 5.Transistor M6, M7, M8, M9 constitutes benchmark (CASCODE) current source, M6, the M7 grid is connected with bias voltage VBIASN, source electrode and M8, the drain electrode of M9 connects, M8, the grid of M9 is connected with the drain electrode of transistor M10, M7.

The drain electrode of transistor M6 is connected with capacitor C 4 through switch SW 7, constitutes the discharge loop of capacitor C 4.Operational amplifier op2 is buffering (BUFFER) level, the voltage on the output capacitance C4 (VOUT).

Capacitor C 2 constitutes switching capacity equivalent resistance network with switch SW 1, SW2, capacitor C 5 and switch SW 4, and SW5 constitutes another one switching capacity equivalent resistance network.

The setting of SW6, SW7 switching frequency is provided by the phase error detection result (CHLOGIC and CHLOGIC are non-) of prime, and its frequency is f, and the cycle is T, and when pulse duty factor changed, capacitor C 2, C5 were converted to voltage accumulation on capacitor C 4 with phase error.In one-period, twice charging and discharge process are arranged.

I in the following formula _ChThe expression charging current, I _DischThe expression discharging current, V _ChThe expression charging voltage, V _DischThe expression discharge voltage.

I _ch＝V _REF*ω _conC ₂

I _disch＝V _REF*ω _conC ₅ ${\mathrm{\&Delta;V}}_{\mathrm{ch}}=\frac{I_{\mathrm{ch}}*t_{\mathrm{CIII}.\mathrm{<figure-callout\; id="4"\; label="OGIC\; C"\; filenames="A0113482300251.png,A0113482300261.png"\; state="\{\{state\}\}">OGIC</figure-callout>}}}{C_{}}$ $={\frac{V_{\mathrm{REF}}*{\mathrm{\&omega;}}_{\mathrm{<figure-callout\; id="2"\; label="con\; C"\; filenames="A0113482300231.png"\; state="\{\{state\}\}">con</figure-callout>}}{C}_{}{}_2*\frac{T+\mathrm{\&Delta;T}}{4}}{C_4}}_{({\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="A0113482300231.png"\; state="\{\{state\}\}">C</figure-callout>}}_2=C_4)}$ $=\frac{V_{\mathrm{REF}}*{\mathrm{\&omega;}}_{\mathrm{con}}*(T+\mathrm{\&Delta;T})}{4}$ ${\mathrm{\&Delta;V}}_{\mathrm{disch}}=\frac{V_{\mathrm{REF}}*{\mathrm{\&omega;}}_{\mathrm{con}}*(T-\mathrm{\&Delta;T})}{4}$ ΔV＝ΔV _ch-ΔV _disch

＝V _REF*ω _con*ΔT/2

Can see from above derivation: the voltage on the capacitor C 4 is relevant with the time that discharges and recharges frequency and phase difference of reference voltage V REF, capacitor C 4.

Therefore, in subsequent treatment, reference level and VREF as comparator op2 input are linear, the then frequency that only discharges and recharges with switching capacity C4 of the conversion of phase error and the time correlation of phase error, thereby the phase error after can repeatedly being added up more accurately.

When this phase-accumulated method of employing, the phase place of Tiao Zhenging then can be utilized the pattern of open loop in adjusting range requires if desired, is that the phase error of two passages is mated adjustment; If be applied in during closed loop adjusts, coupling is adjusted will be more accurate, but need carry out careful design at the stability of control circuit and delay character etc.

Fig. 7 is a kind of phase error accumulator of utilizing recursive schema to realize.Op1 and op2 are two operational amplifiers, and the positive input terminal of op1 is connected with VREF, and negative input end is connected with transistor M1 source electrode and resistance R 1, and the output of op1 is connected with the grid of M1.Transistor M2, M3, M4, M5, M6, M7 primordial standard (CASCODE) current source, M8, M9, M10, M11 constitutes another one benchmark (CASCODE) current source.M2, M3, the grid of M7 is connected with bias voltage VBIASP, M4, M5, the grid of M6 is connected with the drain electrode of M1, M2, M4, M5, the source electrode of M6 is connected with power vd D.The grid of M8 and M10 is connected with bias voltage VBIASN, M9, and the grid of M11 is connected with the drain electrode of M3, M8, M9, the source electrode of M11 is connected with ground wire.

When the output pulse CHLOGIC of phase error detection was 1, SW2 imported capacitor C 1 with the electric current among M6, the M7 with the charging form, and SW1 imports power supply with the electric current among M10, the M11; When CHLOGIC was 0, SW2 imported ground wire with electric current among M6, the M7, and SW1 imports capacitor C 1 with electric current among M11, the M10 with discharge type.

Op2 is a voltage follower, makes buffer stage (BUFFER), and positive input terminal is connected with capacitor C 1, and negative input end is connected with output (VOUT).

SW3 is (RESET) control that resets of capacitor C 1.Voltage on capacitor C 1 raises or reduces, and after having caused the signed magnitude arithmetic(al) of a logic control, phase error once being adjusted, promptly capacitor C 1 is resetted.After capacitor C 1 resets, promptly adjust computing next time.

The number of times of adjusting (RESET signal) is provided by iteration count (ITERATION COUNTER).Its charging, discharge and phase difference (time difference) are provided by following formula. $I_{\mathrm{ch}}=I_{\mathrm{disch}}=\frac{{\mathrm{<figure-callout\; id="1"\; label="V\; REF\; R"\; filenames="A0113482300271.png"\; state="\{\{state\}\}">V</figure-callout>}}_{\mathrm{REF}}}{R_{}}$ ${\mathrm{\&Delta;V}}_{\mathrm{ch}}=\frac{I_{\mathrm{ch}}*\left(\frac{T+\mathrm{\&Delta;T}}{4}\right)}{{\mathrm{<figure-callout\; id="1"\; label="C"\; filenames="A0113482300271.png"\; state="\{\{state\}\}">C</figure-callout>}}_1}$ ${\mathrm{\&Delta;V}}_{\mathrm{disch}}=\frac{I_{\mathrm{disch}}*\left(\frac{T-\mathrm{\&Delta;T}}{4}\right)}{{\mathrm{<figure-callout\; id="1"\; label="C"\; filenames="A0113482300271.png"\; state="\{\{state\}\}">C</figure-callout>}}_1}$ ΔV＝(ΔV _ch-ΔV _disch)*2

Can see from above analysis, the accumulation method of this kind phase error, relevant with reference voltage V REF, resistance R 1, capacitor C 1 and phase error.Therefore be not suitable for doing the coupling adjustment of single,, be subjected to the influence of drift voltage OFFSET little, be applicable to and in closed-loop control, realize the adjustment of iteration phase error coupling because circuit is simple.

The additive effect of phase error when the additive effect of phase error and Q passage are ahead of the I passage when among Fig. 8 a, Fig. 8 b Q passage being shown respectively and lagging behind the I passage.As can be seen, when output pulse (CHLOGIC) duty ratio of phase error detection circuit increased, the voltage output (VOUT) of phase error summation circuit just increased; When the output pulse (CHLOGIC) of phase error detection circuit when duty ratio reduces, the voltage of phase error summation circuit output (VOUT) then reduces.

Owing to once charge and the net effect of discharge little, simultaneously, have reasons such as other noises, feasible net effect each time is also different, thereby occurs the shake phenomenons such as (JITTER) of jitter when utilizing the single phase error to adjust easily.Can utilize the effect that repeatedly adds up to adjust, can suppress this kind problem effectively.

The present invention has designed two kinds of implementations for phase error logic control circuit 243, is shown by Fig. 9, Figure 10 respectively.

Referring to Fig. 9, first kind of implementation.Producing circuit (being connected in series the resistor voltage divider circuit that constitutes by resistance R, 2R), voltage comparator matrix (COM ARRAY), combinational logic module (LOGICCOMBINATION) and latch (LATCH) by the differential levels comparative level connects and composes.VCOM is the common mode reference voltage, and VCOM+VREF is the upper limit reference voltage of voltage comparator matrix, and VCOM-VREF is the lower limit reference voltage of voltage comparator matrix.Form the benchmark level (being connected) of each voltage comparator in the voltage comparator matrix between the upper limit and the lower limit reference voltage with negative input end with the resistance string form.

VOUT is the output voltage that is positioned at the phase accumulator of this circuit prime, be connected with the positive input terminal of voltage comparator matrix, when VOUT voltage surpasses the benchmark level of certain voltage comparator in the voltage comparator matrix, correspondent voltage comparator occurrence logic state turnover.

The output logic state of comparator matrix enters the combinational logic module and carries out encoding process, produces corresponding channel phases match parameter, i.e. the channel delay logic control signal of respective channel simulation process module median filter.With the I passage is the benchmark passage, and when Q channel phases hysteresis I channel phases, VOUT raises, the upset of respective comparator takes place in the comparator matrix, logic combination circuit coding produces the phase matched parameter, makes the delay of Q passage reduce, thereby makes the Phase advance of Q passage; Otherwise when the leading I channel phases of Q channel phases, VOUT descends, and the upset of corresponding comparator takes place in the comparator matrix 2432, and the logic combination circuit coding produces the phase matched parameter, makes the delay of Q passage increase, thereby makes the Phase delay of Q passage.

Latch in the control circuit (LATCH), its function are after initialization finishes, and store each passage respective phase match parameter, till power down.

This method has adopted the voltage comparator matrix, once can produce the required phase matched parameter of certain passage, is suitable for the occasion of open loop control, also can use in closed loop.

Figure 10 is second kind of implementation.Connect to form by upper voltage limit comparator (COM), lower voltage limit comparator (COM), combinational logic module (LOGIC COMBINATION) and latch (LATCH).VCOM is the common mode reference voltage; VCOM+VREF is the upper limit reference voltage of voltage comparator matrix; be connected with the negative input end of upper voltage limit comparator, and VCOM-VREF is the lower limit reference voltage of voltage comparator matrix, is connected with the positive input terminal of lower voltage limit comparator.Connect with resistance R between three voltage references.VOUT is the output of phase-accumulated circuit, is connected with the positive and negative input of upper and lower limit voltage comparator respectively.

When VOUT was higher than upper voltage limit VCOM+VREF, addition (add) computing was done in the upset of upper voltage limit comparator in the combinational logic module; When VOUT is lower than lower voltage limit VCOM-VREF, the upset of lower voltage limit comparator, (subtract) computing subtracts in logic combination circuit.

With passage I is the benchmark passage, when Q channel phases hysteresis I channel phases, VOUT raises, and does add operation in logic combination circuit, the filter delay of passage Q reduces in the logic state control simulation process module of output, adjusts the precision of Q channel phases to regulation gradually.Vice versa, and the subtraction logic makes the filter delay of Q passage increase.

This phase error logic control circuit can carry out open loop with the signalling channel of reality and handle, and the mean value of a plurality of phase errors as the foundation of adjusting, can effectively be reduced the influence of shake.

This phase error logic control circuit can carry out closed-loop process with the signalling channel of reality, utilizes adder or subtracter that the phase error that adds up is progressively adjusted.When the combinational logic value after reset (RESET) is the median of control, can make plus and minus calculation in the combinational logic part; Combinational logic value after reset (RESET) is complete " 1 ", when the phase error of accumulative total is lower than set point, makes one time subtraction; Combinational logic value after reset (RESET) is complete " 0 ", when the phase error of accumulative total surpasses set point, does an add operation.

Latch in the control circuit (LATCH) circuit, its function are after initialization finishes, and store each passage respective phase match parameter, till power down.

After once adjustment is finished, adjust by iteration count (output RESET signal) control next time.Whenever carry out once voltage on the electric capacity in the phase error summation circuit (charge pump) is reset to the operation of VCOM, the numerical value in the iteration count subtracts 1, is to finish adjustment process at 0 o'clock until the numerical value of counter.

Owing to carry out the iteration adjustment, the precision of adjustment is relevant with number of iterations.

The step-length of iteration can be 1bit, also can be many bits.

The present invention is in phase error adds up, owing to used charge pump, as long as the phase place of two passages does not match, can detect, error accumulation and control corresponding by a plurality of cycles add up, adopt the method for multiple averaging or iteration, utilize the control of open loop and closed loop, phase error can be matched the precision that needs.

Claims (19)

1. the multichannel phase match control circuit of wireless communication baseband modulation, comprise importing the digital modulation module that data are carried out digital modulation and exported the parallel multi-channel data, with parallel multi-channel data subchannel is carried out digital-to-analogue conversion, filtering and power drive and exports the multichannel analog processing module of multi-channel analog signal, it is characterized in that:

Also include multi-channel adaptive phase matched control module and digital sine wave generator; Multi-channel adaptive phase matched control module is linked in sequence by phase error detection circuit, phase error summation circuit and phase error logic control circuit and constitutes; The phase error detection circuit subchannel is connected with the power driving circuit of multichannel analog processing module, and phase error logic control circuit subchannel is connected with the filter of multichannel analog processing module; Digital sine wave generator connects described digital modulation module.

2. the multichannel phase match control circuit of wireless communication baseband modulation according to claim 1, it is characterized in that: described phase error detection circuit comprises the drift bucking circuit and the XOR gate of first voltage comparator, second voltage comparator, voltage comparator; An input of first, second voltage comparator connects reference power supply, another input of first, second voltage comparator connects the simulation of multichannel analog processing module benchmark passage respectively and exports the simulation output that reaches arbitrary other passages except that the benchmark passage, the output of first, second voltage comparator connects two inputs of XOR gate respectively, and the drift bucking circuit of voltage comparator connects another input port of first, second voltage comparator.

3. the multichannel phase match control circuit of wireless communication baseband according to claim 1 modulation is characterized in that: described phase error summation circuit is the charge pump of the switching capacity pattern that connected to form by operational amplifier, reference current source, electronic control switch, electric capacity and switching capacity equivalent resistance network.

4. the multichannel phase match control circuit of wireless communication baseband modulation according to claim 1 is characterized in that: described phase error summation circuit is the charge pump that utilizes recursive technique to realize that is connected to form by operational amplifier, reference current source, electronic control switch and electric capacity.

5. the multichannel phase match control circuit of wireless communication baseband modulation according to claim 1, it is characterized in that: described phase error Logic control module is linked in sequence by resitstance voltage divider, voltage comparator matrix, combinational logic module and latch and constitutes.

6. the multichannel phase match control circuit of wireless communication baseband modulation according to claim 1, it is characterized in that: also include the multichannel gain regulation module, subchannel is connected between described digital modulation module and the multichannel analog processing module.

7. the multichannel phase match control circuit of wireless communication baseband modulation according to claim 6, it is characterized in that: described digital modulation module, multichannel gain regulation module, multichannel analog processing module, multi-channel adaptive phase matched control module and digital sine wave generator are produced on the integrated circuit (IC) chip.

8. the multichannel phase match control method of a radio communication base band modulation circuit is characterized in that comprising following treatment step:

A. circuit powers on and enters initial phase;

B. the digitized sine wave signal is sent into digital modulation module and carry out digital modulation, and send the multichannel analog processing module to the mode correspondence of parallel multi-channel data, subchannel, order are carried out digital-to-analogue conversion, filtering and power drive, the sinusoidal wave analog signal of output multichannel;

C. selecting a passage in the multichannel is the benchmark passage, other passages are self adaptation phase matched passage, the sinusoidal wave analog signal of benchmark passage output and the sinusoidal wave analog signal of other self adaptation phase matched passages output are sent into multi-channel adaptive phase matched control module, detect each self adaptation phase matched passage and interchannel phase lag of benchmark or leading phase error and corresponding output pulse signal by phase error detection circuit, by phase error accumulator with the increase of each pulse signal duty ratio or reduce to convert the increase of voltage output variable to or reduce and voltage is converted to the delay control logic signal of corresponding self adaptation phase matched passage by the phase error logic control circuit;

D. will postpone the control logic signal and give the filter of the corresponding self adaptation phase matched of multichannel analog processing module passage, change the delay of corresponding self adaptation phase matched passage, make signal in this self adaptation phase matched passage Phase advance or after move, realize corresponding self adaptation phase matched channel phases and benchmark channel phases the coupling.

E. finish initial phase, the delay control logic signal of each passage of locking phase error logic control circuit output places off position with multi-channel adaptive phase matched control module.

9. the multichannel phase match control method of a kind of wireless communication baseband modulation according to claim 8 is characterized in that the circuit power-up initializing stage of described steps A further comprises:

A1. with in the multichannel analog processing module except that the benchmark passage delay control logic signal of each self adaptation phase matched passage median filter be changed to default value;

A2. the data input with digital modulation module switches to the sinusoidal wave binary data input that is produced by circuit internal digital sine-wave generator.

10. the multichannel phase match control method of a kind of wireless communication baseband modulation according to claim 8 is characterized in that:

Among the described step B, comprise that also sending the first correspondence of the parallel multi-channel data of digital modulation module output to the multichannel gain regulation module carries out self adaptation phase matched passage and the adjustment of the interchannel gain coupling of benchmark, will send the multichannel analog processing module to through the adjusted parallel multi-channel data correspondence of gain coupling again.

11. the multichannel phase match control method of a kind of wireless communication baseband modulation according to claim 8 is characterized in that among the described step C, the phase error that detects two signals further comprises following treatment step:

C1. by the drift bucking circuit of phase error detection circuit by voltage comparator and comparator, two sinusoidal wave analog quadrature modulation signals with benchmark passage and a self adaptation phase matched passage output, common-mode voltage during respectively with channel modulation signal processing separately is that benchmark compares, and the common-mode voltage that changes into so that modulation signal is handled separately is the two ways of digital signals of zero crossing;

C2. by XOR gate two ways of digital signals is carried out logical operation, obtain the phase error digit pulse that reflection two channel phases are leading or lag behind;

C3. be 90 when spending at the signal phase difference of two passages, the phase error digit pulse duty ratio of XOR gate output is 1: 1, and described output pulse is no unnecessary phase place in one-period;

C4. depart from 90 when spending at the signal phase difference of two passages, the phase error digit pulse duty ratio of XOR gate output increases or reduces.

12. the multichannel phase match control method of a kind of wireless communication baseband modulation according to claim 11, it is characterized in that: described phase error detection is a closed loop, and error that the phase error of detection is produced by the single frequency sinusoidal ripple signal in an above cycle on average obtains by asking after adding up again.

13. the multichannel phase match control method of a kind of wireless communication baseband modulation according to claim 8, it is characterized in that: among the described step C phase error that detects is carried out phase error and add up, be by electronic switch control charge pump, by phase-error pulse to electric capacity carry out N time the charging and discharge process in average effect, when the charge pump current size is linearly proportional with electric capacity, the accumulation result of phase error is linear, when charge pump current size and electric capacity do not have linear scale and concerns, utilize iterative algorithm to carry out phase error and add up.

14. the multichannel phase match control method of a kind of wireless communication baseband modulation according to claim 13; it is characterized in that: also comprise an iteration count is arranged to the N digit counter; the every adjustment of described self adaptation phase matched passage is once then once subtracted 1 operation to the N digit counter; send (RESET) signal that resets simultaneously described electric capacity is reset to common mode reference voltage (VCOM), when N equals zero, finish.

15. the multichannel phase match control method of a kind of wireless communication baseband modulation according to claim 8 is characterized in that the delay control logic signal that among the described step C voltage is converted to corresponding self adaptation phase matched passage further comprises:

C5. resistance string is reference with common mode reference voltage (VCOM), the upper limit reference voltage (VCOM+VREF) of comparator matrix and the lower limit reference voltage (VCOM-VREF) of comparator matrix are carried out dividing potential drop, generate the benchmark voltage of each voltage comparator in the comparator matrix;

C6. the voltage (VOUT) that each voltage comparator is exported the phase error summation circuit in the comparator matrix compares with corresponding benchmark voltage, the voltage (VOUT) of phase error summation circuit output surpasses the voltage comparator of benchmark voltage, and the output logic state turnover takes place;

C7. by the logical combination unit logic state of comparator matrix output is carried out encoding process, produce corresponding channel delay control logic signal;

C8. after initial phase finished, latch stores channel delay control logic signal was until the circuit power down.

16. the multichannel phase match control method of a kind of wireless communication baseband modulation according to claim 8 is characterized in that the delay control logic signal that among the described step C voltage is converted to corresponding self adaptation phase matched passage further comprises:

C9. by the upper voltage limit comparator upper limit reference voltage (VCOM+VREF) of comparator matrix and the voltage (VOUT) of phase error summation circuit output are carried out voltage ratio, the lower limit reference voltage (VCOM-VREF) of comparator matrix and the voltage (VOUT) of phase error summation circuit output are carried out voltage ratio by the lower voltage limit comparator;

C10. when the voltage (VOUT) of phase error summation circuit output is higher than the upper limit reference voltage (VCOM+VREF) of comparator matrix, the output logic state of upper voltage limit comparator overturns, by follow-up combinational logic module the phase error of accumulative total is done add operation, when the voltage (VOUT) of phase error summation circuit output is lower than the lower limit reference voltage (VCOM-VREF) of comparator matrix, the output logic state of lower voltage limit comparator overturns, by the phase error subtraction of follow-up combinational logic module, produce corresponding channel delay logic control signal to accumulative total;

C11. after initial phase finishes, by latch stores channel delay logic control signal until the circuit power down.

17. the multichannel phase match control method of a kind of wireless communication baseband modulation according to claim 16, it is characterized in that among the described step c10, also comprise and utilize the RESET value that the combinational logic module is carried out reset operation, when the RESET value is " 1 ", end is at when the phase error adjustment of prepass, and beginning is at the phase error adjustment of next passage or finish whole initialization adjustment processes.

18. the multichannel phase match control method of a kind of wireless communication baseband modulation according to claim 8 is characterized in that: the end initial phase of described step e comprises the data input that the data input of digital modulation module is switched to the receiving circuit outside from the sinusoidal wave binary data input of receiving circuit inside.

19. the multichannel phase match control method of a kind of wireless communication baseband modulation according to claim 8 is characterized in that: described initial phase is adjusted required precision by a timer according to phase matched and is carried out length control.

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