CN108008186B - Non-home intelligent terminal phase configuration device and method - Google Patents

Non-home intelligent terminal phase configuration device and method Download PDF

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Publication number
CN108008186B
CN108008186B CN201711296933.XA CN201711296933A CN108008186B CN 108008186 B CN108008186 B CN 108008186B CN 201711296933 A CN201711296933 A CN 201711296933A CN 108008186 B CN108008186 B CN 108008186B
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pin
dial switch
phase
pcn
pbn
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CN108008186A (en
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邓士伟
傅萌
苗青
耿树军
冯燕钧
何朝伟
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Jiangsu Zhizhen Energy Technology Co ltd
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    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R22/00Arrangements for measuring time integral of electric power or current, e.g. electricity meters
    • G01R22/06Arrangements for measuring time integral of electric power or current, e.g. electricity meters by electronic methods
    • G01R22/061Details of electronic electricity meters
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R11/00Electromechanical arrangements for measuring time integral of electric power or current, e.g. of consumption
    • G01R11/02Constructional details
    • G01R11/04Housings; Supporting racks; Arrangements of terminals

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  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
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  • Input From Keyboards Or The Like (AREA)

Abstract

The invention discloses a non-home intelligent terminal phase configuration device, which comprises a dial switch device, wherein a dial switch comprises a 12-bit dial switch BM1, a 12-bit dial switch BM2, a 12-bit dial switch BM3 and 5I 2C I/O expansion chips, the 12-bit dial switch BM1 comprises a PAn pin, the 12-bit dial switch BM2 comprises a PBn pin, the 12-bit dial switch BM3 comprises a PCn pin, wherein n=1, 2 …, the I2C I/O expansion chip comprises 8-bit I/O ports, and the PAn pin, the PBn pin and the PCn pin are respectively connected with the I/O ports of 5I 2C I/O expansion chips. The invention also discloses a non-home intelligent terminal phase configuration method. The non-home intelligent terminal phase configuration device adopts a dial switch mode to carry out phase configuration on the current of each channel, so that constructors can realize flexible configuration of each channel by hands or small screwdrivers, and can also configure single-phase power supply or three-phase power supply for residents. The non-home intelligent terminal is simple in configuration, does not need complex paper recording, improves accuracy and greatly improves construction efficiency.

Description

Non-home intelligent terminal phase configuration device and method
Technical Field
The invention belongs to the technical field of intelligent power grids and intelligent power consumption, and relates to a non-home intelligent terminal phase configuration device and method.
Background
According to the non-household identification technology, information such as the type, start-stop state, power consumption habit and the like of the actual electric appliances used by residents can be obtained only by installing a monitoring device at the main entrance of the resident power supply.
The existing residential building total power supply is 3-phase power supply, the residential power supply is mainly single-phase power supply, the power distribution of each cell is different, some cells of the power supply are distributed according to the house number sequence ABCABC … mode, and some cells are distributed according to the AABBCC … mode. For large-scale or power-compatibilized residential users, the power supply mode is 3-phase power supply.
When the non-home intelligent terminal identifies the power load, the voltage is required to be matched with the current, so that the active, reactive and other parameters can be calculated through the collection of the voltage and the current, and the analysis and the identification of the electric appliance can be carried out. The non-home intelligent terminal collects 3-phase voltage and 12-channel current, so that the voltage is required to be calibrated for each channel of current, and the current common processing modes include the following:
1, pre-configuring the embedded software in a certain mode, such as an ABCABC mode or an AABBCC mode, and manually recording the corresponding relation between each channel and the house number when the embedded software does not correspond to an actual wiring mode, and providing the corresponding relation between a central software input channel and the house number;
2, configuring parameters through central software, manually recording actual voltage phase when the parameters are installed, reporting the actual voltage phase to a center, and transmitting phase matching parameters to a terminal through the central software;
and 3, before the product leaves the factory, carrying out field investigation, carrying out the corresponding configuration of embedded software according to the actual situation, and forming different situations of different cell software in the mode, wherein the later-stage upgrading and maintenance difficulty is high.
The installers of the non-home intelligent terminals are mostly common electricians, so that the installers can manually record the installers on a construction site and report the installers to a center for configuration, and in practical application, the error rate is high, and the subsequent searching and changing difficulties and the cost are high.
Therefore, a non-home intelligent terminal phase configuration device is provided to solve the above problems.
Disclosure of Invention
The invention aims to provide a non-home intelligent terminal phase configuration device for solving the problems.
The invention realizes the above purpose through the following technical scheme:
the utility model provides a non-intelligent terminal looks configuration device that goes into home, includes dial switch device, dial switch device includes dial switch BM1, dial switch BM2, dial switch BM3 and L I2C I/O expansion chip, dial switch BM1 includes the PAn foot, dial switch BM2 includes the PBn foot, dial switch BM3 includes the PCn foot, wherein, n=1, 2 … M, I2C I/O expansion chip includes K I/O mouth, PAn foot, PBn foot and PCn foot include 3M pin, L I2C I/O expansion chip includes LK I/O mouth, wherein, LK is not less than 3M, 3M pins of dial switch BM1, dial switch BM2, dial switch BM3 are connected with 3M in the LK I/O mouth respectively.
Still further, the dial switch device comprises a dial switch BM1, a dial switch BM2, a dial switch BM3 and 5I 2C I/O expansion chips, the dial switch BM1 comprises a PAn pin, the dial switch BM2 comprises a PBn pin, the dial switch BM3 comprises a PCn pin, wherein n=1, 2 …, the I2C I/O expansion chip comprises 8I/O ports, 5I 2C I/O expansion chips comprise 40I/O ports, and 36 pins of the PAn pin, the PBn pin and the PCn pin are respectively connected with 36 of the 40I/O ports. The method is suitable for phase configuration of 12-channel current.
Still further, the I2C I/O expansion chip includes a chip U12, where the chip U12 includes an SCL end, an SDA end, and K I/O ports, where the SCL end and the SDA end are respectively connected to the i2c2_scl end and the i2c2_sda end, and the K I/O ports are respectively connected to +3.3v voltage ends through resistors.
Still further, the chip U12 further includes a VDD terminal, a VSS terminal, an A0 terminal, an A1 terminal, and an A2 terminal, where the VDD terminal is connected to a +3.3v voltage terminal, the VSS terminal is grounded, the A0 terminal is connected to a +3.3v voltage terminal, and the A1 terminal and the A2 terminal are grounded.
Still further, the chip U12 is a PCF8574TS chip.
Still further, the device also comprises a CPU, wherein the CPU comprises an I2C_SCL pin and an I2C_SDA pin, and the I2C2_SCL end and the I2C2_SDA end are respectively connected with the I2C_SCL pin and the I2C_SDA pin through a resistor R134 and a resistor R135.
Further, the CPU is an STM32F407IGT6 chip.
Further, the resistor R134 and the resistor R135 are both 0Ω resistors.
Further, K I/O ports are connected with a +3.3V voltage terminal through a discharge resistor.
Further, the exclusion is an exclusion of 10K.
The beneficial effects are that: the non-home intelligent terminal phase configuration device adopts a dial switch mode to carry out phase configuration on the current of each channel, a constructor can realize flexible configuration of each channel phase by hands or a small screwdriver, and meanwhile, the residential and civil power supply or the three-phase power supply can be configured.
The invention also discloses a non-home intelligent terminal phase configuration method, which adopts the non-home intelligent terminal phase configuration device, wherein the dial switch BM1, the dial switch BM2 and the dial switch BM3 respectively correspond to an A phase state, a B phase state and a C phase state, the dial switch BM1, the dial switch BM2 and the dial switch BM3 respectively have M bits, wherein M is a natural number, M is not less than 1 and not more than 24, and the M bit switches respectively correspond to 1-M channel current states, and the method comprises the following steps:
1) Periodically scanning the states of the PAn pin of the dial switch BM1, the PBn pin of the dial switch BM2 and the PCn pin of the dial switch BM3 by using a CPU;
2) When the PAn pin of the dial switch BM1, the PBn pin of the dial switch BM2 or the PCn pin of the dial switch BM3 are scanned to change, performing matching judgment bit by bit according to the positions corresponding to the PAn pin, the PBn pin and the PCn pin, wherein n=1, 2 … M; the matching judgment method comprises the following steps:
21 If PAn pin status is 1 and both PBn pin and PCn pin are 0, then the voltage phase representing n channel current is a phase, let n=n+1, go to step 27), otherwise go to step 22);
22 If the PBn pin state is 1 and both the PAn pin and the PCn pin are 0, then the voltage phase representing the n-channel current is B phase, let n=n+1, go to step 27), otherwise go to step 23);
23 If PCn pin status is 1 and PAn pin and PBn pin are both 0, then the voltage phase representing n-channel current is C phase, let n=n+1, go to step 27), otherwise go to step 24);
24 If PAn pin, PBn pin, and PCn pin states are all 0, then indicate n-channel is not enabled, let n=n+1, go to step 27), otherwise go to step 25);
25 If PAn, PBn and PCn pin states are all 1, and PA (n+1), PB (n+1) and PC (n+1) pin states are all 1, and PA (n+2), PB (n+2) and PC (n+2) pin states are all 1, and (n+2) <=m, then n to n+2 channels are three-phase power users and the voltage of n channel current is a phase, the voltage of n+1 channel current is B phase, the voltage of n+2 channel current is C phase, let n=n+3, go to step 27), otherwise go to step 26).
26 If not, configuring error, and exiting judgment;
27 Repeating steps 21) -26) until the voltages of all the channel currents are identified and judged.
The beneficial effects are that: the non-home intelligent terminal phase configuration method is simple in configuration by adopting the code switch configuration, does not need complex paper surface recording, greatly improves the accuracy and greatly improves the construction efficiency.
Drawings
FIG. 1 is a block diagram of a non-home intelligent terminal;
FIG. 2 is a diagram of a dial switch interface;
FIG. 3I 2C I/O expansion chip interface diagram;
fig. 4I 2C interface diagram of stm32f 407.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1, fig. 2, fig. 3 and fig. 4, the non-home intelligent terminal of the present invention includes a dial switch device, the dial switch device includes a dial switch BM1, a dial switch BM2, a dial switch BM3 and L I2C I/O expansion chips, the dial switch BM1 includes a PAn pin, the dial switch BM2 includes a PBn pin, the dial switch BM3 includes a PCn pin, wherein n=1, 2 … M, the I2C I/O expansion chip includes K I/O ports, the PAn pin, the PBn pin and the PCn pin include 3M pins, the L I2C I/O expansion chips include LK I/O ports, wherein LK is greater than or equal to 3M, and the 3M pins of the dial switch BM1, the dial switch BM2 and the dial switch BM3 are respectively connected with 3M of the LK I/O ports.
Specifically, the dial switch device comprises a dial switch BM1, a dial switch BM2, a dial switch BM3 and 5I 2C I/O expansion chips, the dial switch BM1 comprises a PAn pin, the dial switch BM2 comprises a PBn pin, the dial switch BM3 comprises a PCn pin, wherein n=1, 2 … 12, the I2C I/O expansion chips comprise 8I/O ports, the 5I 2C I/O expansion chips comprise 40I/O ports, and 36 pins of the PAn pin, the PBn pin and the PCn pin are respectively connected with 36 of the 40I/O ports. The method is suitable for phase configuration of 12-channel current.
Specifically, the I2C I/O expansion chip includes a chip U12, where the chip U12 includes an SCL end, an SDA end, and K I/O ports, where the SCL end and the SDA end are respectively connected to the i2c2_scl end and the i2c2_sda end, and the K I/O ports are respectively connected to the +3.3v voltage end through resistors. The chip U12 further comprises a VDD terminal, a VSS terminal, an A0 terminal, an A1 terminal and an A2 terminal, wherein the VDD terminal is connected with a +3.3V voltage terminal, the VSS terminal is grounded, the A0 terminal is connected with a +3.3V voltage terminal, and the A1 terminal and the A2 terminal are grounded. Wherein, the chip U12 is PCF8574TS chip. The K I/O ports are connected with a +3.3V voltage terminal through a discharge resistor. Preferably, the chip U12 includes 8I/O ports. The 8I/O ports are connected with +3.3V voltage terminals through a resistor. The exclusion was 10K.
The CPU comprises an I2C_SCL pin and an I2C_SDA pin, and the I2C2_SCL end and the I2C2_SDA end are respectively connected with the I2C_SCL pin and the I2C_SDA pin through a resistor R134 and a resistor R135. The CPU is an STM32F407IGT6 chip. The resistor R134 and the resistor R135 are both 0Ω resistors.
The non-home intelligent terminal phase configuration device adopts a dial switch mode to carry out phase configuration on the current of each channel, a constructor can realize flexible configuration of each channel phase by hands or a small screwdriver, and meanwhile, the residential and civil power supply or the three-phase power supply can be configured.
The invention also discloses a non-home intelligent terminal phase configuration method, which adopts the non-home intelligent terminal phase configuration device, wherein the dial switch BM1, the dial switch BM2 and the dial switch BM3 respectively correspond to an A phase state, a B phase state and a C phase state, the dial switch BM1, the dial switch BM2 and the dial switch BM3 respectively have M bits, wherein M is a natural number, M is not less than 1 and not more than 24, and the M bit switches respectively correspond to 1-M channel current states, and the method comprises the following steps:
1) Periodically scanning the states of the PAn pin of the dial switch BM1, the PBn pin of the dial switch BM2 and the PCn pin of the dial switch BM3 by using a CPU;
2) When the PAn pin of the dial switch BM1, the PBn pin of the dial switch BM2 or the PCn pin of the dial switch BM3 are scanned to change, performing matching judgment bit by bit according to the positions corresponding to the PAn pin, the PBn pin and the PCn pin, wherein n=1, 2 … M; the matching judgment method comprises the following steps:
21 If PAn pin status is 1 and both PBn pin and PCn pin are 0, then the voltage phase representing n channel current is a phase, let n=n+1, go to step 27), otherwise go to step 22);
22 If the PBn pin state is 1 and both the PAn pin and the PCn pin are 0, then the voltage phase representing the n-channel current is B phase, let n=n+1, go to step 27), otherwise go to step 23);
23 If PCn pin status is 1 and PAn pin and PBn pin are both 0, then the voltage phase representing n-channel current is C phase, let n=n+1, go to step 27), otherwise go to step 24);
24 If PAn pin, PBn pin, and PCn pin states are all 0, then indicate n-channel is not enabled, let n=n+1, go to step 27), otherwise go to step 25);
25 If PAn, PBn and PCn pin states are all 1, and PA (n+1), PB (n+1) and PC (n+1) pin states are all 1, and PA (n+2), PB (n+2) and PC (n+2) pin states are all 1, and (n+2) <=m, then n to n+2 channels are three-phase power users and the voltage of n channel current is a phase, the voltage of n+1 channel current is B phase, the voltage of n+2 channel current is C phase, let n=n+3, go to step 27), otherwise go to step 26).
26 If not, configuring error, and exiting judgment;
27 Repeating steps 21) -26) until the voltages of all the channel currents are identified and judged.
The non-home intelligent terminal phase configuration method is simple in configuration by adopting the code switch configuration, does not need complex paper surface recording, greatly improves the accuracy and greatly improves the construction efficiency.
Examples
The dial switch part of the invention adopts 3 Shenzhen high electron direct insertion, 12 bit dial switches and 5 NXP company I2C I/O expansion chips PCF8574TS, and 3 12 way dial switches respectively correspond to A phase power supply, B phase power supply and C phase power supply.
The phase selection of the user accessing the three-phase power is controlled by using a dial switch, as shown in fig. 2 and 3, in which, in the BM1 example, 13-24 pins of the dial switch BM1 are connected with GND, 1-8 pins are connected with P0-P7 pins of PCF8574TS of NXP company, and 9-12 pins of the dial switch BM1 are connected with P0-P3 pins of PCF8574TS of another chip in a parallel manner. Pin 1 of the PCF8574TS chip is suspended, wherein pin 1 is an INT pin, which represents an interactive LOW. Pin 2 connects i2C_SCL and connects with I2C_SCL of CPU after a0 Ω, pin 2 is SCL foot, represent serial clock line, pin 4 connects i2C_SDA and connects with I2C_SDA of CPU after a0 Ω, pin 4 is SDA foot, represent serial data line. Pin 5 is connected to a +3.3V power supply, and pin 5 is the VDD pin, representing supply voltage. Pin 6 in FIG. 3 is connected to +3.3V, and pins 7 and 9 are connected to ground. The pins 10, 11, 12, 14, 16, 17, 19 and 20 are directly connected with 1-8 pins of the dial switch BM1, wherein 8 pins are required to be connected with two 10K pull-up resistors, and the other ends of the resistors are connected with +3.3V. Pins 10, 11, 12, 14, 16, 17, 19 and 20 are P0, P1, P2, P3, P4, P5, P6 and P7 pins, respectively, wherein pins 10, 11, 12, 14, 16, 17, 19 and 20 are 8-bit remote I/O ports and are quasi-bidirectional I/O ports. Pin 15 is grounded, pin 15 is a VSS pin, representing a supply group. Pin 3, pin 8, pin 13 and pin 18 are suspended. When a user uses phase A electricity, only the switch corresponding to the user in the dial switch BM1 is closed, at the moment, one end of the switch connected with the chip PCF8574TS is changed from high level to low level, the change of the pin level of the chip PCF8574TS is transmitted to the CPU by the I2C bus, at the moment, the CPU can obtain the opening and closing states of each dial bit of BM1, and BM2 and BM3 are similar to BM 1.
Examples of the configuration voltages of the dip switch are shown in the following table:
furthermore, it should be understood that although the present disclosure describes embodiments, not every embodiment is provided with a separate embodiment, and that this description is provided for clarity only, and that the disclosure is not limited to the embodiments described in detail below, and that the embodiments described in the examples may be combined as appropriate to form other embodiments that will be apparent to those skilled in the art.

Claims (9)

1. The non-home intelligent terminal phase configuration device is characterized by comprising a dial switch device, wherein the dial switch device comprises a dial switch BM1, a dial switch BM2, a dial switch BM3 and L I2C I/O expansion chips, the dial switch BM1 comprises a PAn pin, the dial switch BM2 comprises a PBn pin, the dial switch BM3 comprises a PCn pin, n=1, 2 … M, the I2C I/O expansion chips comprise K I/O ports, the PAn pin, the PBn pin and the PCn pin comprise 3M pins, L I2C I/O expansion chips comprise LK I/O ports, wherein LK is more than or equal to 3M, and 3M pins of the dial switch BM1, the dial switch BM2 and the dial switch BM3 are respectively connected with 3M of the LK I/O ports;
the method for configuring the non-home intelligent terminal is adopted, the dial switch BM1, the dial switch BM2 and the dial switch BM3 respectively correspond to an A phase state, a B phase state and a C phase state, the dial switch BM1, the dial switch BM2 and the dial switch BM3 all have M bits, wherein M is a natural number, M is more than or equal to 1 and less than or equal to 24, and the M bit switches respectively correspond to 1-M channel current states, and the method comprises the following steps:
1) Periodically scanning the states of the PAn pin of the dial switch BM1, the PBn pin of the dial switch BM2 and the PCn pin of the dial switch BM3 by using a CPU;
2) When the PAn pin of the dial switch BM1, the PBn pin of the dial switch BM2 or the PCn pin of the dial switch BM3 are scanned to change, performing matching judgment bit by bit according to the positions corresponding to the PAn pin, the PBn pin and the PCn pin, wherein n=1, 2 … M; the matching judgment method comprises the following steps:
21 If PAn pin status is 1 and both PBn pin and PCn pin are 0, then the voltage phase representing n channel current is a phase, let n=n+1, go to step 27), otherwise go to step 22);
22 If the PBn pin state is 1 and both the PAn pin and the PCn pin are 0, then the voltage phase representing the n-channel current is B phase, let n=n+1, go to step 27), otherwise go to step 23);
23 If PCn pin status is 1 and PAn pin and PBn pin are both 0, then the voltage phase representing n-channel current is C phase, let n=n+1, go to step 27), otherwise go to step 24);
24 If PAn pin, PBn pin, and PCn pin states are all 0, then indicate n-channel is not enabled, let n=n+1, go to step 27), otherwise go to step 25);
25 If PAn, PBn and PCn are all 1, PA (n+1), PB (n+1) and PC (n+1) are all 1, PA (n+2), PB (n+2) and PC (n+2) are all 1, and (n+2) <=m, then n to n+2 channels are three-phase users and the voltage phase of n channel current is a phase, the voltage phase of n+1 channel current is B phase, the voltage phase of n+2 channel current is C phase, let n=n+3, go to step 27), otherwise go to step 26);
26 If not, configuring error, and exiting judgment;
27 Repeating steps 21) -26) until the voltages of all the channel currents are identified and judged.
2. The non-home intelligent terminal phase configuration device according to claim 1, wherein: the dial switch device comprises a dial switch BM1, a dial switch BM2, a dial switch BM3 and 5I 2C I/O expansion chips, wherein the dial switch BM1 comprises a PAn pin, the dial switch BM2 comprises a PBn pin, the dial switch BM3 comprises a PCn pin, n=1, 2 … 12, the I2C I/O expansion chips comprise 8I/O ports, 5I 2C I/O expansion chips comprise 40I/O ports, and 36 pins of the PAn pin, the PBn pin and the PCn pin are respectively connected with 36 of the 40I/O ports.
3. The non-home intelligent terminal phase configuration device according to claim 1, wherein: the I2C I/O expansion chip comprises a chip U12, wherein the chip U12 comprises an SCL end, an SDA end and K I/O ports, the SCL end and the SDA end are respectively connected with an I2C2_SCL end and an I2C2_SDA end, and the K I/O ports are respectively connected with a +3.3V voltage end through resistors.
4. The non-home intelligent terminal phase configuration device according to claim 3, wherein: the chip U12 further comprises a VDD end, a VSS end, an A0 end, an A1 end and an A2 end, wherein the VDD end is connected with a +3.3V voltage end, the VSS end is grounded, the A0 end is connected with a +3.3V voltage end, and the A1 end and the A2 end are grounded.
5. The non-home intelligent terminal phase configuration device according to claim 3, wherein: the chip U12 is a PCF8574TS chip.
6. The non-home intelligent terminal phase configuration device according to claim 3, wherein: the CPU comprises an I2C_SCL pin and an I2C_SDA pin, and the I2C2_SCL end and the I2C2_SDA end are respectively connected with the I2C_SCL pin and the I2C_SDA pin through a resistor R134 and a resistor R135.
7. The non-home intelligent terminal phase configuration device according to claim 6, wherein: the CPU is an STM32F407IGT6 chip.
8. The non-home intelligent terminal phase configuration device according to claim 6, wherein: the resistor R134 and the resistor R135 are 0 omega resistors.
9. The non-home intelligent terminal phase configuration device according to claim 3, wherein: k I/O ports are connected with +3.3V voltage terminals through a discharging resistor.
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