CN1392603A - Method for improving leakage current and cllapse voltage of shallow channel isolation area - Google Patents
Method for improving leakage current and cllapse voltage of shallow channel isolation area Download PDFInfo
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- CN1392603A CN1392603A CN 01118829 CN01118829A CN1392603A CN 1392603 A CN1392603 A CN 1392603A CN 01118829 CN01118829 CN 01118829 CN 01118829 A CN01118829 A CN 01118829A CN 1392603 A CN1392603 A CN 1392603A
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Abstract
A method for improving leakage current and breakdown voltage in shallow groove isolating zone is to take a cover layer and a padding oxide layer as etching cover to etch a groove on the substrate, and after a lining oxide layer is formed on the groove surface, a nitrided monox layer is formed on the lining oxide layer, and the groove is fully filled with isolating materials, the surplus isolating material is removed by the chemical-mechanical grinding, and subsequently, the above-mentioend etching cover is stripped to achieve the prevention of the remaining polycrystalline silicon frmo being left at depressions in the groove corners and lower the leakage current shallow groove isolating zone with the effects of reducing the leakage current and raising the breakdown voltage.
Description
The invention relates to a kind of shallow channel isolation area (shallow trench isolation; STI) manufacture method, particularly relevant for a kind of by improving the spatial obstacle of trench corner, avoid the residual of compound crystal silicon, with the leakage current (leakage current) that improves formed shallow channel isolation area and the method for breakdown voltage (breakdown voltage).
Consult Fig. 1, well-known, how traditional LOCOS isolation method is replaced by STI at the circuit production below 0.25 micron owing to beak effect and the smooth restriction of air spots.
The flow process of STI is as described below.At first, pad oxide of growing up on silicon substrate 10 (pad oxide) and silicon nitride layer (nitride) (not shown) after little shadow program definition isolated area, carry out pad oxide, silicon nitride layer and shallow trench etching in regular turn.Afterwards on the inwall of groove with hot oxygen method growth lining oxide layer (liner) 14, to eliminate the infringement that etching was caused.With in the chemical vapor deposition (CVD) oxide layer 16 filling grooves, as grinding stop layer (polish stop), stay a smooth surface more then with the surperficial material that has more of cmp (CMP) technology removal, and with silicon nitride layer.Again silicon nitride layer and pad oxide are removed at last, to carry out the making of subsequent element.Its major defect is:
When removing silicon nitride layer and pad oxide and other wet processed program, because the concentrated event of local stress, over etching is near the filling oxide layer 16 of isolation edge easily, and form the darker depressed area of a degree of depth 22, when making follow-up formation gate pole oxidation layer and gate compound crystal silicon layer, be deposited on the compound crystal silicon layer of recess 22,, thereby be easy to generate leakage current and can reduce the breakdown voltage of element because of the obstacle on the space is difficult for removing.
The purpose of this invention is to provide a kind of method of improving the leakage current and the breakdown voltage of shallow channel isolation area, can avoid compound crystal silicon to residue in the method for the recess of trench corner, it is to be etch mask with cover curtain layer and pad oxide, after in substrate, etching groove, surface at groove forms one deck lining oxide layer, on lining oxide layer, deposit one deck silicon oxynitride layer afterwards, in groove, fill up megohmite insulant again, and utilize cmp that unnecessary megohmite insulant is removed, again above-mentioned etch mask is divested, owing to divest cover curtain layer and the employed etching solution of pad oxide is little to the influence of silicon oxynitride layer, make the depression in corner of formed shallow channel isolation area not have the obstacle on the space so can slow down the over etching of the lining oxide layer of silicon oxynitride layer both sides and megohmite insulant, and avoided compound crystal silicon to residue in this, reach the purpose that reduces leakage current and improve breakdown voltage.
The object of the present invention is achieved like this: a kind of method of improving the leakage current and the breakdown voltage of shallow channel isolation area is characterized in that: comprise following step at least:
(1) in substrate, forms pad oxide and cover curtain layer in regular turn;
(2) with this pad oxide and cover curtain layer patterning, and be etch mask with pad oxide behind the patterning and cover curtain layer, this substrate of etching forms a groove in this substrate;
(3) form a lining oxide layer in the surface of this groove;
(4) on this lining oxide layer, form a silicon oxynitride layer;
(5) form an insulating barrier, insert in this groove;
(6) divest this cover curtain layer and pad oxide, to form channel separating zone.
The thickness of this lining oxide layer is 50-500 .The generation temperature of this lining oxide layer is 900-1150 ℃.The formation method of this silicon oxynitride layer is an electricity slurry enhanced chemical vapor deposition method.The process gas that deposits this silicon oxynitride layer is silane and oxynitrides.The thickness of this silicon oxynitride layer is 50-500 .The method that divests this cover curtain layer is a wet etching.This method that divests this pad oxide is a wet etching.This insulating barrier is the silica that utilizes the high-density electric slurry method to be deposited.
Major advantage of the present invention is to have the effect that reduces leakage current and improve breakdown voltage.
Describe in detail below in conjunction with preferred embodiment and accompanying drawing.
Fig. 1 is the generalized section of traditional shallow channel isolation area.
Fig. 2-Fig. 6 is the flow process generalized section of method of the present invention.
The present invention is the geometry by the depression that the corner produced that changes shallow channel isolation area, improves the problem of leakage current and breakdown voltage.Method of the present invention comprises the steps:
Consult Fig. 2, one substrate 100 is provided, it for example is silicon base, form pad oxide 102 and cover curtain layer 104 in regular turn on substrate 100 surfaces, the method that wherein forms pad oxide 102 can be thermal oxidation method or chemical vapour deposition technique, the material of cover curtain layer 104 for example is a silicon nitride, and its formation method is a chemical vapour deposition technique.Then, on cover curtain layer 104 surfaces, form one deck photoresist design layer 106, and by by micro-photographing process in wherein forming opening 108, the scope of this opening 108 is roughly the scope of element isolation zone.
Consult Fig. 3, utilize the photoresist design layer 106 of patterning to be used as etch mask, carry out anisotropic ground etch process, with the design transfer of photoresist design layer 106 to cover curtain layer 104 and pad oxide 102.Then, remove photoresist design layer 106 with suitable solution or dry-etching program again.
Next, be etch mask with cover curtain layer 104 and pad oxide 102, carry out the anisotropic etching processing procedure, substrate 100 is etched to a desired depth, to form the groove 110 that the degree of depth is about 3000-6000 .
Consult Fig. 4, form one deck lining oxide layer 114 in the surface of groove 110, required process temperatures is about about 900 ℃-1150 ℃, and the thickness of the lining oxide layer 114 that is generated is about about 50-500 .On lining oxide layer 114, form one deck silicon oxynitride layer 120 afterwards, this silicon oxynitride layer 120 also can extend to the top of cover curtain layer 104, its thickness is about about 50-500 , and its formation method is electricity slurry enhanced chemical vapor deposition method (nlasma enhanced CVD; PECVD), employed process gas is silane and oxynitrides, and wherein silane can be silicomethane, and oxynitrides can be nitrous oxide or nitric oxide.
Because the material of silicon oxynitride layer 120 is different from silica, therefore at follow-up removal cover curtain layer 104 and pad oxide 102, and during other wet processed program, can avoid lining oxide layer 114 and follow-up the insulating barrier 116 that forms be crossed etching, the anti-corner that terminates in produces the darker depression of the degree of depth.
Consult Fig. 5, then form a layer insulating 116, and insert in the groove 110 in cover curtain layer 104 tops.The material of aforesaid insulating barrier 116 can be silica, and its deposition process for example is high-density electric slurry (HDP) method.Carry out tempering program or Rapid Thermal processing procedure afterwards again, so that the quality densification of insulating barrier 116.
Consult Fig. 6, utilize chemical mechanical milling method that the insulating barrier 116 of cover curtain layer 104 tops and silicon oxynitride layer 120 are divested after, in regular turn cover curtain layer 104 and pad oxide 102 are divested again, to form channel separating zone 116a.
Wherein, the method that divests cover curtain layer 104 is a wet etching, for example be with hot phosphoric acid for etching solution soaks with its removal; The method that divests pad oxide 102 is a wet etching, and it for example is to be that etching solution soaks with hydrofluoric acid.
In addition, when divesting pad oxide 102, material is that the insulating barrier 116 and the lining oxide layer 114 of silica also can partly be divested, yet, because intervenient silicon oxynitride layer 120 is not subject to the influence of those etching solutions, therefore, can avoid the insulating barrier 116 of its both sides and lining oxide layer 114 by over etching, make that near the degree of depth of the depression the corner of formed shallow channel isolation area 116a is more shallow, and there is not spatial obstacle, so can not cause the spatial obstacle when divesting the electric material of follow-up formed grade, therefore more easily divest clean.Thereby improve the problem of leakage current and breakdown voltage.
In sum, the present invention provides following advantage at least:
1, the present invention is after flute surfaces forms lining oxide layer, and square thereon one-tenth one deck silicon oxynitride layer causes excessive etching to avoid etching solution to lining oxide layer.
2, method provided by the present invention is the spatial obstacle that is used for reducing recess, makes follow-uply when the conductive material that divests herein, is easier to divest clean, does not have the residual various defectives of deriving of conductive material.
3, method provided by the present invention can reduce leakage current, and improves the breakdown voltage of electric crystal, makes formed transistor element have the excellent electrical property quality.
More than be preferred embodiment of the present invention, anyly have the knack of this skill person, do without departing from the spirit and scope of the present invention and change and retouching, all belong within protection scope of the present invention.
Claims (9)
1, a kind of method of improving the leakage current and the breakdown voltage of shallow channel isolation area is characterized in that: comprise following step at least:
(1) in substrate, forms pad oxide and cover curtain layer in regular turn;
(2) with this pad oxide and cover curtain layer patterning, and be etch mask with pad oxide behind the patterning and cover curtain layer, this substrate of etching forms a groove in this substrate;
(3) form a lining oxide layer in the surface of this groove;
(4) on this lining oxide layer, form a silicon oxynitride layer;
(5) form an insulating barrier, insert in this groove;
(6) divest this cover curtain layer and pad oxide, to form channel separating zone.
2, the method for improving the leakage current and the breakdown voltage of shallow channel isolation area according to claim 1, it is characterized in that: the thickness of this lining oxide layer is 50-500 .
3, the method for improving the leakage current and the breakdown voltage of shallow channel isolation area according to claim 1, it is characterized in that: the generation temperature of this lining oxide layer is 900-1150 ℃.
4, the method for improving the leakage current and the breakdown voltage of shallow channel isolation area according to claim 1 is characterized in that: the formation method of this silicon oxynitride layer is electricity slurry enhanced chemical vapor deposition method.
5, the method for improving the leakage current and the breakdown voltage of shallow channel isolation area according to claim 1, it is characterized in that: the process gas that deposits this silicon oxynitride layer is silane and oxynitrides.
6, the method for improving the leakage current and the breakdown voltage of shallow channel isolation area according to claim 1, it is characterized in that: the thickness of this silicon oxynitride layer is 50-500 .
7, the method for improving the leakage current and the breakdown voltage of shallow channel isolation area according to claim 1, it is characterized in that: the method that divests this cover curtain layer is a wet etching.
8, the method for improving the leakage current and the breakdown voltage of shallow channel isolation area according to claim 1 is characterized in that: this method that divests this pad oxide is a wet etching.
9, the method for improving the leakage current and the breakdown voltage of shallow channel isolation area according to claim 1, it is characterized in that: this insulating barrier is the silica that utilizes the high-density electric slurry method to be deposited.
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| Application Number | Priority Date | Filing Date | Title |
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| CN 01118829 CN1392603A (en) | 2001-06-18 | 2001-06-18 | Method for improving leakage current and cllapse voltage of shallow channel isolation area |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100375264C (en) * | 2004-10-21 | 2008-03-12 | 台湾积体电路制造股份有限公司 | Shallow trench isolation structure and method for formation thereof |
| CN100378960C (en) * | 2005-03-10 | 2008-04-02 | 海力士半导体有限公司 | Method for fabricating flash memory device |
| CN101523264A (en) * | 2006-08-10 | 2009-09-02 | 松下电工株式会社 | Photoelectric converter |
| CN103594414A (en) * | 2012-08-17 | 2014-02-19 | 华邦电子股份有限公司 | Trench isolation structure and forming method thereof |
-
2001
- 2001-06-18 CN CN 01118829 patent/CN1392603A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100375264C (en) * | 2004-10-21 | 2008-03-12 | 台湾积体电路制造股份有限公司 | Shallow trench isolation structure and method for formation thereof |
| CN100378960C (en) * | 2005-03-10 | 2008-04-02 | 海力士半导体有限公司 | Method for fabricating flash memory device |
| CN101523264A (en) * | 2006-08-10 | 2009-09-02 | 松下电工株式会社 | Photoelectric converter |
| CN103594414A (en) * | 2012-08-17 | 2014-02-19 | 华邦电子股份有限公司 | Trench isolation structure and forming method thereof |
| CN103594414B (en) * | 2012-08-17 | 2016-05-04 | 华邦电子股份有限公司 | Groove isolation construction and forming method thereof |
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