CN1501470A - Method for forming shallow groove spacer between semiconductor bases - Google Patents
Method for forming shallow groove spacer between semiconductor bases Download PDFInfo
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- CN1501470A CN1501470A CNA021487405A CN02148740A CN1501470A CN 1501470 A CN1501470 A CN 1501470A CN A021487405 A CNA021487405 A CN A021487405A CN 02148740 A CN02148740 A CN 02148740A CN 1501470 A CN1501470 A CN 1501470A
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Abstract
The invention discloses a method for forming shadow trench insulator on the semiconductor substrate comprising, forming an open-ended hard shield on the semiconductor substrate surface, forming a shadow trench by etching the semiconductor substrate from the opening, tempering the semiconductor substrate (e.g. silicon substrate) in the environment containing nitrogen oxide or nitrogen / oxygen, forming an insulation layer on the surface of the hard shield, removing the hard shield to expose the upper substrate surface of the semiconductor and remaining a shadow trench insulator. The method according to the invention can lower or eliminate the stress near the shadow trench insulator, thus lifting the quality for the semiconductor product.
Description
Technical field
The present invention relates to integrated circuit (Integrated circuits; ICs) manufacturing technology is particularly relevant for a kind of separator with shallow grooves (shallow trenchisolation that forms among the semiconductor-based end; STI) method, and reduce the stress that produces because of etching shallow trenches by this.
Background technology
In IC industry, separator with shallow grooves replaces traditional localized oxidation of silicon thing (localsilicon oxidation gradually; LOCOS) to be used as the field isolation structure of improvement.Usually separator with shallow grooves process technique comprises that the etching semiconductor substrate to form shallow trench, inserts megohmite insulant among the above-mentioned shallow trench then, next utilizes chemical mechanical milling method (chemical mechanical polishing; CMP) with the above-mentioned megohmite insulant of planarization and form separator with shallow grooves.The step of above-mentioned formation separator with shallow grooves can cause mechanical stress (mechanical stress) or thermal stress (thermal stress) in the active area at the semiconductor-based end, and then causes the difference row or the defective locations of the active area at the semiconductor-based end.Therefore, will cause that the follow-up regions and source that is formed at the elements such as transistor at the semiconductor-based end produces high leakage path (high leakage current path), and reduce the semiconductor product yield.
People's such as Thei United States Patent (USP) the 6th, 350, disclose a kind of formation method of separator with shallow grooves for No. 662, be used for reducing near the defective of shallow trench, this method is to adopt nitrogen tempering mode to carry out in the etching semiconductor substrate about 30 minutes to 150 minutes after forming shallow trench.Reduce between the intrabasement defective of semiconductor, difference row, semiconductor and the oxide layer interface by this and mend ability (Interface trap) and the stress catch electric charge.
People's such as Arghavani United States Patent (USP) discloses the method that forms separator with shallow grooves in the semiconductor-based end the 5th, 780, No. 346 and the 6th, 261, No. 925.This method is etch groove in the semiconductor-based end after, first oxide skin(coating) to be formed in the groove.Then under the environment of the gas of nitrogenous and oxygen, handle, and after the tempering program, form nitrogen oxide in first oxide skin(coating) with between the semiconductor-based end.Yet this silicon oxynitride is under the temperature that improves the silicon oxide layer nitrogenize to be formed.So will increase process complexity and processing procedure cost.
Therefore, need provide a kind of modification method that among the semiconductor-based end, forms separator with shallow grooves, use the stress that is produced when the bombardment of eliminating or being reduced in by reactive ion etching forms the processing procedure of shallow trench parting.
Summary of the invention
In view of this, the object of the present invention is to provide a kind of method that forms separator with shallow grooves among the semiconductor-based end, the stress that processing procedure produced that forms the shallow trench parting can be eliminated or be reduced in to the method, and improve the product yield.
Moreover another purpose of the present invention is to provide a kind of method that forms separator with shallow grooves among the semiconductor-based end, is used for reducing process complexity and manufacturing cost.
According to above-mentioned purpose, the invention provides a kind of method that among the semiconductor-based end, forms separator with shallow grooves, its method is as described below:
At first, form a hard cover screen with opening at above-mentioned semiconductor-based basal surface, and via the above-mentioned semiconductor-based end of above-mentioned opening etching to form a shallow trench; Then, containing nitrogen oxide (NO) or nitrogen (N
2)/oxygen (O
2) environment under tempering is carried out in semiconductor substrate (as silicon base), conformably to form a silicon oxynitride film, in order to barrier layer as the dopant diffusion of avoiding source/drain on the shallow trench surface; In this tempering step, oxidation reaction and nitridation reaction can take place in the silicon base surface that exposes; Then, form a megohmite insulant on above-mentioned hard cover screen surface, to insert above-mentioned shallow trench; Secondly, utilize above-mentioned hard cover screen to be used as and grind to stop layer, and behind the above-mentioned megohmite insulant of planarization, remove above-mentioned hard cover screen, to expose above-mentioned upper surface of substrate of semiconductor and to stay a separator with shallow grooves.
Tempering is preferably carried out in the above-mentioned semiconductor-based end after utilizing standard cleaning liquid and deionized water to carry out prerinse in regular turn, employed standard cleaning liquid is the NH for diluting for example
4OH/H
2O
2The NH of solution (being SC1) or dilution
4OH/HCl solution (being SC2).
Moreover, preferably with the tempering 2 to 15 minutes in the environment that is containing nitrogen oxide or nitrogen/oxygen under about 800 ℃ to 1100 ℃ of the temperature of the above-mentioned semiconductor-based end.
Moreover, the pad nitration case that above-mentioned hard cover screen comprises the pad oxide that is formed at the semiconductor upper surface of substrate and is formed at above-mentioned pad oxide surface.
Moreover the formation of above-mentioned shallow trench preferably utilizes the anisotropic etching method, and to contain HBr, Cl, CF
4For reacting gas is finished.
Moreover above-mentioned megohmite insulant is to utilize high density plasma chemical vapor deposition method (HDPCVD) to finish.
Moreover above-mentioned megohmite insulant is to adopt chemical mechanical milling method or etch-back until upper surface of substrate of semiconductor and curtain layer of hard hood copline roughly, to finish planarization.
Form the method for separator with shallow grooves among the semiconductor-based end according to the present invention, near the stress separator with shallow grooves can be lowered or eliminate, and can promote the semiconductor product yield by this.In addition, silicon oxynitride film 111 is as barrier layer, diffuses to insulating barrier in the shallow trench 110 outward in order to avoid the follow-up admixture that is formed at the source/drain of active region.
Description of drawings
Fig. 1 to Fig. 6 is the processing procedure profile that forms separator with shallow grooves according to the embodiment of the invention among the semiconductor-based end.
Embodiment
Please refer to Fig. 1, a semiconductor-based end 100 that is made of monocrystalline silicon is provided.Then, under oxygen containing high temperature (800 ℃ to 1000 ℃) environment in the pad oxide 102 of about 200 dust to 400 dusts of the above-mentioned semiconductor-based end 100 surperficial growth thickness.This pad oxide 102 be used for strengthening the pad nitration case 104 of follow-up formation and the semiconductor-based end 100 between tackifying ability.Then, utilize Low Pressure Chemical Vapor Deposition (lowpressure chemical vapor deposition; And import SiH LPCVD),
2Cl
2With NH
3Be used as the deposition reaction source Deng mist, to form the pad nitration case 104 of about 1000 dust to 2000 dusts of thickness on above-mentioned pad oxide 102 surfaces, above-mentioned deposition pressure is approximately 0.1 Bristol (Torr) to 1.0 Bristols, and depositing temperature is approximately 700 ℃ to 800 ℃.
Then, utilize traditional little shadow technology (lihthography) to form photoresistance pattern (photoresist pattern) (not illustrating among the figure) with opening on above-mentioned pad nitration case 104 surfaces, secondly, utilize reactive ion-etching (reactive ion etching; RIE) via the opening of above-mentioned photoresistance pattern, above-mentioned pad nitration case 104 of anisotropic ground (anisotropically) etching and above-mentioned pad oxide 102, to expose the upper surface at the above-mentioned semiconductor-based end 100, and form hard cover screen 106 (hard mask) with opening 108, this hard cover screen 106 is made of residual pad oxide 102 and pad nitration case 104 as shown in Figure 1.Next, remove above-mentioned photoresistance pattern.
Then, please refer to Fig. 2, utilize and contain HBr, Cl, CF
4Etching gas, and adopt suitable etching machine to carry out etching via 106 pairs of above-mentioned semiconductor-based ends 100 of opening of above-mentioned hard cover screen 108.In this step, can form the shallow trench 110 that the degree of depth is approximately 3000 dust to 5000 dusts, therefore near the sidewall of above-mentioned shallow trench 110, caused the mechanical stress that plasma bombardment caused also because of etching step.Then utilize standard cleaning liquid (standard clean solutions), for example Xi Shi NH
4OH/H
2O
2The NH of solution (being SC1) or dilution
4OH/HCl solution (being SC2) combines with deionized water, and semiconductor substrate 100 is cleaned.
Afterwards, please refer to Fig. 3, in the environment that contains nitrogen oxide (NO), shallow trench 110 surfaces that add conformably form silicon oxynitride film 111 at semiconductor-based the end 100 under about 800 ℃ to 1100 ℃ of temperature, and its thickness is approximately 20 dust to the 30 Izod right sides.The time that forms this silicon oxynitride film 111 is about 2 to 15 minutes.This tempering manufacturing process is in order to reduce or to remove by etching shallow trenches 110 caused stress.
Then as shown in Figure 4, utilize high density plasma chemical vapor deposition method (high densityplasma pressure chemical vapor deposition; HDPCVD), and adopt tetraethyl-metasilicate (tetra-ethyl-ortho-silicate) and ozone (ozone) for reacting gas to form the megohmite insulant 112 that constitutes by earth silicon material at above-mentioned shallow trench 110.On the other hand, also can adopt the mist of silane and oxygen to replace the mist of above-mentioned tetraethyl-metasilicate and ozone.
Then, please refer to Fig. 5, utilize above-mentioned hard cover screen 106 to be used as and grind to stop layer (polishing stoplayer), and utilize the above-mentioned megohmite insulant 112 of chemical mechanical milling method planarization, to stay the slightly contour megohmite insulant 112a of upper surface and above-mentioned hard cover screen 106.
Then, please refer to Fig. 6, utilize hydrofluoric acid solution (hydrofluoric acid solution), remove pad nitration case 104 with hot phosphoric acid solution again, till the upper surface that exposes the above-mentioned semiconductor-based end 100 to remove pad oxide 102.In this wet etch step, above-mentioned megohmite insulant 112a is loss and stay megohmite insulant 112b to some extent also.
Form the method for separator with shallow grooves among the semiconductor-based end according to the present invention, near the stress separator with shallow grooves can be lowered or eliminate, and can promote the semiconductor product yield by this.In addition, silicon oxynitride film 111 is as barrier layer, diffuses to insulating barrier in the shallow trench 110 outward in order to avoid the follow-up admixture that is formed at the source/drain of active region.
Moreover different with conventional method is, the present invention does not need first oxide layer, so process complexity and manufacturing cost are minimized.
Though the present invention discloses as above with preferred embodiment; right its is not in order to qualification the present invention, any those who are familiar with this art, without departing from the spirit and scope of the invention; when can doing a little change and retouching, so the present invention's protection range is as the criterion when looking claims scope person of defining.
Claims (10)
1. a method that forms separator with shallow grooves among the semiconductor-based end is characterized in that: comprise the following steps: at least
The hard cover screen that has opening in above-mentioned semiconductor-based basal surface formation one;
Via the above-mentioned semiconductor-based end of above-mentioned opening etching to form a shallow trench;
Under the environment that contains nitrogen oxide (NO), conformably form a silicon oxynitride film on this shallow trench surface;
Form a megohmite insulant on above-mentioned hard cover screen surface, to insert above-mentioned shallow trench;
Utilize above-mentioned hard cover screen to be used as and grind to stop layer, and the above-mentioned megohmite insulant of planarization; And
Remove above-mentioned hard cover screen, exposing above-mentioned upper surface of substrate of semiconductor, and stay a separator with shallow grooves.
2. the method for claim 1 is characterized in that: the pad nitration case that above-mentioned hard cover screen comprises pad oxide and is formed at above-mentioned pad oxide surface.
3. the method for claim 1, it is characterized in that: the formation of above-mentioned shallow trench is to utilize the anisotropic etching method, and to contain HBr, Cl and CF
4For reacting gas is finished.
4. the method for claim 1, it is characterized in that: above-mentioned megohmite insulant utilizes high density plasma chemical vapor deposition method (HDPCVD) and finishes.
5. the method for claim 1 is characterized in that: above-mentioned megohmite insulant adopts chemical mechanical milling method to finish.
6. the method for claim 1 is characterized in that: the removal step of above-mentioned hard cover screen is to adopt phosphoric acid solution to finish.
7. the method for claim 1 is characterized in that: this silicon oxynitride film is to form down for about 800 ℃ to 1100 ℃ in temperature.
8. method as claimed in claim 7 is characterized in that: the time that forms this silicon oxynitride film is about 2 to 15 minutes.
9. the method for claim 1, it is characterized in that: the thickness of this silicon oxynitride film is about 20 to 30 dusts.
10. a method that forms separator with shallow grooves among the semiconductor-based end is characterized in that: comprise the following steps: at least
The hard cover screen that has opening in above-mentioned semiconductor-based basal surface formation one;
Via the above-mentioned semiconductor-based end of above-mentioned opening etching to form a shallow trench;
Containing nitrogen (N
2) and oxygen (O
2) environment under conformably form a silicon oxynitride film on this shallow trench surface;
Form a megohmite insulant on above-mentioned hard cover screen surface, to insert above-mentioned shallow trench;
Utilize above-mentioned hard cover screen to be used as and grind to stop layer, and the above-mentioned megohmite insulant of planarization; And
Remove above-mentioned hard cover screen, exposing above-mentioned upper surface of substrate of semiconductor, and stay a separator with shallow grooves.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA021487405A CN1501470A (en) | 2002-11-15 | 2002-11-15 | Method for forming shallow groove spacer between semiconductor bases |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA021487405A CN1501470A (en) | 2002-11-15 | 2002-11-15 | Method for forming shallow groove spacer between semiconductor bases |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100375264C (en) * | 2004-10-21 | 2008-03-12 | 台湾积体电路制造股份有限公司 | Shallow trench isolation structure and method for formation thereof |
| US7544561B2 (en) | 2006-11-06 | 2009-06-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Electron mobility enhancement for MOS devices with nitrided polysilicon re-oxidation |
| CN101577242B (en) * | 2008-05-05 | 2011-03-23 | 中芯国际集成电路制造(北京)有限公司 | Shallow trench isolation structure and forming method thereof |
| CN103904017A (en) * | 2012-12-24 | 2014-07-02 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
-
2002
- 2002-11-15 CN CNA021487405A patent/CN1501470A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100375264C (en) * | 2004-10-21 | 2008-03-12 | 台湾积体电路制造股份有限公司 | Shallow trench isolation structure and method for formation thereof |
| US7544561B2 (en) | 2006-11-06 | 2009-06-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Electron mobility enhancement for MOS devices with nitrided polysilicon re-oxidation |
| CN101577242B (en) * | 2008-05-05 | 2011-03-23 | 中芯国际集成电路制造(北京)有限公司 | Shallow trench isolation structure and forming method thereof |
| CN103904017A (en) * | 2012-12-24 | 2014-07-02 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
| CN103904017B (en) * | 2012-12-24 | 2017-11-10 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacture method of semiconductor devices |
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