CN1501470A - Method for forming shallow trench isolation in semiconductor substrate - Google Patents

Abstract

A method of forming shallow trench isolation in a semiconductor substrate; firstly, forming a hard mask with an opening on the surface of the semiconductor substrate, and etching the semiconductor substrate through the opening to form a shallow trench; then, annealing the semiconductor substrate (such as a silicon substrate) in an environment containing nitrogen oxide or nitrogen/oxygen to form a silicon oxynitride film on the surface of the shallow trench to be used as a barrier layer for preventing the diffusion of the dopant of the source/drain; then, forming an insulating material on the surface of the hard mask to fill the shallow trench; secondly, using the hard mask as a polishing stop layer, and removing the hard mask after planarizing the insulating material to expose the upper surface of the semiconductor substrate and leave a shallow trench isolation; the method of the invention can reduce or eliminate the stress near the shallow trench isolation, thereby improving the yield of semiconductor products; in addition, the silicon oxynitride film is used as a barrier layer to prevent the dopant of the source/drain electrode formed in the active region from diffusing out to the insulating layer in the shallow trench.

Description

Method of forming shallow trench isolation in semiconductor substrate

technical field

The present invention relates to the manufacturing technology of integrated circuit (Integrated circuits; ICs), relate in particular to a kind of method for forming shallow trench isolation (shallow trench isolation; STI) in semiconductor substrate, and thereby reduce the impact caused by etching shallow trenches. resulting stress.

Background technique

In the integrated circuit industry, shallow trench isolations have gradually replaced traditional local silicon oxide (LOCOS) as an improved field isolation structure. The usual shallow trench isolation process technology includes etching the semiconductor substrate to form shallow trenches, and then filling insulating substances into the shallow trenches, and then using chemical mechanical polishing (CMP) to planarize the above-mentioned shallow trenches. insulating material and form shallow trench isolation. The above-mentioned steps of forming the STIs will cause mechanical stress or thermal stress in the active region of the semiconductor substrate, thereby causing dislocation or defect positions in the active region of the semiconductor substrate. Therefore, a high leakage current path (high leakage current path) will be generated in the source/drain regions of components such as transistors formed subsequently on the semiconductor substrate, thereby reducing the yield of semiconductor products.

U.S. Patent No. 6,350,662 to Thei et al. discloses a method of forming shallow trench spacers for reducing defects near shallow trenches by using nitrogen tempering after etching a semiconductor substrate to form shallow trenches About 30 minutes to 150 minutes. In this way, the defects, dislocations, charge trapping ability (Interface trap) and stress of the interface between the semiconductor and the oxide layer in the semiconductor substrate are reduced.

US Patent Nos. 5,780,346 and 6,261,925 to Arghavani et al. disclose methods of forming shallow trench spacers in semiconductor substrates. The method is to form a first oxide layer in the trench after etching the trench in the semiconductor substrate. Then, it is processed under the atmosphere of gas containing nitrogen and oxygen, and after the tempering process, oxynitride is formed between the first oxide layer and the semiconductor substrate. However, the silicon oxynitride is formed by nitridating the silicon oxide layer at elevated temperature. This will increase the complexity and cost of the manufacturing process.

Therefore, there is a need to provide an improved method of forming shallow trench spacers in a semiconductor substrate, so as to eliminate or reduce the stress generated during the process of forming shallow trench spacers by bombardment of reactive ion etching.

Contents of the invention

In view of this, the object of the present invention is to provide a method for forming shallow trench spacers in a semiconductor substrate, this method can eliminate or reduce the stress generated in the process of forming shallow trench spacers, and improve product quality. Rate.

Furthermore, another object of the present invention is to provide a method for forming shallow trench isolators in a semiconductor substrate for reducing process complexity and manufacturing cost.

According to the above object, the present invention provides a method for forming shallow trench isolators in a semiconductor substrate, the method is as follows:

First, a hard mask with an opening is formed on the surface of the above-mentioned semiconductor substrate, and the above-mentioned semiconductor substrate is etched through the above-mentioned opening to form _a shallow trench; ₂ ) Tempering the semiconductor substrate (such as silicon substrate) in an environment to conformably form a silicon oxynitride film on the surface of the shallow trench, which is used as a barrier layer to prevent the dopant diffusion of the source/drain ; In this tempering step, an oxidation reaction and a nitriding reaction will occur on the exposed silicon substrate surface; then, an insulating substance is formed on the surface of the above-mentioned hard mask to fill the above-mentioned shallow trench; secondly, using the above-mentioned hard mask After the hard mask is used as a grinding stop layer and the insulating material is planarized, the hard mask is removed to expose the upper surface of the semiconductor substrate and leave a shallow trench isolation.

The above-mentioned semiconductor substrate is preferably tempered after pre-cleaning with standard cleaning solution and deionized water in sequence. The standard cleaning solution used is, for example, diluted NH ₄ OH/H ₂ O ₂ solution (ie SC1) Or dilute NH ₄ OH/HCl solution (ie SC2).

Furthermore, it is preferred to temper the aforementioned semiconductor substrate at a temperature of about 800° C. to 1100° C. in an atmosphere containing nitrogen oxide or nitrogen/oxygen for 2 to 15 minutes.

Furthermore, the hard mask includes a pad oxide layer formed on the upper surface of the semiconductor substrate and a pad nitride layer formed on the surface of the pad oxide layer.

Furthermore, the formation of the above-mentioned shallow trenches is preferably performed by using an anisotropic etching method and using HBr, Cl, and CF ₄ as reactive gases to complete.

Furthermore, the above-mentioned insulating material is completed by high-density plasma chemical vapor deposition (HDPCVD).

Furthermore, the insulating substance is planarized by chemical mechanical polishing or etching back until the upper surface of the semiconductor substrate is substantially coplanar with the hard mask layer.

According to the method for forming the shallow trench isolation in the semiconductor substrate of the present invention, the stress near the shallow trench isolation can be reduced or eliminated, thereby improving the yield of semiconductor products. In addition, the silicon oxynitride film 111 is used as a barrier layer to prevent the dopant formed in the source/drain of the active region from diffusing out to the insulating layer in the shallow trench 110 .

Description of drawings

1 to 6 are cross-sectional views of a process for forming shallow trench isolators in a semiconductor substrate according to an embodiment of the present invention.

Detailed ways

Referring to FIG. 1 , a semiconductor substrate 100 made of single crystal silicon is provided. Next, a pad oxide layer 102 with a thickness of approximately 200 angstroms to 400 angstroms is grown on the surface of the semiconductor substrate 100 in an oxygen-containing high temperature (800° C. to 1000° C.) environment. The pad oxide layer 102 is used to enhance the adhesion between the subsequently formed pad nitride layer 104 and the semiconductor substrate 100 . Next, using low pressure chemical vapor deposition (LPCVD), and introducing a mixed gas such as SiH ₂ Cl ₂ and NH ₃ as a deposition reaction source, to form a thickness of about 1000 angstroms to 2000 angstroms on the surface of the pad oxide layer 102. For the pad nitride layer 104 of angstroms, the deposition pressure is about 0.1 Torr to 1.0 Torr, and the deposition temperature is about 700° C. to 800° C.

Then, a photoresist pattern (photoresist pattern) with openings (not shown in the figure) is formed on the surface of the above-mentioned pad nitride layer 104 by using conventional lithography technology (lihthography), and secondly, using reactive ion etching (reactive ion etching) RIE) through the opening of the photoresist pattern, anisotropically etch the pad nitride layer 104 and the pad oxide layer 102 to expose the upper surface of the semiconductor substrate 100, and form a hard layer with an opening 108 A hard mask 106 (hard mask), as shown in FIG. 1 , is composed of a remaining pad oxide layer 102 and a pad nitride layer 104 . Next, the above photoresist pattern is removed.

Next, referring to FIG. 2 , the semiconductor substrate 100 is etched through the opening 106 of the hard mask 108 by using an etching gas containing HBr, Cl, and CF ₄ with an appropriate etching machine. In this step, a shallow trench 110 with a depth of approximately 3000 angstroms to 5000 angstroms can be formed, but mechanical stress caused by plasma bombardment in the etching step is caused near the sidewalls of the shallow trench 110 . Then use standard clean solutions (standard clean solutions), such as diluted NH ₄ OH/H ₂ O ₂ solution (ie SC1) or diluted NH ₄ OH/HCl solution (ie SC2) combined with deionized water, to clean the semiconductor substrate 100 Clean up.

Afterwards, referring to FIG. 3 , a silicon oxynitride film 111 is conformally formed on the surface of the shallow trench 110 in the semiconductor substrate 100 in an environment containing nitrogen oxide (NO) at a temperature of about 800° C. to 1100° C., with a thickness of about It is about 20 angstroms to 30 angstroms. The time for forming the silicon oxynitride film 111 is about 2 to 15 minutes. The tempering process is used to reduce or remove the stress caused by etching the shallow trench 110 .

Next, as shown in Figure 4, using high density plasma pressure chemical vapor deposition (high density plasma pressure chemical vapor deposition; HDPCVD), and using tetra-ethyl-ortho-silicate (tetra-ethyl-ortho-silicate) and ozone (ozone) as the reaction gas to form an insulating substance 112 made of silicon dioxide in the shallow trench 110 . On the other hand, a mixed gas of silane and oxygen may also be used instead of the mixed gas of tetraethylsilicate and ozone.

Then, please refer to FIG. 5 , using the hard mask 106 as a polishing stopper, and planarizing the insulating substance 112 by chemical mechanical polishing, so that the upper surface is slightly equal to the hard mask 106 insulating material 112a.

Next, referring to FIG. 6 , the pad oxide layer 102 is removed by hydrofluoric acid solution, and the pad nitride layer 104 is removed by hot phosphoric acid solution until the upper surface of the semiconductor substrate 100 is exposed. In this wet etching step, the insulating substance 112a will also be lost to leave the insulating substance 112b.

According to the method for forming the shallow trench isolation in the semiconductor substrate of the present invention, the stress near the shallow trench isolation can be reduced or eliminated, thereby improving the yield of semiconductor products. In addition, the silicon oxynitride film 111 is used as a barrier layer to prevent the dopant formed in the source/drain of the active region from diffusing out to the insulating layer in the shallow trench 110 .

Furthermore, different from the traditional method, the present invention does not require the first oxide layer, so the process complexity and manufacturing cost are reduced.

Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Anyone familiar with this art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, this The scope of protection of an invention shall be defined by the scope of the claims.

Claims (10)

1. a method that forms separator with shallow grooves among the semiconductor-based end is characterized in that: comprise the following steps: at least

The hard cover screen that has opening in above-mentioned semiconductor-based basal surface formation one;

Via the above-mentioned semiconductor-based end of above-mentioned opening etching to form a shallow trench;

Under the environment that contains nitrogen oxide (NO), conformably form a silicon oxynitride film on this shallow trench surface;

Form a megohmite insulant on above-mentioned hard cover screen surface, to insert above-mentioned shallow trench;

Utilize above-mentioned hard cover screen to be used as and grind to stop layer, and the above-mentioned megohmite insulant of planarization; And

Remove above-mentioned hard cover screen, exposing above-mentioned upper surface of substrate of semiconductor, and stay a separator with shallow grooves.

2. the method for claim 1 is characterized in that: the pad nitration case that above-mentioned hard cover screen comprises pad oxide and is formed at above-mentioned pad oxide surface.

3. the method for claim 1, it is characterized in that: the formation of above-mentioned shallow trench is to utilize the anisotropic etching method, and to contain HBr, Cl and CF ₄For reacting gas is finished.

4. the method for claim 1, it is characterized in that: above-mentioned megohmite insulant utilizes high density plasma chemical vapor deposition method (HDPCVD) and finishes.

5. the method for claim 1 is characterized in that: above-mentioned megohmite insulant adopts chemical mechanical milling method to finish.

6. the method for claim 1 is characterized in that: the removal step of above-mentioned hard cover screen is to adopt phosphoric acid solution to finish.

7. the method for claim 1 is characterized in that: this silicon oxynitride film is to form down for about 800 ℃ to 1100 ℃ in temperature.

8. method as claimed in claim 7 is characterized in that: the time that forms this silicon oxynitride film is about 2 to 15 minutes.

9. the method for claim 1, it is characterized in that: the thickness of this silicon oxynitride film is about 20 to 30 dusts.

10. a method that forms separator with shallow grooves among the semiconductor-based end is characterized in that: comprise the following steps: at least

The hard cover screen that has opening in above-mentioned semiconductor-based basal surface formation one;

Via the above-mentioned semiconductor-based end of above-mentioned opening etching to form a shallow trench;

Containing nitrogen (N ₂) and oxygen (O ₂) environment under conformably form a silicon oxynitride film on this shallow trench surface;

Form a megohmite insulant on above-mentioned hard cover screen surface, to insert above-mentioned shallow trench;

Utilize above-mentioned hard cover screen to be used as and grind to stop layer, and the above-mentioned megohmite insulant of planarization; And

Remove above-mentioned hard cover screen, exposing above-mentioned upper surface of substrate of semiconductor, and stay a separator with shallow grooves.

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