CN103904017A - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
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- CN103904017A CN103904017A CN201210568208.4A CN201210568208A CN103904017A CN 103904017 A CN103904017 A CN 103904017A CN 201210568208 A CN201210568208 A CN 201210568208A CN 103904017 A CN103904017 A CN 103904017A
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- shallow trench
- semiconductor device
- semiconductor substrate
- manufacture method
- trench isolation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention provides a method for manufacturing a semiconductor device, and relates to the technical field of semiconductors. The method comprises the following steps: step S101, providing a semiconductor substrate and forming a hard mask on the semiconductor substrate; step S102, forming a shallow trench isolation in the hard mask and the semiconductor substrate; step S103, forming a second mask on the semiconductor substrate through a direct self-assembly graphical process, and using the second mask to etch the semiconductor substrate to form a very shallow trench isolation trench and stripes on the two sides thereof; and step S104, forming a very shallow trench isolation in the very shallow trench isolation trench. According to the method for manufacturing a semiconductor device of the invention, a segmented field effect transistor (SegFet) is manufactured by a method in which a shallow trench isolation is formed first and then a very shallow trench isolation is formed, the overlay issue between a shallow trench isolation and a very shallow trench isolation easily caused due to the adoption of a double patterning technology is avoided, and the yield of the semiconductor device is improved.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of manufacture method of semiconductor device.
Background technology
How reducing short-channel effect (short channel effect), is one of key issue of facing of process for fabrication of semiconductor device.In prior art, by using the transistor (SegFet) of raceway groove segmentation to make the technical scheme of semiconductor device, be one of very promising technology of the short-channel effect that can be used for reducing device.
In the prior art, use structure (Fig. 1 is the cutaway view along grid width direction) as shown in Figure 1 of the semiconductor device of the transistor (SegFet) of raceway groove segmentation.Shallow trench isolation STI 101, grid 104 that this semiconductor device comprises Semiconductor substrate 100 and is located thereon, wherein channel region is surpassed shallow trench isolation from (Very Shallow Trench Isolation, VSTI) 102 be separated into multiple subsegments, Semiconductor substrate 100(particularly, is channel part) part between every two adjacent VSTI or between VSTI and STI is strip pattern (stripe) 103.Wherein, the distribution of strip pattern 103 is by shallow trench isolation from 101 and the determining positions of super shallow trench isolation from 102, and its width is subject to the impact of precision of manufacturing process.Because channel region has been separated into multiple subsegments by VSTI, form the transistor of raceway groove segmentation, so this semiconductor device is subject to the impact of short-channel effect less, this structure has reduced the short-channel effect of device.In order to realize the technique effect that better reduces short-channel effect, must form good strip pattern; And the width of the strip pattern of formation is less, the threshold voltage performance that the semiconductor device of manufacture has had.Therefore, in the manufacture process of semiconductor device, how forming strip pattern, is one of key factor of restriction semiconductor device manufacture.
At present, in the manufacturing process of semiconductor device, manufacture and use the transistorized semiconductor device of raceway groove segmentation generally to adopt double-pattern (double patterning) technology, first etching forms strip pattern (forming VSTI) etching formation STI again.But the method is easy to cause the overlap problem (overlay issue) of STI and VSTI, this has just caused forming good strip pattern, and then has caused the bad of semiconductor device.
Therefore,, in order to address the above problem, a kind of manufacture method of new semiconductor device need to be proposed.
Summary of the invention
For the deficiencies in the prior art, the invention provides a kind of manufacture method of semiconductor device, the method comprises:
Step S101: Semiconductor substrate is provided, forms hard mask in described Semiconductor substrate;
Step S102: in described hard mask and Semiconductor substrate, form shallow trench isolation from;
Step S103: form the second mask by the graphical technique of direct self assembly in Semiconductor substrate, utilize described the second mask to carry out etching to described Semiconductor substrate, form super shallow trench isolated groove and be positioned at the strip pattern of its both sides;
Step S104: in described super shallow trench isolated groove form super shallow trench isolation from.
Further, described step S102 comprises:
Step S1021: form shallow trench isolated groove in described hard mask and Semiconductor substrate;
Step S1022: in described shallow trench isolated groove, fill shallow trench isolated material and carry out CMP, with in described shallow trench isolated groove, form shallow trench isolation from.
Wherein, described shallow trench isolated material is oxide.
Further, described step S103 comprises:
Step S1031: remove described hard mask be positioned at described Semiconductor substrate intend forming super shallow trench isolation from the part in the region of strip pattern;
Step S1032: form patterned the second mask in the removed region of described hard mask by the graphical technique of direct self assembly;
Step S1033: utilize described the second mask to carry out etching to described Semiconductor substrate, form super shallow trench isolated groove and strip pattern in described Semiconductor substrate, wherein, described strip pattern is positioned at the both sides of described super shallow trench isolated groove.
Wherein, in step S1031, remove the lithographic method adopting in the method for employing of described hard mask and step S1033, be dry etching.
Wherein, in described step S1031, described plan form super shallow trench isolation from the region of strip pattern be active area.
Wherein, described step S1032 comprises:
Step S10321: at the different amount Molecularly Imprinted Polymer of the removed area filling of described hard mask;
Step S10322: toast described different amount Molecularly Imprinted Polymer, to form patterned the second mask.
Further, described step S104 comprises: in described super shallow trench isolated groove, fill super shallow trench isolated material carry out CMP, with form super shallow trench isolation from.
Wherein, described super shallow trench isolated material is oxide.
The width of the described strip pattern wherein, forming in described step S103 is not less than the length of the grid of described semiconductor device.The thickness of the hard mask wherein, forming in step S101 is
Further, after described step S104, also comprise step S105: in described Semiconductor substrate, form gate dielectric and grid.
Wherein, described gate dielectric is only positioned at the top of described strip pattern.
Further, after described step S105, also comprise step S106: form gate lateral wall and source electrode and drain electrode.
The manufacture method of semiconductor device of the present invention, first form shallow trench isolation from (STI) owing to having adopted, form again super shallow trench isolation and manufacture the transistor of raceway groove segmentation from the mode of (VSTI), avoid available technology adopting double-pattern (double patterning) technology easily to cause shallow trench isolation from (STI) and super shallow trench isolation from (VSTI) overlapping problem (overlayissue), improved the yield of semiconductor device.
Accompanying drawing explanation
Following accompanying drawing of the present invention is used for understanding the present invention in this as a part of the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.
In accompanying drawing:
Fig. 1 is the schematic cross sectional view along grid width direction of the semiconductor device of prior art;
Fig. 2 A-Fig. 2 H is the schematic cross sectional view (along grid width direction) of the figure that forms of the each step of the manufacture method of the semiconductor device that proposes of the present invention;
Fig. 3 is the flow chart of the manufacture method of a kind of semiconductor device of proposing of the present invention.
Embodiment
In the following description, a large amount of concrete details have been provided to more thorough understanding of the invention is provided.But, it is obvious to the skilled person that the present invention can be implemented without one or more these details.In other example, for fear of obscuring with the present invention, be not described for technical characterictics more well known in the art.
Should be understood that, the present invention can be with multi-form enforcement, and should not be interpreted as the embodiment that is confined to propose here.On the contrary, provide these embodiment to expose thorough and complete, and scope of the present invention is fully passed to those skilled in the art.In the accompanying drawings, for clear, the size in Ceng He district and relative size may be exaggerated.Same reference numerals represents identical element from start to finish.
Be understood that, when element or layer be called as " ... on ", " with ... adjacent ", " being connected to " or " being coupled to " other element or when layer, its can be directly on other element or layer, with it adjacent, connect or be coupled to other element or layer, or can there is element or layer between two parties.On the contrary, when element be called as " directly exist ... on ", when " with ... direct neighbor ", " being directly connected to " or " being directly coupled to " other element or layer, there is not element or layer between two parties.Although it should be understood that and can use term first, second, third, etc. to describe various elements, parts, district, floor and/or part, these elements, parts, district, floor and/or part should not limited by these terms.These terms are only used for distinguishing an element, parts, district, floor or part and another element, parts, district, floor or part.Therefore, do not departing under the present invention's instruction, the first element discussed below, parts, district, floor or part can be expressed as the second element, parts, district, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... under ", " ... on ", " above " etc., thereby can be used for convenience of description the relation of element shown in description figure or feature and other element or feature here.It should be understood that except the orientation shown in figure, spatial relationship term intention also comprise use and operate in the different orientation of device.For example, if the device in accompanying drawing upset, then, be described as " below other element " or " under it " or " under it " element or feature will be oriented to other element or feature " on ".Therefore, exemplary term " ... below " and " ... under " can comprise upper and lower two orientations.Device can additionally be orientated (90-degree rotation or other orientation) and as used herein spatial description language correspondingly explained.
The object of term is only to describe specific embodiment and not as restriction of the present invention as used herein.In the time that this uses, " one " of singulative, " one " and " described/to be somebody's turn to do " also intention comprise plural form, unless the other mode of pointing out known in context.It is also to be understood that term " composition " and/or " comprising ", in the time using in these specifications, determine the existence of described feature, integer, step, operation, element and/or parts, but do not get rid of one or more other existence or the interpolations of feature, integer, step, operation, element, parts and/or group.In the time that this uses, term "and/or" comprises any and all combinations of relevant Listed Items.
Here with reference to the cross-sectional view of the schematic diagram as desirable embodiment of the present invention (and intermediate structure), inventive embodiment is described.Like this, can expect due to for example manufacturing technology and/or tolerance cause from shown in the variation of shape.Therefore, embodiments of the invention should not be confined to the given shape in district shown here, but comprise owing to for example manufacturing the form variations causing.For example, the Qi edge, injection region that is shown as rectangle has round or bending features and/or implantation concentration gradient conventionally, rather than binary from injection region to non-injection regions changes.Equally, when the disposal area forming by injection can cause this disposal area and injection to be carried out some injections in the district between the surface of process.Therefore, the district showing in figure is in fact schematically, their shape be not intended display device district true form and be not intended to limit scope of the present invention.
Unless otherwise defined, all terms (comprising technology and scientific terminology) have the identical implication of conventionally understanding with the those of ordinary skill in field of the present invention as used herein.Also will understand, in dictionary such as common use, defined term should be understood to have the implication consistent with they implications in the environment of association area and/or these specifications, and can not explaining in desirable or excessively formal meaning, unless definition so expressly here.
In order thoroughly to understand the present invention, will detailed step and detailed structure be proposed in following description, so that the manufacture method of the semiconductor device that explaination the present invention proposes.Preferred embodiment of the present invention is described in detail as follows, but except these are described in detail, the present invention can also have other execution modes.
With reference to Fig. 2 A-Fig. 2 H and Fig. 3, the detailed step of an illustrative methods of manufacture method of the semiconductor device of the present invention's proposition is described below.Wherein, Fig. 2 A-Fig. 2 H is the schematic cross sectional view (along grid width direction) of the figure that forms of the each step of manufacture method of the semiconductor device that proposes of the present invention; Fig. 3 is the flow chart of the manufacture method of a kind of semiconductor device of proposing of the present invention.
The manufacture method of the semiconductor device of the embodiment of the present invention, comprises the steps:
Step 1: semi-conductive substrate 200 is provided, forms hard mask 201 in described Semiconductor substrate 200, the figure of formation as shown in Figure 2 A.Wherein, hard mask 201 thickness be
As example, in the present embodiment, described Semiconductor substrate 200 selects single crystal silicon material to form.
Step 2: form shallow trench isolated groove (STI trench) 202 in hard mask 201 and Semiconductor substrate 200, the figure of formation as shown in Figure 2 B.
Wherein, shallow trench isolated groove, refer to be used to form shallow trench isolation from groove, shallow trench isolation is from being formed in this groove.Exemplary, form the method for trench isolations groove 202, can be: the hard mask 201 of etching intend forming shallow trench isolation from position form opening; Then utilize the hard mask 201 of this formation opening as mask etching Semiconductor substrate 200, to form trench isolations groove 202 in Semiconductor substrate 200.
Step 3: from (STI) 203, the figure of formation as shown in Figure 2 C at the interior formation shallow trench isolation of shallow trench isolated groove 202.
Exemplary, this step can comprise the steps:
Step 301, fill described shallow trench isolated groove 202 with shallow trench isolated material;
Step 302, described Semiconductor substrate 200 is carried out to CMP, remove unnecessary shallow trench isolated material., remove the part of shallow trench isolated material higher than hard mask 201.
Wherein, shallow trench isolated material can be oxide (silica) or other suitable materials.In the present embodiment, in the time removing unnecessary shallow trench isolated material, hard mask 201 also can be removed a part.
Step 4: hard mask 201 is carried out to selective removal, remove hard mask 201 be positioned in Semiconductor substrate 200 intend forming super shallow trench isolation from the part in the region of strip pattern, the figure of formation is as shown in Figure 2 D.
Wherein, hard mask 201 be positioned in Semiconductor substrate 200, intend forming super shallow trench isolation from the part in the region of strip pattern, be exactly generally the part of hard mask 201 between two adjacent STI, as shown in Figure 2 D.In the present embodiment, in Semiconductor substrate 200, intend forming super shallow trench isolation from the region of strip pattern, be preferably and comprise whole active area (AA district).In the time all forming strip pattern in whole active area, can make the better effects if of transistorized raceway groove segmentation, further improve the performance of device.
Removing the method that hard mask 201 adopts, can be dry etching.
Step 5: form patterned the second mask 204 by the graphical technique of direct self assembly (Directed Self-assemblypatterning, DSA patterning) removed region of hard mask 201 in Semiconductor substrate 200.Wherein, the open area 2041 of the second mask 204 is corresponding to the position that will form super shallow trench isolated groove, and the second region of mask 204 except open area 2041 is corresponding to the region that will form strip pattern.The figure forming, as shown in Figure 2 E.
Wherein, particularly, the method that forms patterned the second mask 204 by the graphical technique of direct self assembly (DSA patterning) comprises the steps:
Step 501, at the hard appropriate different amount Molecularly Imprinted Polymer (copolymer) of the removed area filling of mask 201;
Step 502, baking (bake) described different amount Molecularly Imprinted Polymer, to form patterned the second mask 204.
Conventionally, the mask forming by DSA patterning technique has identical figure and spacing, therefore, use which to form the second mask 204, can guarantee that the homogeneous of the super shallow trench isolated groove of subsequent etching formation and the figure of strip pattern, with consistent, is conducive to improve the performance of semiconductor device.And DSA patterning technique can realize higher graphical of precision, makes the width of the strip pattern forming less, and then guarantees that the semiconductor device of manufacturing has better threshold voltage performance.
Step 6: utilize the second mask 204 etching semiconductor substrates 200, form super shallow trench isolated groove (VSTI trench) 205 and strip pattern 205 ' in described Semiconductor substrate 200.Wherein, strip pattern 205 ' is positioned at the both sides of super shallow trench isolated groove, strip pattern 205 ' adjacent super shallow trench isolation between or adjacent super shallow trench isolation from and front trench isolations between.The figure forming, as shown in Figure 2 F.
Wherein, super shallow trench isolated groove (VSTI trench), refers to and is used to form the groove of super shallow trench isolation from (VSTI), shallow trench isolation is from being formed in this groove.
Wherein, the method for Semiconductor substrate 200 described in etching, adopts dry etching.
Preferably, the number of the strip pattern 205 ' of formation is multiple (multi-stripes), and its width equates, and spacing between adjacent strip pattern 205 ' equates (width that is VSTI trench205 equates).This design can make the segmentation of raceway groove of semiconductor device more even, and then guarantees that semiconductor device has better electrology characteristic.
Wherein, further preferred, the width of strip pattern 205 ' is more than or equal to the length of the grid that (being not less than) will form.
Step 7: from (VSTI) 206, the figure of formation as shown in Figure 2 G at the super shallow trench isolation of the interior formation of super shallow trench isolated groove 205.
Exemplary, this step can comprise the steps:
Step 701, the super shallow trench isolated material of use are filled described super shallow trench isolated groove 205;
Step 702, described Semiconductor substrate 200 is carried out to CMP, remove unnecessary super shallow trench isolated material, to form super shallow trench isolation from 206., remove the part of shallow trench isolated material higher than Semiconductor substrate 200.
Wherein, super shallow trench isolated material can be oxide (silica) or other suitable materials.In the present embodiment, in the time removing unnecessary super shallow trench isolated material, Semiconductor substrate 200 also can be removed a part.
Step 8: form gate dielectric 207 and grid 208 in Semiconductor substrate 200, the figure of formation is as shown in Fig. 2 H.
Wherein, preferred, the gate dielectric 207 of formation is only positioned at the top of strip pattern 205 ', as shown in Fig. 2 H.This structure and gate dielectric cover compared with whole Semiconductor substrate (simultaneously cover super shallow trench isolation from), and semiconductor device has better performance.
In the present embodiment, after step 8, also can comprise step 9: form gate lateral wall and source electrode and drain electrode.
So far, whole processing steps that method is implemented are according to an exemplary embodiment of the present invention completed, next, can complete by subsequent technique (such as forming interlayer dielectric layer, forming the step of contact hole and formation metal level etc.) making of whole semiconductor device, described subsequent technique is identical with traditional process for fabricating semiconductor device, repeats no more herein.
The manufacture method of the semiconductor device of the embodiment of the present invention, adopt and first formed shallow trench isolation from (STI), form again super shallow trench isolation and manufacture the transistor of raceway groove segmentation from the mode of (VSTI), avoid available technology adopting double-pattern (double patterning) technology easily to cause shallow trench isolation from (STI) and super shallow trench isolation from (VSTI) overlapping problem (overlayissue), improved the yield of semiconductor device.
And further, the embodiment of the present invention forms the second mask by DSA patterning technique, can guarantee that the homogeneous of the super shallow trench isolated groove of formation and the figure of strip pattern, with consistent, is conducive to improve the performance of semiconductor device.
With reference to Fig. 3, wherein show the flow chart of a kind of typical method in the manufacture method of semiconductor device that the present invention proposes, for schematically illustrating the flow process of whole manufacturing process.
Step S101: Semiconductor substrate is provided, forms hard mask in described Semiconductor substrate;
Step S102: in described hard mask and Semiconductor substrate, form shallow trench isolation from;
Step S103: form the second mask by the graphical technique of direct self assembly in Semiconductor substrate, utilize described the second mask to carry out etching to described Semiconductor substrate, form super shallow trench isolated groove and be positioned at the strip pattern of its both sides;
Step S104: in described super shallow trench isolated groove form super shallow trench isolation from.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment is the object for giving an example and illustrating just, but not is intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, can also make more kinds of variants and modifications according to instruction of the present invention, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (14)
1. a manufacture method for semiconductor device, is characterized in that, described method comprises the steps:
Step S101: Semiconductor substrate is provided, forms hard mask in described Semiconductor substrate;
Step S102: in described hard mask and Semiconductor substrate, form shallow trench isolation from;
Step S103: form the second mask by the graphical technique of direct self assembly in Semiconductor substrate, utilize described the second mask to carry out etching to described Semiconductor substrate, form super shallow trench isolated groove and be positioned at the strip pattern of its both sides;
Step S104: in described super shallow trench isolated groove form super shallow trench isolation from.
2. the manufacture method of semiconductor device as claimed in claim 1, is characterized in that, described step S102 comprises:
Step S1021: form shallow trench isolated groove in described hard mask and Semiconductor substrate;
Step S1022: in described shallow trench isolated groove, fill shallow trench isolated material and carry out CMP, with in described shallow trench isolated groove, form shallow trench isolation from.
3. the manufacture method of semiconductor device as claimed in claim 2, is characterized in that, described shallow trench isolated material is oxide.
4. the manufacture method of semiconductor device as claimed in claim 1, is characterized in that, described step S103 comprises:
Step S1031: remove described hard mask be positioned at described Semiconductor substrate intend forming super shallow trench isolation from the part in the region of strip pattern;
Step S1032: form patterned the second mask in the removed region of described hard mask by the graphical technique of direct self assembly;
Step S1033: utilize described the second mask to carry out etching to described Semiconductor substrate, form super shallow trench isolated groove and strip pattern in described Semiconductor substrate, wherein, described strip pattern is positioned at the both sides of described super shallow trench isolated groove.
5. the manufacture method of semiconductor device as claimed in claim 4, is characterized in that, removes the lithographic method adopting in the method for employing of described hard mask and step S1033 in step S1031, is dry etching.
6. the manufacture method of semiconductor device as claimed in claim 4, is characterized in that, in described step S1031, described plan form super shallow trench isolation from the region of strip pattern be active area.
7. the manufacture method of semiconductor device as claimed in claim 4, is characterized in that, described step S1032 comprises:
Step S10321: at the different amount Molecularly Imprinted Polymer of the removed area filling of described hard mask;
Step S10322: toast described different amount Molecularly Imprinted Polymer, to form patterned the second mask.
8. the manufacture method of semiconductor device as claimed in claim 1, is characterized in that, described step S104 comprises: in described super shallow trench isolated groove, fill super shallow trench isolated material carry out CMP, with form super shallow trench isolation from.
9. the manufacture method of semiconductor device as claimed in claim 8, is characterized in that, described super shallow trench isolated material is oxide.
10. the manufacture method of semiconductor device as claimed in claim 1, is characterized in that, the width of the described strip pattern forming in described step S103 is not less than the length of the grid of described semiconductor device.
The manufacture method of 11. semiconductor device as claimed in claim 1, is characterized in that, the thickness of the hard mask forming in step S101 is
The manufacture method of 12. semiconductor device as described in claim 1 to 11 any one, is characterized in that, also comprises step S105: in described Semiconductor substrate, form gate dielectric and grid after described step S104.
The manufacture method of 13. semiconductor device as claimed in claim 12, is characterized in that, described gate dielectric is only positioned at the top of described strip pattern.
The manufacture method of 14. semiconductor device as claimed in claim 12, is characterized in that, also comprises step S106 after described step S105: form gate lateral wall and source electrode and drain electrode.
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| CN1447444A (en) * | 2002-03-21 | 2003-10-08 | 旺宏电子股份有限公司 | Method for minimizing short channel effect of semiconductor devices and transistors |
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