CN103904017B - A kind of manufacture method of semiconductor devices - Google Patents
A kind of manufacture method of semiconductor devices Download PDFInfo
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- CN103904017B CN103904017B CN201210568208.4A CN201210568208A CN103904017B CN 103904017 B CN103904017 B CN 103904017B CN 201210568208 A CN201210568208 A CN 201210568208A CN 103904017 B CN103904017 B CN 103904017B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The present invention provides a kind of manufacture method of semiconductor devices, is related to technical field of semiconductors.This method includes：Step S101：Semiconductor substrate is provided, forms hard mask on the semiconductor substrate；Step S102：Shallow trench isolation is formed in the hard mask and Semiconductor substrate；Step S103：By forming the second mask on a semiconductor substrate directly from assembling patterning process, the Semiconductor substrate is performed etching using second mask, forms an ultra shallow trench isolations groove and the strip pattern positioned at its both sides；Step S104：An ultra shallow trench isolations are formed in an ultra shallow trench isolations groove.The manufacture method of the semiconductor devices of the present invention, isolate as a result of shallow trench is initially formed, the mode for re-forming an ultra shallow trench isolations manufactures the transistor of raceway groove segmentation, avoid and the problem of shallow trench isolation is overlapping with an ultra shallow trench isolations is easily caused using double-pattern technology, improve the yield of semiconductor devices.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of manufacture method of semiconductor devices.
Background technology
How short-channel effect is reduced（short channel effect）, it is the pass that process for fabrication of semiconductor device faces
One of key problem.In the prior art, the transistor being segmented by using raceway groove（SegFet）Make the technical side of semiconductor devices
Case, it may be employed to reduce one of very promising technology of short-channel effect of device.
In the prior art, the transistor being segmented using raceway groove（SegFet）Semiconductor devices structure it is as shown in Figure 1
（Fig. 1 is the sectional view along grid width direction）.The semiconductor devices includes Semiconductor substrate 100 and disposed thereon shallow
Trench isolations STI 101, grid 104, wherein channel region is by an ultra shallow trench isolations（Very Shallow Trench
Isolation, VSTI）102 are separated into multiple subsegments, Semiconductor substrate 100（Specifically, it is raceway groove part）Positioned at each two
Part between adjacent VSTI or between VSTI and STI is strip pattern（stripe）103.Wherein, point of strip pattern 103
Cloth determines that its width is influenceed by precision of manufacturing process by the position of shallow trench isolation 101 and an ultra shallow trench isolations 102.Due to
Channel region has been separated into multiple subsegments by VSTI, the transistor of raceway groove segmentation is formd, so the semiconductor devices is by short ditch
The influence of channel effect is smaller, i.e., this structure reduces the short-channel effect of device.Preferably reduce short channel effect to realize
The technique effect answered, it is necessary to form good strip pattern；Also, the width of the strip pattern formed is smaller, and manufacture is partly led
There is body device better threshold voltage to show.Therefore, in the manufacturing process of semiconductor devices, how strip pattern is formed,
It is to restrict one of an important factor for semiconductor devices manufactures.
At present, in the manufacturing process of semiconductor devices, the semiconductor devices one for the transistor that manufacture is segmented using raceway groove
As use double-pattern（double patterning）Technology, first etch and form strip pattern（Form VSTI）Shape is etched again
Into STI.However, this method easily causes STI and VSTI overlap problem（overlay issue）, which results in can not
Good strip pattern is formed, and then result in the bad of semiconductor devices.
Therefore, in order to solve the above problems, it is necessary to propose a kind of manufacture method of new semiconductor devices.
The content of the invention
In view of the shortcomings of the prior art, the present invention provides a kind of manufacture method of semiconductor devices, and this method includes：
Step S101：Semiconductor substrate is provided, forms hard mask on the semiconductor substrate；
Step S102：Shallow trench isolation is formed in the hard mask and Semiconductor substrate；
Step S103：By forming the second mask on a semiconductor substrate directly from assembling patterning process, using described
Second mask performs etching to the Semiconductor substrate, forms an ultra shallow trench isolations groove and the bar graph positioned at its both sides
Case；
Step S104：An ultra shallow trench isolations are formed in an ultra shallow trench isolations groove.
Further, the step S102 includes：
Step S1021：Shallow trench isolated groove is formed in the hard mask and Semiconductor substrate；
Step S1022：Shallow trench isolated material is filled in the shallow trench isolated groove and carries out CMP, with described
Shallow trench isolation is formed in shallow trench isolated groove.
Wherein, the shallow trench isolated material is oxide.
Further, the step S103 includes：
Step S1031：Remove the hard mask and be located at the Semiconductor substrate and intend forming an ultra shallow trench isolations and bar graph
The part in the region of case；
Step S1032：By being formed graphically in the region that the hard mask is removed directly from assembling patterning process
The second mask；
Step S1033：The Semiconductor substrate is performed etching using second mask, on the semiconductor substrate
An ultra shallow trench isolations groove and strip pattern are formed, wherein, the strip pattern is located at the two of an ultra shallow trench isolations groove
Side.
Wherein, the etching employed in the method and step S1033 of the use of the hard mask is removed in step S1031
Method, it is dry etching.
Wherein, in the step S1031, the region that the plan forms an ultra shallow trench isolations and strip pattern is active
Area.
Wherein, the step S1032 includes：
Step S10321：In the different amount Molecularly Imprinted Polymer of area filling that the hard mask is removed；
Step S10322：The different amount Molecularly Imprinted Polymer is toasted, to form patterned second mask.
Further, the step S104 includes：An ultra shallow trench isolations material is filled in an ultra shallow trench isolations groove
Expect and carry out CMP, to form an ultra shallow trench isolations.
Wherein, an ultra shallow trench isolation is oxide.
Wherein, the width of the strip pattern formed in the step S103 is not less than the grid of the semiconductor devices
The length of pole.Wherein, the thickness of the hard mask formed in step S101 is
Further, step S105 is also included after the step S104：Grid is formed on the semiconductor substrate
Dielectric layer and grid.
Wherein, the gate dielectric is only located at the top of the strip pattern.
Further, step S106 is also included after the step S105：Form gate lateral wall and source electrode and drain electrode.
The manufacture method of the semiconductor devices of the present invention, isolate as a result of shallow trench is initially formed（STI）, re-form super
Shallow trench is isolated（VSTI）Mode manufacture raceway groove segmentation transistor, avoid and use double-pattern in the prior art
（double patterning）Technology easily causes shallow trench isolation（STI）With an ultra shallow trench isolations（VSTI）The problem of overlapping
（overlayissue）, improve the yield of semiconductor devices.
Brief description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, for explaining the principle of the present invention.
In accompanying drawing：
Fig. 1 is the schematic cross sectional view along grid width direction of the semiconductor devices of prior art；
Fig. 2A-Fig. 2 H are schematically cuing open for the figure that each step of manufacture method of semiconductor devices proposed by the present invention is formed
Face figure（Along grid width direction）；
Fig. 3 is a kind of flow chart of the manufacture method of semiconductor devices proposed by the present invention.
Embodiment
In the following description, a large amount of concrete details are given to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention can be able to without one or more of these details
Implement.In other examples, in order to avoid obscuring with the present invention, do not enter for some technical characteristics well known in the art
Row description.
It should be appreciated that the present invention can be implemented in different forms, and it should not be construed as being limited to what is proposed here
Embodiment.On the contrary, providing these embodiments disclosure will be made thoroughly and complete, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in Ceng He areas may be exaggerated.From beginning to end
Same reference numerals represent identical element.
It should be understood that when element or layer be referred to as " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " it is other
When element or layer, its can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
Person may have element or layer between two parties.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " directly
It is connected to " or when " being directly coupled to " other elements or layer, then element or layer between two parties is not present.It should be understood that although it can make
Various elements, part, area, floor and/or part are described with term first, second, third, etc., these elements, part, area, floor and/
Or part should not be limited by these terms.These terms be used merely to distinguish an element, part, area, floor or part with it is another
One element, part, area, floor or part.Therefore, do not depart from present invention teach that under, the first element discussed below, portion
Part, area, floor or part are represented by the second element, part, area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... under ", " ... it
On ", " above " etc., herein can for convenience description and by using so as to describe an element shown in figure or feature with
The relation of other elements or feature.It should be understood that in addition to the orientation shown in figure, spatial relationship term is intended to also include making
With the different orientation with the device in operation.For example, if the device upset in accompanying drawing, then, is described as " under other elements
Face " or " under it " or " under it " element or feature will be oriented to other elements or feature " on ".Therefore, exemplary art
Language " ... below " and " ... under " it may include upper and lower two orientations.Device can additionally be orientated (be rotated by 90 ° or its
It is orientated) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as the limitation of the present invention.Make herein
Used time, " one " of singulative, "one" and " described/should " be also intended to include plural form, unless context is expressly noted that separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when in the specifications in use, determining the feature, whole
Number, step, operation, the presence of element and/or part, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of element, part and/or group.Herein in use, term "and/or" includes any and institute of related Listed Items
There is combination.
Describe to send out herein with reference to the cross-sectional view of the schematic diagram of the desirable embodiment (and intermediate structure) as the present invention
Bright embodiment.As a result, it is contemplated that due to caused by such as manufacturing technology and/or tolerance from the change of shown shape.Therefore,
Embodiments of the invention should not necessarily be limited to the given shape in area shown here, but including due to for example manufacturing caused shape
Shape deviation.For example, it is shown as that the injection region of rectangle generally has circle at its edge or bending features and/or implantation concentration ladder
Degree, rather than the binary change from injection region to non-injection regions.Equally, the disposal area can be caused by injecting the disposal area formed
Some injections in area between the surface passed through during injection progress.Therefore, the area shown in figure is substantially schematic
, their shape is not intended the true form in the area of display device and is not intended to limit the scope of the present invention.
Unless otherwise defined, all terms (including technology and scientific terminology) as used herein have and field of the present invention
The identical implication that those of ordinary skill is generally understood that.It will also be understood that the term defined in such as commonly used dictionary
It should be understood to the implication consistent with their implications in the environment of association area and/or this specifications, and can not be
Explained in the sense that preferably or excessively formal, unless expressly so definition here.
In order to thoroughly understand the present invention, detailed step and detailed structure will be proposed in following description, so as to
Explain the manufacture method of semiconductor devices proposed by the present invention.Presently preferred embodiments of the present invention is described in detail as follows, but except
Outside these are described in detail, the present invention can also have other embodiment.
Below, reference picture 2A- Fig. 2 H and Fig. 3, show to describe the manufacture method one of semiconductor devices proposed by the present invention
The detailed step of example property method.Wherein, Fig. 2A-Fig. 2 H are that each step of manufacture method of semiconductor devices proposed by the present invention is formed
Figure schematic cross sectional view（Along grid width direction）；Fig. 3 is a kind of manufacturer of semiconductor devices proposed by the present invention
The flow chart of method.
The manufacture method of the semiconductor devices of the embodiment of the present invention, comprises the following steps：
Step 1：Semi-conductive substrate 200 is provided, hard mask 201, the figure of formation are formed in the Semiconductor substrate 200
Shape is as shown in Figure 2 A.Wherein, the thickness of hard mask 201 is
As an example, in the present embodiment, the Semiconductor substrate 200 is formed from single crystal silicon material.
Step 2：Shallow trench isolated groove is formed on hard mask 201 and Semiconductor substrate 200（STI trench）202,
The figure of formation is as shown in Figure 2 B.
Wherein, shallow trench isolated groove, refers to the groove for forming shallow trench isolation, i.e. shallow trench isolation will be formed in
In the groove.Exemplary, the method for forming trench isolations groove 202, Ke Yiwei：Hard mask 201 is etched to intend forming shallow ridges
The position of groove isolation forms opening；Then by the use of the hard mask 201 of the formation opening as mask etching Semiconductor substrate 200,
To form trench isolations groove 202 in Semiconductor substrate 200.
Step 3：Shallow trench isolation is formed in shallow trench isolated groove 202（STI）203, figure such as Fig. 2 C institutes of formation
Show.
Exemplary, this step may include following steps：
Step 301, with shallow trench isolated material fill the shallow trench isolated groove 202；
Step 302, CMP is carried out to the Semiconductor substrate 200, remove unnecessary shallow trench isolated material.That is, remove shallow
Trench isolation is higher than the part of hard mask 201.
Wherein, shallow trench isolated material can be oxide（Silica）Or other suitable materials.In the present embodiment,
When removing unnecessary shallow trench isolated material, hard mask 201 can also be removed a part.
Step 4：Selective removal is carried out to hard mask 201, hard mask 201 is removed and is located in Semiconductor substrate 200 and intend shape
Into an ultra shallow trench isolations and the part in the region of strip pattern, the figure of formation is as shown in Figure 2 D.
Wherein, hard mask 201, which is located at, intends the region for forming an ultra shallow trench isolations and strip pattern in Semiconductor substrate 200
Part, typically it is exactly part of the hard mask 201 between two adjacent STI, as shown in Figure 2 D.In the present embodiment, half
Intend being formed the region of an ultra shallow trench isolations and strip pattern on conductor substrate 200, preferably comprise whole active area（AA areas）.When
When whole active area is respectively formed strip pattern, the effect that can be segmented the raceway groove of transistor is more preferable, further improves device
Performance.
Method used by hard mask 201 is removed, can be dry etching.
Step 5：By directly from assembling patterning process（Directed Self-assemblypatterning, DSA
patterning）The region that hard mask 201 is removed on semiconductor substrate 200 forms patterned second mask 204.Its
In, the open area 2041 of the second mask 204 corresponds to the position that form an ultra shallow trench isolations groove, and the second mask 204 removes
Region outside open area 2041 corresponds to the region that form strip pattern.The figure of formation, as shown in Figure 2 E.
Wherein, specifically, with directly from assembling patterning process（DSA patterning）Patterned second is formed to cover
The method of film 204 comprises the following steps：
The appropriate different amount Molecularly Imprinted Polymer of step 501, the area filling being removed in hard mask 201（copolymer）；
Step 502, baking（bake）The different amount Molecularly Imprinted Polymer, to form patterned second mask 204.
Generally, the mask formed by DSA patterning techniques has identical figure and spacing, therefore, use this
Mode forms the second mask 204, it is ensured that an ultra shallow trench isolations groove and the figure of strip pattern that subsequent etching is formed
It is homogeneous with it is consistent, be advantageous to improve semiconductor devices performance.Also, DSA patterning techniques can realize precision more
High is graphical, makes the width for the strip pattern to be formed smaller, and then ensures that the semiconductor devices of manufacture has more preferable threshold value
Voltage shows.
Step 6：Using the etch semiconductor substrates 200 of the second mask 204, an ultra shallow is formed in the Semiconductor substrate 200
Trench isolations groove（VSTI trench）205 and strip pattern 205 '.Wherein, strip pattern 205 ' is located at an ultra shallow trench isolations
The both sides of groove, i.e. strip pattern 205 ' are between adjacent an ultra shallow trench isolations or adjacent an ultra shallow trench isolations are with before
Between trench isolations.The figure of formation, as shown in Figure 2 F.
Wherein, an ultra shallow trench isolations groove（VSTI trench）, refer to be used to form an ultra shallow trench isolations（VSTI）Ditch
The isolation of groove, i.e. shallow trench will be formed in the groove.
Wherein, the method for etching the Semiconductor substrate 200, using dry etching.
Preferably, the number of the strip pattern 205 ' of formation is multiple（multi-stripes）, and its width is equal, and
Spacing between adjacent strip pattern 205 ' is equal（That is the width of VSTI trench205 is equal）.This can be designed so that
The segmentation of the raceway groove of semiconductor devices ensures that semiconductor devices has more preferable electrology characteristic than more uniform.
Wherein, it is further preferred that the width of strip pattern 205 ' is more than or equal to（It is not less than）The grid to be formed
Length.
Step 7：An ultra shallow trench isolations are formed in an ultra shallow trench isolations groove 205（VSTI）206, the figure of formation is as schemed
Shown in 2G.
Exemplary, this step may include following steps：
Step 701, with an ultra shallow trench isolation fill an ultra shallow trench isolations groove 205；
Step 702, CMP is carried out to the Semiconductor substrate 200, remove unnecessary an ultra shallow trench isolation, to be formed
An ultra shallow trench isolations 206.That is, the part that shallow trench isolated material is higher than Semiconductor substrate 200 is removed.
Wherein, an ultra shallow trench isolation can be oxide（Silica）Or other suitable materials.In the present embodiment
In, when removing unnecessary an ultra shallow trench isolation, Semiconductor substrate 200 can also be removed a part.
Step 8：Gate dielectric 207 and grid 208, figure such as Fig. 2 H institutes of formation are formed on semiconductor substrate 200
Show.
Wherein, it is preferred that the gate dielectric 207 of formation is only located at the top of strip pattern 205 ', as illustrated in figure 2h.This
One structure covers whole Semiconductor substrate with gate dielectric（Cover an ultra shallow trench isolations simultaneously）Compare, semiconductor devices tool
There is better performance.
In the present embodiment, after step 8, it may also include step 9：Form gate lateral wall and source electrode and drain electrode.
So far, whole processing steps that method according to an exemplary embodiment of the present invention is implemented are completed, next, can be with
Pass through subsequent technique（Such as the step of forming interlayer dielectric layer, forming contact hole and form metal level etc.）Complete whole semiconductor
The making of device, the subsequent technique is identical with traditional process for fabricating semiconductor device, and here is omitted.
The manufacture method of the semiconductor devices of the embodiment of the present invention, employ and be initially formed shallow trench isolation（STI）, re-form
An ultra shallow trench isolations（VSTI）Mode manufacture raceway groove segmentation transistor, avoid and use double-pattern in the prior art
（double patterning）Technology easily causes shallow trench isolation（STI）With an ultra shallow trench isolations（VSTI）The problem of overlapping
（overlayissue）, improve the yield of semiconductor devices.
Also, further, the embodiment of the present invention forms the second mask by DSA patterning techniques, it is ensured that
An ultra shallow trench isolations groove of formation and the figure of strip pattern it is homogeneous with it is consistent, be advantageous to improve the property of semiconductor devices
Energy.
Reference picture 3, it illustrated therein is a kind of typical method in the manufacture method of semiconductor devices proposed by the present invention
Flow chart, for schematically illustrating the flow of whole manufacturing process.
Step S101：Semiconductor substrate is provided, forms hard mask on the semiconductor substrate；
Step S102：Shallow trench isolation is formed in the hard mask and Semiconductor substrate；
Step S103：By forming the second mask on a semiconductor substrate directly from assembling patterning process, using described
Second mask performs etching to the Semiconductor substrate, forms an ultra shallow trench isolations groove and the bar graph positioned at its both sides
Case；
Step S104：An ultra shallow trench isolations are formed in an ultra shallow trench isolations groove.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
Citing and the purpose of explanation, and be not intended to limit the invention in described scope of embodiments.In addition people in the art
Member can also make more kinds of it is understood that the invention is not limited in above-described embodiment according to the teachings of the present invention
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (13)
1. a kind of manufacture method of the transistor of raceway groove segmentation, it is characterised in that methods described comprises the following steps：
Step S101：Semiconductor substrate is provided, forms hard mask on the semiconductor substrate；
Step S102：Shallow trench isolation is formed in the hard mask and Semiconductor substrate；
Step S103：Remove the hard mask and be located at the area that the Semiconductor substrate intends being formed an ultra shallow trench isolations and strip pattern
The part in domain, covered by forming patterned second in the region that the hard mask is removed directly from assembling patterning process
Film, the Semiconductor substrate is performed etching using second mask, to form an ultra shallow groove in the Semiconductor substrate
Isolated groove and strip pattern, wherein, the strip pattern is located at the both sides of an ultra shallow trench isolations groove；
Step S104：An ultra shallow trench isolations are formed in an ultra shallow trench isolations groove.
2. manufacture method as claimed in claim 1, it is characterised in that the step S102 includes：
Step S1021：Shallow trench isolated groove is formed in the hard mask and Semiconductor substrate；
Step S1022：Shallow trench isolated material is filled in the shallow trench isolated groove and carries out CMP, with the shallow ridges
Shallow trench isolation is formed in groove isolated groove.
3. manufacture method as claimed in claim 2, it is characterised in that the shallow trench isolated material is oxide.
4. manufacture method as claimed in claim 1, it is characterised in that remove method and the utilization of the use of the hard mask
Second mask performs etching used lithographic method to the Semiconductor substrate, is dry etching.
5. manufacture method as claimed in claim 1, it is characterised in that the plan forms an ultra shallow trench isolations and strip pattern
Region is active area.
6. manufacture method as claimed in claim 1, it is characterised in that it is described by directly from assembling patterning process described
The region that hard mask is removed, which forms patterned second mask, to be included：
In the different amount Molecularly Imprinted Polymer of area filling that the hard mask is removed；
The different amount Molecularly Imprinted Polymer is toasted, to form patterned second mask.
7. manufacture method as claimed in claim 1, it is characterised in that the step S104 includes：An ultra shallow groove every
From filling an ultra shallow trench isolation in groove and carrying out CMP, to form an ultra shallow trench isolations.
8. manufacture method as claimed in claim 7, it is characterised in that an ultra shallow trench isolation is oxide.
9. manufacture method as claimed in claim 1, it is characterised in that the strip pattern formed in the step S103
Width not less than the semiconductor devices grid length.
10. manufacture method as claimed in claim 1, it is characterised in that the thickness of the hard mask formed in step S101
For
11. the manufacture method as described in any one of claim 1 to 10, it is characterised in that also wrapped after the step S104
Include step S105：Gate dielectric and grid are formed on the semiconductor substrate.
12. manufacture method as claimed in claim 11, it is characterised in that the gate dielectric is only located at the strip pattern
Top.
13. manufacture method as claimed in claim 11, it is characterised in that also include step after the step S105
S106：Form gate lateral wall and source electrode and drain electrode.
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| CN201210568208.4A CN103904017B (en) | 2012-12-24 | 2012-12-24 | A kind of manufacture method of semiconductor devices |
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| CN201210568208.4A CN103904017B (en) | 2012-12-24 | 2012-12-24 | A kind of manufacture method of semiconductor devices |
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| CN1447444A (en) * | 2002-03-21 | 2003-10-08 | 旺宏电子股份有限公司 | Method for minimizing short channel effect of semiconductor devices and transistors |
| CN1501470A (en) * | 2002-11-15 | 2004-06-02 | 矽统科技股份有限公司 | Method for forming shallow groove spacer between semiconductor bases |
| CN101165874A (en) * | 2006-10-19 | 2008-04-23 | 国际商业机器公司 | Sub-lithographic nano interconnect structures, and method for forming same |
| CN101697352A (en) * | 2009-10-30 | 2010-04-21 | 上海宏力半导体制造有限公司 | Multi-point insulated silicon transistor with double ultra sallow isolation structures |
| CN101740393A (en) * | 2008-11-27 | 2010-06-16 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacture method thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070090484A1 (en) * | 2005-08-25 | 2007-04-26 | Chartered Semiconductor Manufacturing, Ltd. | Integrated circuit stress control system |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1447444A (en) * | 2002-03-21 | 2003-10-08 | 旺宏电子股份有限公司 | Method for minimizing short channel effect of semiconductor devices and transistors |
| CN1501470A (en) * | 2002-11-15 | 2004-06-02 | 矽统科技股份有限公司 | Method for forming shallow groove spacer between semiconductor bases |
| CN101165874A (en) * | 2006-10-19 | 2008-04-23 | 国际商业机器公司 | Sub-lithographic nano interconnect structures, and method for forming same |
| CN101740393A (en) * | 2008-11-27 | 2010-06-16 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacture method thereof |
| CN101697352A (en) * | 2009-10-30 | 2010-04-21 | 上海宏力半导体制造有限公司 | Multi-point insulated silicon transistor with double ultra sallow isolation structures |
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| CN103904017A (en) | 2014-07-02 |
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