CN1353522A - Signaling No.7 analyzer - Google Patents
Signaling No.7 analyzer Download PDFInfo
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- CN1353522A CN1353522A CN 00127444 CN00127444A CN1353522A CN 1353522 A CN1353522 A CN 1353522A CN 00127444 CN00127444 CN 00127444 CN 00127444 A CN00127444 A CN 00127444A CN 1353522 A CN1353522 A CN 1353522A
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Abstract
A No.7 signaling analyzer has an open structure composed of ISA card module and PC host for high scalability. The ISA card module has an information exchange channel connected between PC host and data collector, the data collector connected between the information exchange channel and an E1 basic interface circuit, the E1 basic interface circuit connected to I/O relay lines for receiving signaling data, and a logic controller.
Description
The present invention relates to a kind of electrical measurement analytical equipment, especially a kind of real-time collection, Signaling System Number 7 analyzer of analysis switch interoffice Signaling System Number 7 data of being used for.It also is applicable to any multichannel big data quantity real-time data acquisition, analytical system.
In the modern communication net, each programme-controlled exchange and transmission equipment are set up the interconnection of information in order to carry out information exchange, send and receive various signalings, and various signaling systems are also just arisen at the historic moment.Wherein, No.7 signalling system is the common channel signal technology that is suitable for adopting in digital communication network most.At present, most of stored-program control exchange all adopts Signaling System Number 7 to carry out the interoffice information exchange.The signaling transmission duplex channel that signaling data link is made up of two data channels, these two Channel Transmission directions are opposite, adopt the digital channel of 64KB/S under digital environment usually.Usually there are many signaling data links at interoffice.Yet the transmission of signaling in data link often makes a mistake owing to the imperfection of transmission equipment and the interference in the data link.For avoiding the generation of error code, improve transmission quality, need carry out monitoring analysis to signaling data, to guarantee to set up normal connection.
Task of the present invention provides a kind of Signaling System Number 7 analyzer, it can carry out the signaling data collection at a high speed, easily, and upload, carry out analyzing and processing, and can on capacity, be easy to expansion, also simpler on the structure, on forming and dispose, system can provide the plurality of optional mode according to user's requirement.
For solving above-mentioned task, solution of the present invention is: the Open architecture that this Signaling System Number 7 analyzer adopts ISA module card and portable main frame to form, wherein the ISA module card comprises
Information exchanging channel: be connected between PC main frame and the data acquisition unit, it comprises a Double Port Random Memory DPRAM, is used for PC main frame and data acquisition unit exchange of control information; A push-up storage FIFO is used for large-scale data transmission between PC main frame and the digital processing unit;
Data acquisition unit: be connected between information exchanging channel and the E1 basic interface circuit, receive test command, the test parameter of PC main frame; Receive the signaling data that E1 basic interface circuit transmits, be sent to information exchanging channel;
E1 basic interface circuit: link to each other with measured incoming trunk line, receive signaling data;
Logic controller;
During system works, the PC main frame is by information exchanging channel Double Port Random Memory DPRAM, the working procedure that will be arranged in the signaling data on the test trunk of main frame writes data acquisition unit, data acquisition unit poll multichannel E1 interface circuit then, signaling data on the trunk line is entered in the data acquisition unit by the E1 interface circuit, deposit in the data buffer zone, after finishing poll, data acquisition unit is pressed into push-up storage FIFO with buffer data, enter the PC main frame, among the change Double Port Random Memory DPRAM among the controlled flag notice PC main frame push-up storage FIFO Frame get ready, and data length enters next poll then.
Because the structure that the present invention has adopted PC main frame, information exchanging channel, data acquisition unit, E1 basic interface circuit to be linked in sequence makes system can realize carrying out the signaling data collection at a high speed, easily, and uploads, carries out the function of analyzing and processing; Because the present invention is placed on the part of the integrated circuit beyond the PC main frame in the ISA module card, form the Open architecture that ISA module card and portable main frame are formed, the system that makes is easy to expansion on capacity, also simpler on the structure, on forming and dispose, system can provide the plurality of optional mode according to user's requirement.
Below in conjunction with drawings and Examples the present invention program is described in more detail.
Fig. 1 is a design frame chart of the present invention.
Fig. 2 is 8 module map of EPLD logical construction of the present invention.
Shown in Fig. 1 design frame chart of the present invention, the present invention includes PC main frame and ISA module card.Wherein the PC main frame is used for receiving configuration information, by information exchanging channel control ISA plug-in card; Receive the storage data, analyze data.Whole test system needs a PC host computer control.The PC main frame is made the master cpu of system, operates on Windows ' 95 operating systems.But a PC full configuration is put 4 test modules, monitors 8 pairs of 16 PCM links simultaneously, and the PC main frame can be selected according to system's needs.
The ISA module card comprises information exchanging channel, data acquisition unit, E1 basic interface circuit, logic controller, clock power.
1. information exchanging channel: for PC main frame and data acquisition unit provide control information and data information exchange mode.
Push-up storage FIFO, Double Port Random Memory DPRAM, isa bus configuration information interchange channel.In the information exchanging channel, Double Port Random Memory DPRAM is used for PC main frame and data acquisition unit exchange of control information, and push-up storage FIFO is used for large-scale data transmission between PC main frame and the digital processing unit.Accomplish that like this control information separates with data message.The outstanding advantage of push-up storage FIFO is that the reading and writing data manipulation is simple, quick, need not change memory unit address.In our instrument, adopt this mode, the lot of data collection, transmit this mode of evidence not only efficiently but also reliable.Adopting the capacity of IDT company selecting for use of push-up storage FIFO is the IDT7204 of 4K, and each module only need dispose a slice IDT7204.Double Port Random Memory RAM is as the communication device between PC main frame and the data acquisition unit.Except that signaling data transmitted by push-up storage FIFO, the transmission of other test command, test parameter, test result and software protocol etc. all pass through Double Port Random Memory RAM to be realized.Adopting IDT company capacity is the IDT7132 of 2K.Each block configuration a slice IDT7132.
2. data acquisition unit: operation basic interface circuit obtains image data.And transmit data to the PC main frame by information exchanging channel.
Data acquisition unit adopts the TMS320C5X series of high speed microprocessor based on digital signal processor DSP of 16 buses.This processor host frequency 40M, basic configuration has the 64K program storage area, the 96K data storage area.Nearly abundant I/O mouth and a plurality of inside and outside maskable interrupts and the high speed serial port of 64K can be provided.This microprocessor provides direct memory visit dma mode simultaneously.And have special data buffer zone to set up instruction, can in RAM, set up the data buffer zone that width is 32K.Digital signal processor has independently program and data space, flexible configuration, and working procedure can be carried out in ram in slice, to obtain the maximum speed of service.The major function of data acquisition unit is to communicate acceptance test order, test parameter with the PC main frame; Control E1 basic interface circuit is finished transmitting-receiving, filtration, the buffer memory of signaling data and the functions such as signaling data that receive to the transmission of PC main frame.Each block configuration a slice TMS320C5X.RAM recommends to use CY7C199, and ROM recommends to use AM27C1024, also can use other EPROM to replace.
3.E1 basic interface circuit, isolating coupler constitute the basic interface circuit.
Configuration 4 road E1 basic interface circuit on each test module, the supervision of respectively corresponding 4 links.E1 basic interface unit is between digital exchange system and the digital exchange system or the interface unit between digital exchange system and the digital transmission system, its effect is according to the PCM time division multiplexing principle, voice signal and the signaling of 32 road 64KB/S are multiplexed to the transmission of 2048KB/S signal, receive 2048KB/S speech and signaling-information that the opposite end sends simultaneously.E1 basic interface unit possesses following basic function;
Code conversion: the signal in transmission not in the know is that HDB3 three rank high density are extremely given birth to sign indicating number or AMI pseudoternary code, and intra-office carries out adopting when switched connection is handled the NRZ nonreturn to zero code.The digital junction unit changes Incoming HDB3 sign indicating number into the NRZ sign indicating number, intra-office NRZ sign indicating number is converted to the HDB3 sign indicating number sends.
Clock Extraction with more regularly: from the data flow of input, extract reference clock, and as the external reference clock source of local terminal system clock as input traffic.
Frame/multi-frame is synchronous: at receiving terminal, from the input pcm stream, extract the frame alignment signal of input signal, produce the time-gap pulsing on each road of receiving end again, it is alignd from each road of TS0 with the frame slot pulse of making a start, the signal that sends so that make a start can correctly be received termination and receive, and promptly achieve frame is synchronous.If under channel associated signaling, to realize that also multi-frame is synchronous.
Control, detection, alarm: control comprises the initialization of interface circuit; Orders such as execution resets, go-and-return test.Detecting content has the error rate, slip number of times, OOF, multiframe out-of-sync., repeating signal to lose etc.Alarm promptly sends out detected fault message by certain way, make faulty indication, transmit relevant warning information.
On system realized, E1 basic interface circuit adopted the digital junction large scale integrated chip (LSI chip) BT8370 of BT company.BT8370 has the parallel port, can be directly by digital signal processor DSP visit, control.BT8370 has a fairly large number of status register, can show the generation of various anomalous events, can handle accordingly after the digital signal processor DSP inquiry.BT8370 provides various self-looped testing functions, convenient debugging and test.Simultaneously, it has powerful High-Level Data Link Control HDLC function and well behaved inner phase-locked loop, can save phase-locked loop circuit, reduces cost.Digital signal processor DSP can directly be visited BT8370, finishes the reception of signaling data and sends out.
4. logic controller: produce the needed logic of data acquisition unit.
The EPLD programmable logic device constitutes logic controller.Adopt the EPLD programmable logic device to produce required various control logics and sequential circuit, comprise the sheet choosing of chips such as digital signal processor DSP, BT8370 and the generation of various sequential.The EPLD programmable logic device adopts the EPM7128S of ALTERA company.Each block configuration a slice EPM7128S.
The EPLD design comprises 8 modules, produces needed all signals of each chip respectively, as shown in Figure 2.The concrete signal of 8 modules and decipher as follows:
The generation of module 1:PC machine I/O mouth gating signal
10 address signal SA0, SA1------SA9 of PC and address allow signal SAEN to produce gating signal SIO0, SIO1, the SIO2 of I/O mouth after deciphering.
The generation of module 2:E1 interface gating signal
7 address signal CA9, the CA10------CA15 of TMS320C50 and data strobe signal CDS produce chip selection signal E1CS1, E1CS2, E1CS3, the E1CS4 of E1 interface chip after deciphering.
The generation of module 3:PC machine end dual port RAM chip selection signal
10 address signal SA11, SA12------SA19 of PC, internal memory read signal SRD, internal memory write signal SWR and address allow signal SAEN to produce the chip selection signal SDPCS of PC end dual port RAM after deciphering.
The machine-readable generation of writing direction signal of module 4:PC
The internal memory read signal SRD of PC, internal memory write signal SWR, I/O mouth read signal SIOR and I/O mouth write signal SIOW produce PC read-write direction signal MR/W after deciphering.
The generation that module 5:PC machine visit peripheral hardware is prepared number good signal
The dual port RAM gating signal SDPCS of PC end and busy signal SDPBS produce the preparation number good signal SRDY of PC visit peripheral hardware after deciphering.
The generation of module 6:TMS320C50 end dual port RAM chip selection signal
5 address signal CA11, the CA12------CA15 of TMS320C50 and data strobe signal CDS produce the chip selection signal CDPCS of TMS320C50 end dual port RAM.
The generation of module 7:E1 interface latch signal
The read signal CRD of TMS320C50 and write signal CWR produce the latch signal ASDS of E1 interface after deciphering.
The generation of module 8:245 chip GATE signal
PC end I/O mouth gating signal and dual port RAM gating signal produce the GATE signal of 245 chips after deciphering.
5. clock power: provide power supply, data acquisition controller and basic interface circuits needed clock.The data acquisition unit working method:
After system powers on, TMS320C5X starts ROM and goes up boot, cooperate with the PC main frame by information exchanging channel Double Port Random Memory DPRAM, to be positioned at working procedure (the TMS320C5X operation E1 interface circuit of main frame, obtain the program of signaling data on the measured incoming trunk line) write in the TMS320C5X ram in slice, withdraw from boot then, change in the TMS320C5X sheet and move working procedure, poll multichannel E1 interface circuit, obtain signaling data, data encapsulation is become to have to obtain E1 interface circuit label, and the acquisition time Frame of (Millisecond) deposits in the data buffer zone.After finishing poll, buffer data is pressed into push-up storage FIFO, among the change Double Port Random Memory DPRAM among the controlled flag notice PC main frame push-up storage FIFO Frame get and data length among the push-up storage FIFO ready.Enter next poll then.PC host work mode:
After entering system,, wait for that recording controller enters the program download state by logic controller reseting data collector.To be positioned at local data acquisition unit working procedure by Double Port Random Memory DPRAM downloads.Push-up storage FIFO information among the inquiry Double Port Random Memory DPRAM is read signaling data among the push-up storage FIFO.Deposit file in or do further processing.
Adopt this programme, energy is accurate and system under test (SUT) is synchronous on clock, provides buffer memory effectively and rapidly to collecting signaling data, guarantees that signaling data receives reliably, transmits.
Claims (11)
1, a kind of Signaling System Number 7 analyzer, the Open architecture that it adopts ISA module card and PC main frame to form, wherein the ISA module card comprises
Information exchanging channel: be connected between PC main frame and the data acquisition unit, it comprises a Double Port Random Memory DPRAM, is used for PC main frame and data acquisition unit exchange of control information; A push-up storage FIFO is used for large-scale data transmission between PC main frame and the digital processing unit;
Data acquisition unit: be connected between information exchanging channel and the E1 basic interface circuit, receive test command, the test parameter of PC main frame; Receive the signaling data that E1 basic interface circuit transmits, be sent to information exchanging channel;
E1 basic interface circuit: link to each other with measured incoming trunk line, receive signaling data;
Logic controller,
During system works, the PC main frame is by information exchanging channel Double Port Random Memory DPRAM, the working procedure that will be arranged in the signaling data on the test trunk of main frame writes data acquisition unit, data acquisition unit poll multichannel E1 interface circuit then, signaling data on the trunk line is entered in the data acquisition unit by the E1 interface circuit, deposit in the data buffer zone, after finishing poll, data acquisition unit is pressed into push-up storage FIFO with buffer data, enter the PC main frame, among the change Double Port Random Memory DPRAM among the controlled flag notice PC main frame push-up storage FIFO Frame get ready, and data length enters next poll then.
2, Signaling System Number 7 analyzer according to claim 1 is characterized in that: dispose 4 these ISA module cards on the PC main frame of this Signaling System Number 7 analyzer.
3, Signaling System Number 7 analyzer according to claim 1 is characterized in that: this push-up storage FIFO is that the IDT7204 of 4K forms by a slice capacity.
4, Signaling System Number 7 analyzer according to claim 1 is characterized in that: this Double Port Random Memory DPRAM is that the IDT7132 of 2K forms by a slice capacity.
5, Signaling System Number 7 analyzer according to claim 1 is characterized in that: this data acquisition unit is made up of the TMS320C5X series of high speed microprocessor based on digital signal processor DSP of 16 buses.
6, Signaling System Number 7 analyzer according to claim 5 is characterized in that: this data acquisition unit sheet contains random access memory ram that adopts CY7C199 and the read only memory ROM that adopts AM27C1024.
7, Signaling System Number 7 analyzer according to claim 1 is characterized in that: this ISA module card disposes 4 E1 basic interface circuit.
8, Signaling System Number 7 analyzer according to claim 1 is characterized in that: this E1 basic interface circuit adopts the digital junction large scale integrated chip (LSI chip) BT8370 of BT company.
9, Signaling System Number 7 analyzer according to claim 1, it is characterized in that: this logic controller is made of the EPLD programmable logic device.
10, Signaling System Number 7 analyzer according to claim 9 is characterized in that: this EPLD programmable logic device is that the EPM7128S by ALTERA company constitutes.
11, Signaling System Number 7 analyzer according to claim 1 is characterized in that: it also comprises a clock circuit that is used to provide power supply, data acquisition controller and basic interface circuits needed clock are provided.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB001274449A CN1140976C (en) | 2000-11-13 | 2000-11-13 | Signaling No.7 analyzer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB001274449A CN1140976C (en) | 2000-11-13 | 2000-11-13 | Signaling No.7 analyzer |
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| CN1353522A true CN1353522A (en) | 2002-06-12 |
| CN1140976C CN1140976C (en) | 2004-03-03 |
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| CNB001274449A Expired - Fee Related CN1140976C (en) | 2000-11-13 | 2000-11-13 | Signaling No.7 analyzer |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100342747C (en) * | 2004-06-28 | 2007-10-10 | 普天信息技术研究院 | Method for detecting signalling server load |
| CN100356727C (en) * | 2003-03-19 | 2007-12-19 | 华为技术有限公司 | Method for analysing signalling |
| CN100444561C (en) * | 2005-08-29 | 2008-12-17 | 中兴通讯股份有限公司 | Signal collecting module with exchanging convergence function |
| CN102647238A (en) * | 2012-03-21 | 2012-08-22 | 深圳市友讯达科技发展有限公司 | Telecom energy and frame protocol testing system of information collection wireless downlink channel module |
| CN102867445A (en) * | 2012-09-12 | 2013-01-09 | 南通智翔信息科技有限公司 | CDMA (Code Division Multiple Access) signaling analysis teach simulated training equipment |
| CN103067195A (en) * | 2012-11-22 | 2013-04-24 | 北京中创信测科技股份有限公司 | Signalling system 7 collection system slot-time/data exchanging controller and implement method thereof |
-
2000
- 2000-11-13 CN CNB001274449A patent/CN1140976C/en not_active Expired - Fee Related
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100356727C (en) * | 2003-03-19 | 2007-12-19 | 华为技术有限公司 | Method for analysing signalling |
| CN100342747C (en) * | 2004-06-28 | 2007-10-10 | 普天信息技术研究院 | Method for detecting signalling server load |
| CN100444561C (en) * | 2005-08-29 | 2008-12-17 | 中兴通讯股份有限公司 | Signal collecting module with exchanging convergence function |
| CN102647238A (en) * | 2012-03-21 | 2012-08-22 | 深圳市友讯达科技发展有限公司 | Telecom energy and frame protocol testing system of information collection wireless downlink channel module |
| CN102867445A (en) * | 2012-09-12 | 2013-01-09 | 南通智翔信息科技有限公司 | CDMA (Code Division Multiple Access) signaling analysis teach simulated training equipment |
| CN102867445B (en) * | 2012-09-12 | 2015-08-05 | 上海智翔信息科技股份有限公司 | CDMA signalling analysis teaching simulation Practical training equipment |
| CN103067195A (en) * | 2012-11-22 | 2013-04-24 | 北京中创信测科技股份有限公司 | Signalling system 7 collection system slot-time/data exchanging controller and implement method thereof |
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| Publication number | Publication date |
|---|---|
| CN1140976C (en) | 2004-03-03 |
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Owner name: ZTE CO., LTD. Free format text: FORMER NAME OR ADDRESS: SHENZHENG CITY ZTE CO., LTD. |
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Address after: 518057 Department of law, Zhongxing building, South Science and technology road, Nanshan District hi tech Industrial Park, Shenzhen Patentee after: ZTE Corporation Address before: 518057, Shenzhen Nanshan District hi tech Industrial Park, science and technology south road, ZTE building, 6 floor of the Ministry of law Patentee before: Zhongxing Communication Co., Ltd., Shenzhen City |
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