CN1331211C - 利用检测闸门氧化硅层中氮化物含量的半导体元件制成方法 - Google Patents

利用检测闸门氧化硅层中氮化物含量的半导体元件制成方法 Download PDF

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CN1331211C
CN1331211C CNB03142094XA CN03142094A CN1331211C CN 1331211 C CN1331211 C CN 1331211C CN B03142094X A CNB03142094X A CN B03142094XA CN 03142094 A CN03142094 A CN 03142094A CN 1331211 C CN1331211 C CN 1331211C
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游智星
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Semiconductor Manufacturing International Beijing Corp
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Abstract

本发明涉及一种集成电路元件的制程方法，包括：引入测试晶片到生产流线的晶片群中去形成一各个制程实验室组，每个晶片都须尚未受闸门层介电质生长的制程步骤。此方法导入实验组晶片于闸门介电质生产的制程，即，闸门氧化程。此方法形成氮氧化硅薄膜到预定的厚度不多于40埃。利用预定的制程温度及引入含氮成份物质，含氧成份物质个别的或混合的，制程环境。此方法是将测试晶片从生产流程中取出，施此第二次氧化步骤于之前的氮氧化硅薄膜至增长出第二厚度，其值大受在氮氧化硅中氮浓度成份的影响。此方法决定厚度值差即第一预定值厚度与第二生成厚度值的差别。另加一步骤即以此值差投应于一群组氮浓度数值表去决定在该薄膜厚度，其氮浓度数值为何。

Description

利用检测闸门氧化硅层中氮化物含量的半导体元件制成方法
技术领域
本发明涉及半导体器件的工艺及集成电路的制造。具体地说，本发明涉及一种生成闸门氧化硅层，内含有氮化物并以检测氮化物浓度决定生成薄的闸门层于MOS结构，应用于逻辑元件。
背景技术
我们可认知此发明应有更广泛的运用价值，例如，此发明可用于各种元件，如动态随机存取存储器，静态随机存取存储器，(SRAM)，专用集成电路(ASIC)，微处理器，微控制器，Flash存储器及其他。
集成电路或“IC”，涉及将无数相连通的元件组制造于单一晶片上含有上百万的元件。现今的IC所提供的表现度及设计复杂度是远远超过以往的想象。为要取得复杂度的改善及增加线路密度(即，单位晶片面积内能被装入的元件数目)，最小化元件的大小规格，又称为元件的“身量规格”(Geometry)，因而IC变得愈来愈小。
增加线路的密度不但改变IC的复杂度及表现度，更提供了最低价的元件器给顾客。一座IC制造厂，须花费动辄百万或十亿美元的造价。各厂有其相对的晶片处理量，而每一片晶片又有其相对的元件数。因此，若我们能将各个IC做得愈小，更多的元件就将可作入单一晶片，于是增加该制造厂的元件产出量。
而要将元件做小，因每个制程有其极限，故是个很难的挑战。也就是说，一种制程组合方式通常只能做小到某种大小规格，再过，则须要改变制程或改变元件铺展的设计。有一种极限例子就是闸门氧化硅层阻挡住杂质促闸门外扩散至其下通道的能力，这种能力决定了三相晶体管元件的可靠度(reliability)。
同可作例证的是，离子渗入杂质能促闸门间游离入通道间造成负面影响。硼杂质常使用于渗入闸门，因其原子小且移动率快，常渗入闸门区内。这种硼迁移常始于闸门层，包括多晶硅层，穿过氧化硅层，到达通道(channel)区内。因硼乃带电杂质，它们通常影响三相晶体管元件的起始电压(ThveShold Voltage)值造成其值的平移，其他限制包括高的价电子滞留(T rapping)率，P-型通道次起始(sub-threshold))电压反转值的恶化(degradation)，较差的三相晶体管的可靠度，极其他。
由上观之，改良制程以制造更佳半导体元件是件必要之事。
发明内容
本发明涉及及半导体器件的工艺及其集成电路的制造。具体说，本发明涉及一种生成闸门氧化硅层，内含氮化物，并以随时检测氮化物浓度方式在MOS元件结构中生成的薄的闸门层，可应用于存储元件。我们可认知此发明有更广泛的运用价值。例如，此发明可应用于各种元件，如静态随机存取存储器(SRAM)，特殊用途集成电路元件体(ASIC)，微处理器，微控制器，Elash存储器及其他。
在一具体实施例中，本发明提供一种制程方法用于生产制造集成电路元件体。
根据本发明，提供一种制造集成电路的工艺方法，包括下列步骤：
引入一测试晶片到生产线晶片群中去形成一组制程实验组，每个晶片都须尚未经闸门层介电质生成的制程步骤，导入此实验组于闸门介电层生成的流程，形成氮氧化硅的薄膜到预定厚度，该预定厚度不多于40埃，形成的温度及氮成份、氧成份气体的种类预先选定，
把测试晶片取出施于第二次氧化步骤，使氮氧化硅层膜增长出第二厚度，此第二厚度之值取决于氮成份在氮氧化硅层中的浓度；
量出预定厚度和第二厚度间之差值；
根据此差值到一氮分子浓度和厚度关系资料中，确定在氮氧化硅层中氮分子的浓度。
根据本发明，提供一种集成电路元件制程方法，其包括：
引入一测试晶片于一闸门介质形成的制程，形成一氮氧化硅层至预定的厚度小于40埃，在预定的制程温度，使用含氮成份物质于测试片上，
使之第二次氧化此氮氧化硅膜，形成增加了第二厚度的氧化膜，此第二厚度的生成，取决于氮成份物质在氮氧化硅中的含量浓度，
根据一氮分子浓度和厚度关系资料，利用第二厚度决定氮成份浓度在氮氧化硅膜中的浓度数值。
非常多的益处可由此发明取代传统方法。例如，此方法利用传统测量技术而简易好用。在其他含蓄体，此发明提高更高的良率，其以每晶片上晶粒数为单位。更加的，此方法提供一种制作程序和传统的制程技术和设备均为匹配。优先的，此方法应将可应用于不同的元件生产。譬如存储器，ASIC，微处理器和其他元件。从不同的含蓄体，此方法都将得到更多不同的优势。这些或其他优势，将于此节或特别的下节介绍。
有关此发明的目的、特征及优点如将于比照细节描述及随同的附图作更详尽描述如下：
附图说明
图1是依本发明一个实施例的半导体元件的简明切面图。
图2是依本发明的另一实施例的半导体元件的简明切面图。
图3是依本发明一个实施例的简明的检测图表。
图4是依本发明一个实施例的简明的检测图表。
图5是依本发明一个实施例的简明厚度图表投射相对氮化物含量，由图4的方法测量取得。
具体实施方式
本发明涉及半导体器件的工艺及集成电路的制造。具体地说，本发明涉及一种生成闸门氧化硅层，内含氮化物成份，并以检测氮化物浓度在MOS元件结构中生成闸门层，可应用于存储器生成。我们可认知此发明应有更广泛的运用价值，例如，此发明可应用于各类元件，如静态随机存取存储器(SRAM)，特殊用途集成电路元件(ASIC)，微处理器，微控制器，Flash存储器及其他。
图1是依本发明一个实施例的半导体元件的简明切面图100。此图仅作例子，不能仅依之而局限本发明申求有效的范围。本领域技术人员，可从此发明悟出许多其他的新变数，改造方式和新取代方法。
如图所示，标记100包含各项特征如闸门体101，包括含硼成份杂质，连同极/集极区域完整定义一个MOS三相晶体管。此含硼成份杂质从闸门区扩散透过闸门之下。在系列制程热效应107下，上述扩散作用会频繁发生。含硼成份的杂质，通常很小，常聚集堆在通道区109中，由于有此硼杂质扩散的现象，制程的限制就很多。此限制包含须考虑发生正向起始电压(Threshold Voltage)的平移，次起始(Sub-threshold)切换值的增加，电子井陷的增加，及其他许多可靠度的问题。基于此，许多技术都研发来设法减少甚或阻止任何硼迁移到通道区的发生。这些技术都将在本文中被介绍、描述、尤其于以下文。
图2是依本发明另一实施例的半导体元件的简明切面图。此图仅作例证，不能依此而局限本发明有效的范围。本技术领域者，不难从此发明而认出许多其他新变数，改造方式和取代方法。如图所示，标志200包括形成氮氧化硅层201于闸门体之下。依之，含硼杂质被保留在闸门区203而大量减少进入通道区其直接位于闸门闸门区之下。通常我们很困难去控制多少量的含氮分子进入氮氧化硅层膜内。亦即，杂质浓度很难测量，而且只能被生产线外特别检测系统来测量，其造成负担和困难。依之，这样一来的层膜几乎无法在合理的准确度内测量它们的厚度尤其当膜是如此薄到传统使用闸门层的结构的厚度。因此，我们研发了一个技巧以检测氮成份在膜内的浓度，利用到下列方法且描述于下。
依本发明一个实施例，一种检测氮成份杂质浓度在闸门层膜中的方法。在此说明提供如下：
1、提供半导体基底晶元片于生产流程中，伴随生产晶片或不随生产晶片；
2、使用水蒸气(即，低于750℃)在基底上形成氧化层；
3、引入含一氧化氮NO(或二氧化氮NO2)的气体，在预先设定温度下，以将含氮分子注入到氧化层；
4、维持薄膜厚度在预先决定数值稍低于30埃(Augstrom)，而其厚度在其他晶片有不同氮成份浓度者，都大致相同在同一范围；
5、在此已氮化(Nitrided)薄膜上进行快速热氧化，以使它长厚达到最后厚度，此长厚已知令受多少氮分子成份存留在氧化硅膜中的影响，此长厚的厚度最好大于第4点中的薄膜厚度。该快速热氧化可以在900℃的含氧分子成份的气体环境中进行。
6、利用精圆测量仪(ellipsometer)测量膜最后厚度；
7、利用氮含量检测分析制成交叉图表对应厚度增长(thickness difference)从最后厚度比照确定的厚度。
8、判定含氮分子在氧化硅膜内的浓度；
9、利用此检测步骤，结果调整必须改变的制程；
10、再作上步骤去判定适合的氮分子浓度；
11、若必须继续其他步骤；
上法是一连续步骤用来准备对应薄膜内氮分子浓度和热工时间(或厚度)的关系。此关系资料将用来判定在任一闸门介电质层中氮分子的浓度。此方法更多细节，陈述于下列图表中。
图3是依本发明一个实施例的简化图式的检测方法300。此图仅作例子，不能依此而局限本发明的有效范围。本技术领域者，不难从此发明而认出许多其他变数，改造方式和取代方法。首先，此方法准备一半导体基底片，用来作闸门层氧化形成。此方法形成利用到水蒸气(即少于750℃)在基底片上形成一预定厚度的闸门氧化层301。此方法亦引入一氧化氮NO(或二氧化氮NO2)等含氮物质在低温时注入此含氮分子于氧化层膜。此层膜收受第一次热工305而形成第一厚度A1321，其厚度受第一次热工预定温度的影响。在此，厚度是用一椭圆仪来测量，可像RudolphInstruments。所造的仪器，但也可以像其他。氮浓度的数值是由SIMS来决定，这些连续步骤，重复施作，以其他热工时间(即，307，309，311)，形成其他厚度(即，A2 323，A3 325，A4 327)和相关的浓度(即，333，335，337)。
图4是依本发明一个实施例的简示图说明检测的方法。此图仅作例子，不能依此而局限本发明的有效范围。本技术领域者，不难从此发明而认出许多其他变数，改造方法和取代方法。参见图4，每一个基底(即，A1 321，A2 323，A3 325，A4 327)均接受快火热工氧化(Rapid therinal Oxidation)或慢火炉热氧化去形成在氮氧化硅上的厚度。最佳晶片上都相似。此制程的实施直到每个基底晶片都形成另加的氧化硅厚度a1，a2，a3，a4，其相对的总厚度则是B1403，B2405，B3407，B4409。使用更简便方式，以椭圆仪测量各晶片总厚度。
仅供于例证，我提供了下列的关系：
a1＝B1-A1
在此，a1是从快火热工氧化或慢火炉热氧化后薄膜厚度；
B1是再氧化了氮氧化硅层后的总厚度；
A1是氮化氧化硅层后的总厚度；
此方法决定a1 411，a2 413，a3 415，a4 421。下一步骤，对照图5的图表，根据再氧化后层的厚度(另加的氧化硅厚度a1，a2，a3，a4)得到其相对的含氮浓度值。由图5作展示，它是一个简易厚度图投射出相对应的氮浓度使用到本发明领域内的图4方法。此图仅作例子，不能依此而局限本发明的有效范围，本技术领域者，不难从此发明而认出许多其他变数，改造方式和取代方法。如示，此垂直的轴表示厚度以埃作单位，而此水平轴，交叉于垂直轴，表示的是氮分子成份的浓度。此方法建立一方式能投照厚度的增加到相对应的浓度切深，依照以上描述的所有程序步骤。
即是，这方法决定测试片厚度于垂直轴上，而决定浓度切深于横轴上，而此法可供决定制程的氮浓度是否须调整改变。

Claims (7)

1、一种制造集成电路的工艺方法，包括下列步骤：
引入一测试晶片到生产线晶片群中去形成一组制程实验组，每个晶片都须尚未经闸门层介电质生成的制程步骤，导入此实验组于闸门介电层生成的流程，形成氮氧化硅的薄膜到预定厚度，该预定厚度不多于30埃，形成的温度及氮成份、氧成份气体的种类预先选定，
把测试晶片取出施于第二次氧化步骤，使氮氧化硅层的薄膜增长出第二厚度，氮成份在氮氧化硅层中的浓度与此第二厚度值有关；
量出预定厚度和第二厚度间之差值；
根据此差值到一氮分子浓度和厚度关系资料中，确定在氮氧化硅层中氮分子的浓度。
2、如权利要求1所述的工艺方法，其特征在于，第二氧化步骤是以快火热工氧化于含氧成份的气体中而完成。
3、如权利要求2所述的工艺方法，其特征在于，第二厚度值是要比预定厚度值大。
4、如权利要求1所述的工艺方法，其特征在于，其第二氧化步骤是以高于900℃，操作于含氧分子成份的气体环境中。
5、如权利要求1所述的工艺方法，其特征在于，建立上述氮分子浓度和厚度关系资料，以标示厚度差值与氮浓度值之间的关系。
6、如权利要求1所述的工艺方法，其特征在于，是以至少椭圆仪来决定该厚度和该第二厚度。
7、一种集成电路元件制程方法，其包括：
引入一测试晶片于一闸门介质形成的制程，在预定的制程温度，使用含氮成份物质于该测试晶片上，形成一氮氧化硅层至预定的厚度，该厚度小于30埃，
第二次氧化此氮氧化硅层，使氮氧化硅层增长出第二厚度，氮成份物质在氮氧化硅层中的浓度与此第二厚度有关，
根据一氮分子浓度和厚度关系资料，利用第二厚度决定氮成份浓度在氮氧化硅层中的浓度数值。
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