WO2001070438A1 - Device for monitoring and calibrating oxide charge measurement equipment and method therefor - Google Patents

Device for monitoring and calibrating oxide charge measurement equipment and method therefor Download PDF

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Publication number
WO2001070438A1
WO2001070438A1 PCT/US2000/007711 US0007711W WO0170438A1 WO 2001070438 A1 WO2001070438 A1 WO 2001070438A1 US 0007711 W US0007711 W US 0007711W WO 0170438 A1 WO0170438 A1 WO 0170438A1
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Prior art keywords
wafer
sio
dielectric layer
layer
stabilized
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PCT/US2000/007711
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French (fr)
Inventor
Ronald Koelsch
Robert Koelsch
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Ronald Koelsch
Robert Koelsch
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Application filed by Ronald Koelsch, Robert Koelsch filed Critical Ronald Koelsch
Priority to KR1020027012504A priority Critical patent/KR20020089407A/en
Priority to EP00918293A priority patent/EP1274529A1/en
Priority to AU2000239126A priority patent/AU2000239126A1/en
Priority to PCT/US2000/007711 priority patent/WO2001070438A1/en
Priority to JP2001568682A priority patent/JP2004507878A/en
Publication of WO2001070438A1 publication Critical patent/WO2001070438A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y25/00—Nanomagnetism, e.g. magnetoimpedance, anisotropic magnetoresistance, giant magnetoresistance or tunneling magnetoresistance
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B5/00—Recording by magnetisation or demagnetisation of a record carrier; Reproducing by magnetic means; Record carriers therefor
    • G11B5/127—Structure or manufacture of heads, e.g. inductive
    • G11B5/33—Structure or manufacture of flux-sensitive heads, i.e. for reproduction only; Combination of such heads with means for recording or erasing only
    • G11B5/39—Structure or manufacture of flux-sensitive heads, i.e. for reproduction only; Combination of such heads with means for recording or erasing only using magneto-resistive devices or effects
    • G11B2005/3996—Structure or manufacture of flux-sensitive heads, i.e. for reproduction only; Combination of such heads with means for recording or erasing only using magneto-resistive devices or effects large or giant magnetoresistive effects [GMR], e.g. as generated in spin-valve [SV] devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B5/00—Recording by magnetisation or demagnetisation of a record carrier; Reproducing by magnetic means; Record carriers therefor
    • G11B5/127—Structure or manufacture of heads, e.g. inductive
    • G11B5/33—Structure or manufacture of flux-sensitive heads, i.e. for reproduction only; Combination of such heads with means for recording or erasing only
    • G11B5/39—Structure or manufacture of flux-sensitive heads, i.e. for reproduction only; Combination of such heads with means for recording or erasing only using magneto-resistive devices or effects
    • G11B5/3903—Structure or manufacture of flux-sensitive heads, i.e. for reproduction only; Combination of such heads with means for recording or erasing only using magneto-resistive devices or effects using magnetic thin film layers or their effects, the films being part of integrated structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • This invention is m the field of semiconductor fabrication process monitoring and control, and methods therefor, and more par t icularly, s a device and method that applies to the calibration, monitoring and control of test equipment used on the process line to measure oxide charge including mobile ion contamination.
  • Semiconductor wafers undergo a variety of measurements to measure and ensure the suitability of the wafer for further processing. Some of these measurements test for acceptable levels of charge time retention, dopant concentration, leakage and mobile ion concentration. In particular, one of these tests, for the detection of mobile ion concentration and other oxide charge is key to the successful fabrication of integrated circuits upon semiconductor wafers m the process line.
  • the monitoring of mobile ion contaminants such as sodium ions or potassium ions is required to ensure that adequate yields result, and also to ensure that the reliability of the products is maintained at a quality level. Mobile ions are most commonly caused by the atoms of contaminant, or impure, materials. Two examples of iriaior sources of contaminants are sodium and potassium.
  • Sodium may be introduced from quartz ware within oxide furnaces, and it may also be present in chemicals used during the semiconductor manufacturing process such as photoresist solutions. These contaminant ions are of course differentiated from implanted dopant ions such as boron and phosphorus .
  • the first of these methods measures the capacitance-voltage (CV) of metal-oxide-silicon (MOS) structures.
  • the second method measures surface photovoltage 'SPV) and oxide surface voltage (Vs't without using a metal contact, and in some cases measures tne amount of charge deposited on top of the oxide by a corona-dischar ⁇ e source.
  • the first measurement method utilizes equipment that is categorized as a contact prooe tester to measure the CV.
  • a contact probe tester method utilizes a process m which a voltage is incremented on a MOS electrode upon the surface of a semiconductor wafer using a contact prooe, and the corresponding increment in the charge upon the wafer, as measured by a contact probe coulombmeter is monitored.
  • the second measurement method utilizes equipment that is categorized as a non-contact probe tester.
  • a corona gun or wire is used to deposit charges on the dielectric for biasing it.
  • An example of a non-contact probe tester is given m U.S. Pat. No. 5,498,974, and functions as follows: A wafer is charged with a non-contact corona discharge at a positive polarity until a positive dielectric field is developed. A negative, thougn equal m value, polarity is then applied to the wafer until a negative dielectric field is developed. The amount of corona discharge necessary to change the dielectric field from the positive field to the negative field is measured. This measured charge, Q m/ is noted.
  • a further problem is that m order to control the oxide charge m a semiconductor fabrication line, it is necessary to distinguish between the variables associated with the dielectric layer of a wafer under test and the variables m the tester itself.
  • An object of the present invention is to provide a system and method of producing improved calibration wafers.
  • Another object of the present invention is to provide a system and method of producing calibration wafers having tne properties of predictability and stability m order to ensure the correct assessment of the production line equipment and the wafers m process .
  • a further object cf the present invention s to provide a system and method of producing high quality calibration wafers capable of meetm ⁇ quaiitv control certification.
  • An additional object cf the present invention is to provide a system and metr.o ⁇ of producing high quality calibration wafers tc enable distinguishing between the variables associated with the dielectric layer of a wafer under test and the variables in the tester itself.
  • a stabilized wafer for monitoring and calibrating oxide charge test equipment comprises; a silicon wafer, a Si0 2 layer upon the silicon wafer, and a phosp osilicate glass layer formed in the Si0 2 layer for providing the stabilized wafer by stabilizing an Si0_ interface and containing oxygen ons.
  • a method of constructing and using a stabilized wafer for monitoring and calibrating oxide charge test equipment comprises the steps of; providing a stabilized wafer for stabilizing an SiO : interface and containing oxygen ions, and using the stabilized wafer for monitoring and calibrating oxide charge test equipment.
  • a method of constructing and using a stabilized wafer for monitoring and calibrating oxide charge test equipment comprises the steps of; providing a silicon wafer, placing a polarizable dielectric layer of Si0 2 or. the silicon wafer for stabilizing an SiO, interface and containing oxygen ions, forming a phospnosilicate glass layer m the top of the SiO_ layer, and anneali c. the silicon wafer.
  • Fig. 1 is a scnematic drawing of tne device used to monitor and calibrate oxide cnarge testers according to the invention.
  • Fig. 2 is a scnematic drawing of the device after polarization of tne PSG layer from an applied electric field and temperature- bias stressing.
  • Fig. 3 is a scnematic drawing of the device after reversal of the temperature- ⁇ ias stressing of Figure 42 .
  • Fig. 4 is an exemplary grapn of the change in surface potential of tne composite dielectric curing temperature-bias stressing.
  • Fig. 5 is an exemplary grapn of the change m oxide charge parameters as a function of the PSG concentration.
  • the present invention is applicable m the fields of both contact and non- contact probe testers and methods of testing for oxide charge, including mobile ion contamination. In a preferred embodiment, it is especially useful for the monitoring and calibration of non- contact probe testers such as the non-contact probe described m U.S. Pat. No, ⁇ ,498,9 "7 4.
  • a wafer standard cf the present invention is constructed from a silicon wafer with a silicon dioxide (SiO,) layer and a layer of phospnosilicate glass (PSG) , and is used for the monitoring and calioration of the mobile ion contact and non-contact probe testers.
  • the polarization properties of tne PSG simulate mobile ions m the SiO by causing a shift m the surface potential of the SiO dielectric after temperature and bias are applied. This phenomena is stable and repeatable making it ideal for mobile ion proce tester calibration and monitoring.
  • Mobile ion prooe tester calibrators m the form of wafer standards are desiraD e but difficult to Puiid Because dielectrics that nave been purposely contaminated witn modiie ions tend to de unpredictable and unstable.
  • the use of a pnospnosilicate (PSG) qlass layer solves this prodlem because its polarization properties result in desirable qualities cf such as the charge drift that has been placed in the wafer is reversible from one polarity to the opposite polarity. Additionally, the wafer charge drift will saturate at a certain level, and then maintain at that level, for a given stressing electric field, time and temperature.
  • PSG pnospnosilicate
  • the wafer's PSG layer has the effect of passivating the Si0 2 , thus preventing the Si-Si0 2 , interface charge cf the grown oxide from shifting and thereby locks in the overall charge characteristics of the final SiO,/PSG composite dielectric. Therefore, the PSG wafer of the present invention has desirable properties of repeatability and stability.
  • PSG film compositions in SiO can be formed by a number of processes.
  • An exemplary method of producing PSG film compositions in SiO is by alloying thermally grown SiO, with phosphorus pentoxide (P 2 0 5 ) vapor followed by a nitrogen anneal.
  • the P 2 0 5 vapor may be from either, a solid P 2 0. : source, a liquid POC1, source, a spin-on-giass phosphorus source, cr a phosphorus doped OVD-SiO, source .
  • Another exemplary method of producing PSG film compositions in SiO is by ion implantation of phosphorus followed by an oxygen anneal .
  • the wafer standard of the present invention is suitable for both contact and non-contact probe testers. If the desired use of the wafer standard is with a contact probe tester, a further addition to a preferred embodiment may be the addition cf a MOS structure.
  • a MOS structure s formed by processing metal contacts on top of the composite dielectric. Additionally, some contact probe testers are designed to measure dielectric properties of wafers without the need of metal contacts, and these contact probe testers may be used with the wafer standard that either do, or do not, have MOS structure metal contacts. If the present invention is desired to oe used with non- contact probe testers, a corona gun or wire is used to deposit a charge upon the wafer standard in a controlled fashion.
  • the applicable measurements of the properties of the wafer standard device formed by the composite dielectric and silicon wafer are obtained by simply using the non-contact probe tester to determine the SPV, Vs and corona charge deposited on top of the dielectric.
  • An Additional advantage and feature of the wafer standard of the present invention in a preferred embodiment includes that since the PSG stabilizes all charges m the Si0 2/ the measurement of leakage, threshold voltage (Vt) , equivalent charge (Qeff) , total charge (Qtot) , density of interface traps (Dit) , density of oxide traps (Dot), flatband voltage (Vfb), dielectric thickness (Tox)and surface photovoltage (SPV) becomes repeatable day m and day out over months of time. Additionally, the wafer standard becomes the means to measure and control the variables m a probe tester including the variables having their origins in electrical, mechanical, thermal or computer software components. Furthermore, a wafer standard, m a preferred embodiment of the present invention, may be used to monitor, calibrate and troubieshoot oxide charge testers and correlate it with other testers.
  • the wafer standard device 10 for calibrating mobile ion probe testers, or oxide charge testers is shown.
  • the wafer standard device 10 in a preferred embodiment, is a silicon wafer 16 with a pola ⁇ zable dielectric layer.
  • the dielectric may be Si0 2 14 with a PSG 12 layer en the top.
  • the SiO, 14 is thermally grown to a thickness of approximately 500 to 700 angstroms and the PSG 12 is formed by either diffusing or ion implanting pnospnorus into tne SiO, 14.
  • special cases ignt use SiO, 14 thermally grown to a th ⁇ c ⁇ ness as thin as about 100 angstroms and as thick as about 1500 angstroms.
  • An appropriate anneal is done to complete the wafer standard device 10.
  • the anneal must minimize S ⁇ -S ⁇ O ⁇ interface charge and assure the formation of the P O. molecule.
  • an oxygen anneal between about 700°C to about 1000°C is used to incorporate oxygen into the process so that P 0.. is formed, though m a preferred embodiment, a temperature range of about 900°C to about 1000°C is used for the oxygen anneal.
  • a nitrogen anneal m the same temperature range (s) as that used for the oxygen anneal is sufficient because the oxygen is available to form P,0 5 during the POCL3 deposition.
  • PSG 12 is thus formed by alloying SiO 14 with P,0..
  • the PSG 12 serves to ensure that movement of ions such as oxygen are contained within the PSG 12. Furthermore, the PSG 12 protects and stabilizes the SiO, 14 interface.
  • the structure of the S ⁇ 0 2 14 is composed of interconnected tetrahedra of S ⁇ 0 4 . Alloying Si0 2 14 with P 2 0 5 to form PSG 12 incorporates tetrahedra of PO justify into the network of S ⁇ 0 2 14.
  • the non-bridgmg oxygen ion associated with every other phosphorus ion results m a loosely bound oxygen ion that transfers between neighboring PO filed tetrahedra under the influence of an applied electric field.
  • the mobility of the oxygen ion results m the electrical polarization of tne PSG 12.
  • the mooile ions stay inside the PSG 12 layer.
  • the negative oxygen ions also act to getter oxide contaminates such as mobile positive ions like sodium that weaken and destabilize the SiO, 14.
  • This beneficial effect of the PSG 12 layer accounts for the repeatability of the mobile ion measurement day m day out over months of testing. Furthermore, the PSG 12 formation general... , coincides .-vitn a quidus cnase.
  • the resulting continuous qiass ⁇ ayer over the oxioe accounts for an increase m the dielectric strength of the PSG/SiO, composite compared to SiO, alone and greatly reduces flaw-type failures.
  • Another beneficial effect of the continuous glass layer formed by tne PSG 12 is to stabilize the overa-1 cnarge characteristics of the capacitor formed by the S1-S1O -PSG, assuring the repeatability of interface and ouik charge measurements such as: leakage, Vt, Vfb, Qeff, Tox, Dit, Dot, Qtot, spv tests etc.
  • the result is a wafer standard device 10 ideal for use as a wafer standard for oxioe charge testers .
  • the dipoies of the PSG 12 may be randomly disordered m some initial state.
  • the dipoies snou ⁇ o be pre-aligned at tne beginning of tne calibration metnoc to bring them to an orderly initial state. This can oe accomplished by letting the dipoies come to equilibrium at room temperature Pefore testing of oxide testers or by defining some other initial state by pre-aligning tne dipoies m the PSG 12 layer.
  • the method for calibrating the wafer standard device 10 begins by aligning the dipoies of the polarization layer, PSG 12, in the same direction.
  • tms is best accomplished by thermal stressing using a negative corona Pias for p-type wafers and positive corona Dias for n-type wafers.
  • the normal mobile ion test routine _s carried out which usually consists of a "pusn” using positive bias followed by multiple "pulls" using negative bias (see Fig. # 3) to get full oipole reversal and a consistent mobile ion measurement.
  • the present embodiment shows the use of plus and minus 8 .ilovolts for this procedure of pusn v F ⁇ g. 2) and pull (Fig. 3 .
  • the actual voltage used for this procedure may vary however _-. accordance with the equipment or platform that tne wafer standard device 10 of the present _nvent ⁇ cn is being used with.
  • a typical PSG composition, temperature- bias stress condition and related surface voltage shift as a function of time are shown.
  • the PSG concentration m the SiO is between one and fifteen mole percent.
  • the concentration of PSG is controlled by the time, temperature and parts per million (ppm) of the ? 0 5 diffusion. For ion implantation, it is the dose and energy of tne pnosphorus ion implantation that sets the concentration.
  • the final concentration cf the PSG is measured by Secondary Ion Mass Spectroscopy 'SIMS), or by the etch rate of the PSG m a dilute HF bath.
  • Thermal stress conditions may vary by species of dipoies and type of dielectric.
  • Typical stress temperatures for PSG m S ⁇ 0 2 range from 170°C to 280°C and typical biasing electric fields vary from 0.5 x 10 volts per centimeter to 2.5 x 10' volts per centimeter. This combination of thermal stress conditions gives a flatband voltage shift of between 30 millivolts and 250 millivolts for a dielectric thickness from 500 angstroms to 1000 angstroms. This corresponds to mobile ion concentrations of from 0.5 x 10 10 ions per square centimeter to 20 x 10 10 ions per square centimeter.
  • Figure # 5 shows the change m various oxide charges as the concentration of PSG changes.
  • the wafer standard device 10 (Fig. 1-3) can be fabricated to give the end user the quantity of charge desired for a particular application.
  • Q n/ for example, if 4xlO iC mobile ions per square centimeter are oesired, the PSG concentration would be 5 mole %.
  • Qeff of 4x10-- charges per square centimeter the PSG concentration would be 2 moIe % .

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Abstract

A stabilized wafer for monitoring and calibrating oxide charge test equipment. The stabilized wafer comprises; a silicon wafer, a SiO2 layer of at least 100 angstroms upon the silicon wafer, and a phosphosilicate glass layer containing phosphorus formed in the SiO2 layer for providing the stabilized wafer by stabilizing an SiO2 interface and containing oxygen ions. The stabilized wafer is used for monitoring and calibrating oxide charge test equipment.

Description

Device For Monitoring and Calibrating Oxide Charge Measurement Equipment and Method Therefor
1. Field of the Invention
This invention is m the field of semiconductor fabrication process monitoring and control, and methods therefor, and more particularly, s a device and method that applies to the calibration, monitoring and control of test equipment used on the process line to measure oxide charge including mobile ion contamination.
2. Description of the Related Art
Semiconductor wafers undergo a variety of measurements to measure and ensure the suitability of the wafer for further processing. Some of these measurements test for acceptable levels of charge time retention, dopant concentration, leakage and mobile ion concentration. In particular, one of these tests, for the detection of mobile ion concentration and other oxide charge is key to the successful fabrication of integrated circuits upon semiconductor wafers m the process line. The monitoring of mobile ion contaminants such as sodium ions or potassium ions is required to ensure that adequate yields result, and also to ensure that the reliability of the products is maintained at a quality level. Mobile ions are most commonly caused by the atoms of contaminant, or impure, materials. Two examples of iriaior sources of contaminants are sodium and potassium. Sodium may be introduced from quartz ware within oxide furnaces, and it may also be present in chemicals used during the semiconductor manufacturing process such as photoresist solutions. These contaminant ions are of course differentiated from implanted dopant ions such as boron and phosphorus .
In general there are two methods that are routinely used to test for oxide charge, including mobile ion contamination. The first of these methods measures the capacitance-voltage (CV) of metal-oxide-silicon (MOS) structures. The second method measures surface photovoltage 'SPV) and oxide surface voltage (Vs't without using a metal contact, and in some cases measures tne amount of charge deposited on top of the oxide by a corona-discharσe source. The first measurement method utilizes equipment that is categorized as a contact prooe tester to measure the CV. A contact probe tester method utilizes a process m which a voltage is incremented on a MOS electrode upon the surface of a semiconductor wafer using a contact prooe, and the corresponding increment in the charge upon the wafer, as measured by a contact probe coulombmeter is monitored.
The second measurement method utilizes equipment that is categorized as a non-contact probe tester. In the non-contact probe tester method a corona gun or wire is used to deposit charges on the dielectric for biasing it. An example of a non-contact probe tester is given m U.S. Pat. No. 5,498,974, and functions as follows: A wafer is charged with a non-contact corona discharge at a positive polarity until a positive dielectric field is developed. A negative, thougn equal m value, polarity is then applied to the wafer until a negative dielectric field is developed. The amount of corona discharge necessary to change the dielectric field from the positive field to the negative field is measured. This measured charge, Qm/ is noted. Next, an ideal amount of corona discharge necessary to change the dielectric field voltage of a dielectric layer of known thickness from a specific positive dielectric field to a negative, though equal m value, dielectric field is then applied to the wafer. The resultant ideal charge, Ql f is then observed. The ideal charge ζø is then compared to the measured charge __. The difference between the measured ideal charge Q. and measured cnarge Q_ is directly proportional to the amount of mobile ions m the dielectric layer.
There is however, a major area of concern with mooile ion measurement equipment and methods. In order to assure that the readings and measurements obtained by the mobile ion measurement equipment and methods are of high quality, the equipment and methods must be calibrated and verified. There is currently only one common method used for the calibration of mooile ion measurement equipment, and this method is incapable cf meeting accepted quality control standards, such as ISO 9000, (International Organization for Standardization (ISO) - Quality management and quality standards assurance. (9000 series'" This method of calibration consists of the production of calibration wafers that have deen intentionally contaminated witn mooiie ions. Λhiie the production of calibration wafers, or wafer standards as they are sometimes Known, s desirable, these calibration wafers are difficult to produce because the dielectrics of a wafer that have been purposely contaminated with mobile ions tend to be unpredictable and unstable m their use. The unpredictability and instability of the calibration wafers can result m the incorrect calibration of the oxide charge measurement equipment. This may then lead to incorrect assessments of the production line equipment and the wafers m process, which in turn leads to faulty or imperfectly operating semiconductor devices.
A further problem is that m order to control the oxide charge m a semiconductor fabrication line, it is necessary to distinguish between the variables associated with the dielectric layer of a wafer under test and the variables m the tester itself.
Therefore, a need existed for a system and method cf producing improved calibration wafers. An additional need existed for a system and method of producing calibration wafers navmg the properties of predictability and stability in order to ensure the correct assessment of the production line equipment and the wafers in process. A further need existed for a system and method of producing high quality calibration wafers capable of meeting quality control certification. Yet a further need existed for a system and method of producing high quality calibration wafers to enable distinguishing between the variables associated with the dielectric layer of a wafer under test and the variables m the tester itself.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a system and method of producing improved calibration wafers.
Another object of the present invention is to provide a system and method of producing calibration wafers having tne properties of predictability and stability m order to ensure the correct assessment of the production line equipment and the wafers m process .
A further object cf the present invention s to provide a system and method of producing high quality calibration wafers capable of meetmσ quaiitv control certification. An additional object cf the present invention is to provide a system and metr.oα of producing high quality calibration wafers tc enable distinguishing between the variables associated with the dielectric layer of a wafer under test and the variables in the tester itself.
BRIEF DESCRIPTION OF THE PREFERRED EMBODIMENTS
In accordance with a preferred embodiment of the present invention a stabilized wafer for monitoring and calibrating oxide charge test equipment s disclosed. The stabilized wafer for monitoring and calibrating oxide charge test equipment comprises; a silicon wafer, a Si02 layer upon the silicon wafer, and a phosp osilicate glass layer formed in the Si02 layer for providing the stabilized wafer by stabilizing an Si0_ interface and containing oxygen ons.
In accordance with another embodiment cf the present invention a method of constructing and using a stabilized wafer for monitoring and calibrating oxide charge test equipment is disclosed. The method of constructing and using a stabilized wafer for monitoring and calibrating oxide charge test equipment comprises the steps of; providing a stabilized wafer for stabilizing an SiO: interface and containing oxygen ions, and using the stabilized wafer for monitoring and calibrating oxide charge test equipment.
In accordance with yet another emocdiment of the present invention a method of constructing and using a stabilized wafer for monitoring and calibrating oxide charge test equipment is disclosed. The method of constructing and using a stabilized wafer for monitoring and calibrating oxide charge test equipment comprises the steps of; providing a silicon wafer, placing a polarizable dielectric layer of Si02 or. the silicon wafer for stabilizing an SiO, interface and containing oxygen ions, forming a phospnosilicate glass layer m the top of the SiO_ layer, and anneali c. the silicon wafer. BRIEF DESCRIPTION OF THE DRAWING
Fig. 1 is a scnematic drawing of tne device used to monitor and calibrate oxide cnarge testers according to the invention.
Fig. 2 is a scnematic drawing of the device after polarization of tne PSG layer from an applied electric field and temperature- bias stressing.
Fig. 3 is a scnematic drawing of the device after reversal of the temperature-αias stressing of Figure 42 .
Fig. 4 is an exemplary grapn of the change in surface potential of tne composite dielectric curing temperature-bias stressing.
Fig. 5 is an exemplary grapn of the change m oxide charge parameters as a function of the PSG concentration.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
When using either of the two oxide cnarge measurement methods, contact or non-contact, it is necessary to monitor and calibrate both the contact and non-contact probe testers. The present invention is applicable m the fields of both contact and non- contact probe testers and methods of testing for oxide charge, including mobile ion contamination. In a preferred embodiment, it is especially useful for the monitoring and calibration of non- contact probe testers such as the non-contact probe described m U.S. Pat. No, δ,498,9"74.
A wafer standard cf the present invention is constructed from a silicon wafer with a silicon dioxide (SiO,) layer and a layer of phospnosilicate glass (PSG) , and is used for the monitoring and calioration of the mobile ion contact and non-contact probe testers. The polarization properties of tne PSG simulate mobile ions m the SiO by causing a shift m the surface potential of the SiO dielectric after temperature and bias are applied. This phenomena is stable and repeatable making it ideal for mobile ion proce tester calibration and monitoring.
Mobile ion prooe tester calibrators m the form of wafer standards are desiraD e but difficult to Puiid Because dielectrics that nave been purposely contaminated witn modiie ions tend to de unpredictable and unstable. The use of a pnospnosilicate (PSG) qlass layer solves this prodlem because its polarization properties result in desirable qualities cf such as the charge drift that has been placed in the wafer is reversible from one polarity to the opposite polarity. Additionally, the wafer charge drift will saturate at a certain level, and then maintain at that level, for a given stressing electric field, time and temperature. And furthermore, the wafer's PSG layer has the effect of passivating the Si02, thus preventing the Si-Si02, interface charge cf the grown oxide from shifting and thereby locks in the overall charge characteristics of the final SiO,/PSG composite dielectric. Therefore, the PSG wafer of the present invention has desirable properties of repeatability and stability.
These desirable properties are particularly interesting in that PSG was once examined for use in stabilizing field effect transistor (FET) gate oxides, but its use was rejected as the polarization effect caused too much threshold voltage (Vt; shift in that application. However, n a preferred embodiment of the present invention, that same property of polarization has been found to be particularly useful for the simulation of mobile ions to result in predictable and stable wafer standards.
PSG film compositions in SiO, can be formed by a number of processes. An exemplary method of producing PSG film compositions in SiO, is by alloying thermally grown SiO, with phosphorus pentoxide (P205) vapor followed by a nitrogen anneal. The P205 vapor may be from either, a solid P20.: source, a liquid POC1, source, a spin-on-giass phosphorus source, cr a phosphorus doped OVD-SiO, source .
Another exemplary method of producing PSG film compositions in SiO, is by ion implantation of phosphorus followed by an oxygen anneal .
The wafer standard of the present invention is suitable for both contact and non-contact probe testers. If the desired use of the wafer standard is with a contact probe tester, a further addition to a preferred embodiment may be the addition cf a MOS structure. A MOS structure s formed by processing metal contacts on top of the composite dielectric. Additionally, some contact probe testers are designed to measure dielectric properties of wafers without the need of metal contacts, and these contact probe testers may be used with the wafer standard that either do, or do not, have MOS structure metal contacts. If the present invention is desired to oe used with non- contact probe testers, a corona gun or wire is used to deposit a charge upon the wafer standard in a controlled fashion. The combination of the electric field created across the dielectric by this deposited charge and the heating of the wafer standard from the wafer chuck heating, will stress the PSG layer electrically and thermally, causing it to polarize. A Kelvin probe, a Monroe probe or their equivalent is used to measure the potential of the dielectric surface before and after stressing. The shift in dielectric surface potential is quantified to simulate mobile ion drift (Qm) in SiO,.
The applicable measurements of the properties of the wafer standard device formed by the composite dielectric and silicon wafer are obtained by simply using the non-contact probe tester to determine the SPV, Vs and corona charge deposited on top of the dielectric.
An Additional advantage and feature of the wafer standard of the present invention in a preferred embodiment includes that since the PSG stabilizes all charges m the Si02/ the measurement of leakage, threshold voltage (Vt) , equivalent charge (Qeff) , total charge (Qtot) , density of interface traps (Dit) , density of oxide traps (Dot), flatband voltage (Vfb), dielectric thickness (Tox)and surface photovoltage (SPV) becomes repeatable day m and day out over months of time. Additionally, the wafer standard becomes the means to measure and control the variables m a probe tester including the variables having their origins in electrical, mechanical, thermal or computer software components. Furthermore, a wafer standard, m a preferred embodiment of the present invention, may be used to monitor, calibrate and troubieshoot oxide charge testers and correlate it with other testers.
Construction
Referring first to fig. 1, the wafer standard device 10 for calibrating mobile ion probe testers, or oxide charge testers is shown. The wafer standard device 10, in a preferred embodiment, is a silicon wafer 16 with a polaπzable dielectric layer. The dielectric may be Si02 14 with a PSG 12 layer en the top. In that case, m a preferred embodiment, the SiO, 14 is thermally grown to a thickness of approximately 500 to 700 angstroms and the PSG 12 is formed by either diffusing or ion implanting pnospnorus into tne SiO, 14. However, special cases ignt use SiO, 14 thermally grown to a thιcκness as thin as about 100 angstroms and as thick as about 1500 angstroms. An appropriate anneal is done to complete the wafer standard device 10.
The anneal must minimize Sι-SιO^ interface charge and assure the formation of the P O. molecule. In a preferred embodiment, When implanting phospnorus, an oxygen anneal between about 700°C to about 1000°C is used to incorporate oxygen into the process so that P 0.. is formed, though m a preferred embodiment, a temperature range of about 900°C to about 1000°C is used for the oxygen anneal.
When diffusion is used, a nitrogen anneal m the same temperature range (s) as that used for the oxygen anneal is sufficient because the oxygen is available to form P,05 during the POCL3 deposition. PSG 12 is thus formed by alloying SiO 14 with P,0.. The PSG 12 serves to ensure that movement of ions such as oxygen are contained within the PSG 12. Furthermore, the PSG 12 protects and stabilizes the SiO, 14 interface.
The structure of the Sι02 14 is composed of interconnected tetrahedra of Sι04. Alloying Si02 14 with P205 to form PSG 12 incorporates tetrahedra of PO„ into the network of Sι02 14. The non-bridgmg oxygen ion associated with every other phosphorus ion results m a loosely bound oxygen ion that transfers between neighboring PO„ tetrahedra under the influence of an applied electric field. The mobility of the oxygen ion results m the electrical polarization of tne PSG 12. The mooile ions stay inside the PSG 12 layer.
This is m contrast to the general case SiO, 14 contaminated with mooile sodium ions when there is no PSG 12 to protect the SiO 14. In this case the sodium is free to move throughout the SiO, 14 m a random ano unpredictable manner. This containment of the mobile oxygen ions m the PSG 12 layer explains why SiO, 14 with PSG 12 produces a ucn more repeatable mobile ion measurement on the tester.
The negative oxygen ions also act to getter oxide contaminates such as mobile positive ions like sodium that weaken and destabilize the SiO, 14. This beneficial effect of the PSG 12 layer accounts for the repeatability of the mobile ion measurement day m day out over months of testing. Furthermore, the PSG 12 formation general..., coincides .-vitn a quidus cnase. The resulting continuous qiass ^ayer over the oxioe accounts for an increase m the dielectric strength of the PSG/SiO, composite compared to SiO, alone and greatly reduces flaw-type failures. Another beneficial effect of the continuous glass layer formed by tne PSG 12 is to stabilize the overa-1 cnarge characteristics of the capacitor formed by the S1-S1O -PSG, assuring the repeatability of interface and ouik charge measurements such as: leakage, Vt, Vfb, Qeff, Tox, Dit, Dot, Qtot, spv tests etc. The result is a wafer standard device 10 ideal for use as a wafer standard for oxioe charge testers .
Before use of the wafer standard device 10 for testing of oxide testers, the dipoies of the PSG 12 may be randomly disordered m some initial state. To get a consistent mobile ion measurement, the dipoies snou^o be pre-aligned at tne beginning of tne calibration metnoc to bring them to an orderly initial state. This can oe accomplished by letting the dipoies come to equilibrium at room temperature Pefore testing of oxide testers or by defining some other initial state by pre-aligning tne dipoies m the PSG 12 layer.
Referring to figure # 2, the method for calibrating the wafer standard device 10 begins by aligning the dipoies of the polarization layer, PSG 12, in the same direction. For a PSG 12 layer, tms is best accomplished by thermal stressing using a negative corona Pias for p-type wafers and positive corona Dias for n-type wafers. After ore-alignment the normal mobile ion test routine _s carried out which usually consists of a "pusn" using positive bias followed by multiple "pulls" using negative bias (see Fig. # 3) to get full oipole reversal and a consistent mobile ion measurement. The present embodiment shows the use of plus and minus 8 .ilovolts for this procedure of pusn vFιg. 2) and pull (Fig. 3 . The actual voltage used for this procedure may vary however _-. accordance with the equipment or platform that tne wafer standard device 10 of the present _nventιcn is being used with.
Testing non-mobile ion oxide parameters sucn as leakage, Vt, Vfb, Qeff, Dit, Dot, Qtot, spv, etc. ^s best done when the PSG 12 layer po aπzation is m the _n tιal state of choice, oe it equilibrium or pre-alignment . This assures repeatable measurements that are not sκeweo by an unκnown cnarge distribution within tne PSG 12 layer due to random polarization.
Referring to Fig. 4, a typical PSG composition, temperature- bias stress condition and related surface voltage shift as a function of time are shown. The PSG concentration m the SiO, is between one and fifteen mole percent. The concentration of PSG is controlled by the time, temperature and parts per million (ppm) of the ? 05 diffusion. For ion implantation, it is the dose and energy of tne pnosphorus ion implantation that sets the concentration. The final concentration cf the PSG is measured by Secondary Ion Mass Spectroscopy 'SIMS), or by the etch rate of the PSG m a dilute HF bath. Thermal stress conditions may vary by species of dipoies and type of dielectric. Typical stress temperatures for PSG m Sι02 range from 170°C to 280°C and typical biasing electric fields vary from 0.5 x 10 volts per centimeter to 2.5 x 10' volts per centimeter. This combination of thermal stress conditions gives a flatband voltage shift of between 30 millivolts and 250 millivolts for a dielectric thickness from 500 angstroms to 1000 angstroms. This corresponds to mobile ion concentrations of from 0.5 x 1010 ions per square centimeter to 20 x 1010 ions per square centimeter.
Figure # 5 shows the change m various oxide charges as the concentration of PSG changes. The wafer standard device 10 (Fig. 1-3) can be fabricated to give the end user the quantity of charge desired for a particular application. In the instance of Qn/ for example, if 4xlOiC mobile ions per square centimeter are oesired, the PSG concentration would be 5 mole %. Similarly, for a Qeff of 4x10-- charges per square centimeter the PSG concentration would be 2 moIe % .
Although the invention has been particularly shown and described with reference to a preferred embodiment tnereof, it will be understood by those skilled m the art that changes m form and detail may be made therein without departing from the spirit and scope of the invention.

Claims

What is Claimed is:
1. A stabilized wafer for monitoring and calibrating oxide charge test equipment, comprising m combination: a silicon wafer; a SιOz layer upon said silicon wafer; and a phosphosilicate glass layer formed m said Sι02 layer for providing said stabilized wafer by stabilizing an Sι02 interface and containing oxygen ions.
2. The stabilized wafer of Claim 1 wherein said phosphosilicate glass layer comprises gas diffused phosphorus.
3. The stabilized wafer of Claim 1 wherein said phosphosilicate glass layer comprises ion implanted phosphorus.
4. The stabilized wafer of Claim 1 wherein said SiO, layer has a thickness of at least 100 angstroms.
5. The stabilized wafer of Claim 1 further comprising MOS metal contacts formed on said phosphosilicate glass layer.
6. A method of constructing and using a stabilized wafer for monitoring and calibrating oxide charge test equipment, comprising the steps of: providing a stabilized wafer for stabilizing an SiO, interface and containing oxygen ions; and using said stabilized wafer for monitoring and calibrating oxide charge test equipment.
7. The method of claim 6 wherein said step of providing a stabilized wafer for stabilizing an SiO interface and containing oxygen ions comprises the steps of: providing a silicon wafer; placing a polarizable dielectric layer of SiO, on said silicon wafer; forming a phospnosilicate glass layer in the top of said polarizable dielectric layer of SiO, ; and annealing said silicon wafer.
8. The method of Claim 7 wherein said step of placing a polarizable dielectric layer of SiO, on said silicon wafer is comprised of the step of building said polarizable dielectric layer of SiO, to a thickness of at least 100 angstroms.
9 The method of Claim 8 wherein said step of forming a phospnosilicate glass layer in the top of said polarizable dielectric layer of SiO is comprised of the step of gas diffusing phosphorus into said polarizable dielectric layer of Sι02.
10 The method of Claim 9 wherein said step of annealing is comprised of the step of nitrogen annealing m a temperature range of about 700°C to about 1000°C.
11 The method of Claim 8 wherein said step of forming a phosphosixicate αlass layer m the top of said polarizable dielectric layer of SiO, is comprised of the step of ion implanting phosphorus into said polarizable dielectric layer of SiO, .
12. The method of Claim 11 wherein said step of annealing is comprised of the step of oxygen annealing in a temperature range of about 700°C to about 1000°C.
13. The method of claim 6 wherein said step of using said stabilized wafer for monitoring and calibrating oxide charge test equipment comprises the steps of: pre-alignmg dipoies of said phosphosilicate glass layer; and calibrating said stabilized wafer.
14. The etnod of Claim 13 nerem said step of pre-alignmg dipoies of said phospnosilicate giass ±ayer comprises the step of letting said dipoies come to equilibrium at room temperature.
15. The metnod cf Claim 13 wnerem said step of pre-alignmg dipoies cf said phospnosilicate giass layer comprises the step of aligning said dipoies m a user defined state.
16. The method of Claim 13 wnerem said step of calibrating said stabilized wafer comprises tne step of aligning dipoies of said phospnosilicate glass layer the same direction by thermal stressing using a negative corona bias for p-type wafers and positive corona bias for n-type wafers.
17. The method cf Claim 16 further comprising tne step of performing testing of oxide charge test equipment using said wafer standard by "pushing" said dipoies using positive bias followed by multiple "pulls" of said dipoies using negative bias.
18. A method of constructing a stabilized wafer for monitoring and calibrating oxide charge test equipment, comprising the steps of: providing a silicon wafer; placing a polarizable dielectric layer of SιO_ on said silicon wafer for stabilizing an SiO, interface and containing oxygen ions; forming a phospnosilicate glass layer _n the top cf said polarizable dielectric layer of Sι02; and annealing said silicon wafer.
19. The method cf Claim 18 wherein said step of placing a polarizable dielectric layer of SiO, on said silicon wafer is comprised of the step of building said polarizable dielectric layer of Sι02 to a thickness of at least 100 angstroms.
20. The method cf Claim 18 wherein said step of forming a phosphosilicate glass layer in the top of said polarizable dielectric layer of SxO, is comprised of the step of gas diffusing phosphorus into said polarizable dielectric layer of SiO, .
21. The method of Claim 20 wherein said step of annealing is comprised of the step of nitrogen annealing m a temperature range of about 700°C to about 1000°C.
22. The method of Claim 18 wherein said step of forming a phospnosilicate glass layer the top of said polarizable dielectric layer of Sι02 is comprised of the step of ion implanting phosphorus into said polarizable dielectric layer of SiO, .
23. The method of Claim 22 wherein said step of annealing is comprised of the step of oxygen annealing a temperature range of about 700°C to about 1000°C.
PCT/US2000/007711 2000-03-20 2000-03-20 Device for monitoring and calibrating oxide charge measurement equipment and method therefor WO2001070438A1 (en)

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