CN1303686C - High-current triggered electrostatic discharge protector - Google Patents
High-current triggered electrostatic discharge protector Download PDFInfo
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- CN1303686C CN1303686C CNB011097906A CN01109790A CN1303686C CN 1303686 C CN1303686 C CN 1303686C CN B011097906 A CNB011097906 A CN B011097906A CN 01109790 A CN01109790 A CN 01109790A CN 1303686 C CN1303686 C CN 1303686C
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Abstract
The present invention relates to a high-current triggered electrostatic discharge (ESD) protecting circuit which is electrically coupled with a contact point and reference potential to release electrostatic discharge current generated on the contact point. The electrostatic discharge protecting circuit comprises a first conduction type substrate, a second conduction type well region, a first conduction type first doped region and a second conduction type second doped region, wherein the substrate is electrically coupled with the reference potential, and the well region is arranged on the substrate and is electrically coupled with the contact point; the first doped region is arranged on the surface of the well region in an electrically floating mode, and the second doped region is arranged on the substrate and is electrically coupled with the reference potential. ESD current of the contact point supplies voltage to break the connecting surface between the well region and the substrate and trigger a side bipolar transistor composed of the well region, the substrate and the second doped region to release the ESD current. When the electrostatic discharge (ESD) current is higher than predetermined current, the first doped region reduces the potential difference from the contact point to the reference potential.
Description
Technical field
The present invention relates to a kind of static discharge (electrostatic discharge, ESD) protection circuit, especially the ESD protection circuit that refers to a kind of high current trigger, ESD protection circuit of the present invention can provide good electrostatic discharge protective on the one hand, can avoid the ESD protection circuit that the phenomenon of bolt-lock (latch up) takes place when normal running on the other hand.
Background technology
Generally speaking, avoid being subjected to the high voltage destruction that extraneous static electrification article are produced in order to protect the semiconductor chip that completes, so, all can be provided with the ESD protection circuit between the I/O port of existing semiconductor chip and the power port.According to the demand on the circuit, the ESD protection circuit should present the state of open circuit, so that power port and I/O port can be kept operate as normal when general normal running; When having esd event only and occurring in an end of ESD protection circuit, the ESD protection circuit just presents the state near short circuit, in order to the ESD electric current is discharged, with the internal circuit of protection semiconductor chip.
Known ESD protection circuit can be divided into two kinds haply, a kind of is to be primary clustering with bipolar transistor (bipolar transistor), another kind is that (semiconductor control rectifier SCR) is primary clustering with semiconductor controlled rectifier.
Bipolar transistor in the ESD protection circuit generally all is that the bipolar transistor of source electrode/substrate/parasitism that drain electrode produced of utilizing the MOS transistor in the output port constitutes.Because the MOS transistor of output port must have very big thrust, so parasitic bipolar transistor also can emit a large amount of electric currents when electrostatic discharge event takes place.But with regard to the ESD protection circuit between input port and power line, so method just can increase very large chip area more.And the holding voltage Vh of bipolar transistor (holding voltage) is approximately more than 7 volts generally than higher.Therefore, under a large amount of ESD current flowing, will on bipolar transistor, produce high heat.The regional area of MOS transistor if the ESD electric current is only flowed through just is easy to cause MOS transistor to burn.Therefore, the design based on the electrostatic discharge protection circuit of bipolar transistor is to be difficult for very much.
Existing popular ESD protection circuit is to be primary clustering with SCR, gets its low holding voltage Vh (～1.6 volts), low trigger current and consumes the little benefit of semiconductor area.But so (electromagnetic comparability, ESD's ESD protection circuit of design EMC) can go wrong when testing jointly in the electromagnetism of experience system level (system-level).EMC/ESD is after whole system is installed during test, and provides under the power supply, carries out the ESD test.When the EMC/ESD test was carried out, SCR can make an ESD electric current on the I/O port discharge really.Yet power supply generally all is greater than the voltage more than 3 volts.If, the voltage of script on the I/O port before EMC/ESD test be near power source voltage (～3V), that is after EMC/ESD tests, SCR just can be maintained at the voltage on the I/O port holding voltage Vh (～1.6 volts), this just can cause the machine of working as on the whole system, even burns the semiconductor chip of part.
Summary of the invention
In order to overcome the deficiencies in the prior art part, purpose of the present invention is to provide a kind of ESD protection circuit of high current trigger, has the characteristic of little, low holding voltage of the area that takies semiconductor chip and high trigger current, to solve the above problems.
According to above-mentioned purpose, the present invention proposes a kind of ESD protection circuit of high current trigger.ESD protection circuit of the present invention is electrically coupled to a contact and a reference potential, in order to discharge the static discharge current that produces from this contact.This electrostatic storage deflection (ESD) protection circuit includes the substrate of one first conductivity type, the well region of one second conductivity type, first doped region of one first conductivity type and second doped region of one second conductivity type.This substrate is electrically coupled to this reference potential.This well region is located in this substrate, and is electrically coupled to this contact.This first doped region electricity floats is located at this well region surface.This second doped region is located in this substrate, and is electrically coupled to this reference potential.Wherein, the ESD electric current on this contact provides a voltage that the face that connects between this well region and this substrate is collapsed, and triggers the side direction bipolar transistor that this well region, this substrate and this second doped region are constituted, to discharge this static discharge current.This first doped region is in this static discharge current during greater than a scheduled current, in order to reduce the potential difference of this contact to this reference potential.
With regard to the circuit viewpoint, the present invention provides a kind of electrostatic storage deflection (ESD) protection circuit of high current trigger in addition, is coupled in a contact and a reference potential, in order to discharge the static discharge current that produces from this contact.Electrostatic storage deflection (ESD) protection circuit of the present invention includes first doped region of a bipolar transistor and one first conductivity type.This bipolar transistor includes an emitter, a base stage and a collector electrode.Wherein this emitter and this base stage all are electrically coupled to this reference potential, and this current collection polar system is constituted with the collector area of one second conductivity type and is electrically coupled to this contact.This first doped region, unsteady is located in this collector area, and connects face with this collector area formation one.Wherein, this static discharge current makes the face that the connects collapse between this base stage and this collector electrode, triggers this side direction bipolar transistor, to discharge this static discharge current.Wherein, this first doped region is in this static discharge current during greater than a scheduled current, in order to reduce the potential difference of this contact to this reference potential.
When esd event betided on this contact, the face that connects between this base stage and this collector electrode is collapse earlier, and triggers this bipolar transistor.Then the current potential on this contact is maintained one first strangulation current potential.If electric current continues to increase to more than the scheduled current, first doped region adding effect together that this floats, and the current potential on this contact is maintained second a lower strangulation current potential.This first strangulation current potential and this scheduled current can be adjusted with the variation of layout, and the second strangulation current potential approximates 1.6 volts greatly.
Identical reason, the present invention provides a kind of electrostatic storage deflection (ESD) protection circuit of high current trigger in addition.Static discharge good fortune protection circuit of the present invention is electrically coupled to a contact and a reference potential, in order to discharge the static discharge current that produces from this contact.This electrostatic storage deflection (ESD) protection circuit includes the substrate of one first conductivity type, the well region of one second conductivity type, first doped region of one first conductivity type and second doped region of one second conductivity type.This substrate is electrically coupled to this reference potential.This well region is located in this substrate, and is electrically coupled to this contact.This first doped region is located at this well region surface, and is electrically coupled to this contact.This second doped region, what electricity floated is located in this substrate.
With regard to the circuit viewpoint, the present invention provides a kind of electrostatic storage deflection (ESD) protection circuit of high current trigger in addition, be coupled in a contact and a reference potential, in order to discharge the static discharge current that produces from this contact, this electrostatic discharge protection circuit includes second doped region of a bipolar transistor and one second conductivity type.This bipolar transistor includes an emitter, a base stage and a collector electrode.This emitter and this base stage all are electrically coupled to this contact, and this current collection polar system is constituted with the collector area of one first conductivity type and is electrically coupled to this reference potential.What this second doped region floated is located in this collector area, and connects face with this collector area formation one.
First conductivity type can be the n type, and second conductivity type then is the p type; Relative, if first conductivity type can be the p type, second conductivity type then is the n type.
The area that first advantage of the present invention is the ESD protection circuit is very little.Because suitable low of the second strangulation current potential, so what the power that consumes on the ESD protection circuit just can be suitable is little, the area that the ESD protection circuit takies just can be very little and be unlikely to burn wherein assembly.
Second advantage of the present invention does not have the bolt-lock incident when being the EMC/ESD test and takes place.As long as the current potential of the first strangulation current potential during, and the maximum current when this scheduled current test greater than EMC/ESD, then do not have the generation of bolt-lock incident during the EMC/ESD test greater than operate as normal.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and in conjunction with the accompanying drawings, be described in detail below: description of drawings:
Fig. 1 is the chip profile schematic diagram of first embodiment of ESD protection circuit of the present invention;
Fig. 2 A and 2B figure are the circuit diagram of Fig. 1;
The i-v curve figure of the ESD protection circuit that Fig. 3 is constituted for ESD protection circuit and known SCR among Fig. 1;
The i-v curve figure that Fig. 4 draws for the experimental data of the distance between different first doped region to the, three doped regions;
Fig. 5 A and 5B figure are second embodiment and the 3rd embodiment of ESD protection circuit of the present invention;
Fig. 6 A to the 6C figure is the 4th embodiment of ESD protection circuit of the present invention;
Fig. 7 A is the 5th embodiment of ESD protection circuit of the present invention;
Fig. 7 B is the circuit diagram of Fig. 7 A;
Fig. 8 is that first conductivity type is the n type and second conductivity type when being the p type, the embodiment of ESD protection circuit of the present invention;
When Fig. 9 is located at substrate for floating zone, the embodiment of ESD protection circuit of the present invention;
Figure 10 A or Figure 10 B are the equivalent circuit diagram of Fig. 9;
Figure 11 A or Figure 11 B are two kinds of trigger voltages that reduce the ESD protection circuits among Fig. 9
Embodiment;
Figure 12 A or Figure 12 B are two kinds of embodiment that reduce the trigger voltage of the ESD protection circuit among Fig. 9 with n type MOS transistor;
Figure 13 A to Figure 13 D is connecing of well region and substrate is provided with p type the 6th doped region on the face embodiment; And
Figure 14 is that first conductivity type is the n type and second conductivity type when being the p type, another embodiment of ESD protection circuit of the present invention.
The figure number explanation:
10,40 contacts, 12,42 substrates
14,44 well regions, 16,46 first doped regions
18,48 second doped regions, 20,50 the 3rd doped regions
22,52 the 4th doped regions, 28,58 the 5th doped regions
30,60 field oxides 78 the 6th doped region
Embodiment
See also Fig. 1, Fig. 1 is the chip profile schematic diagram of first embodiment of ESD protection circuit of the present invention.The invention provides an ESD protection circuit, in order to ESD electric current to a reference potential on the deenergized contact 10, as the VSS among Fig. 1.The ESD protection circuit includes the substrate 12 of one first conductivity type, the well region 14 of one second conductivity type, first doped region 16 of one first conductivity type, second doped region 18 and the 3rd doped region 20 of one second conductivity type and the 4th doped region 22 of one first conductivity type of one second conductivity type.Convenient in order to explain orally, first conductivity type is the p type, and second conductivity type is the n type.Substrate 12 sees through the 4th doped region 22, is electrically coupled to reference potential VSS.Just, the 4th doped region 22 is located at the surface of substrate 12, and as the ohmic contact of substrate 12, and the 4th doped region 22 is electrically coupled to reference potential VSS.Well region 14 sees through the 3rd doped region 20, is electrically coupled to contact 10.Just, the 3rd doped region 20 is located within the well region 14, and as the ohmic contact of well region 14, and the 3rd doped region 20 is electrically coupled to contact 10.The surface of being located at trap 14 that first doped region, 16 electricity float.First doped region 16, well region 14 and substrate 12 have just constituted a vertical pnp bipolar transistor.Second doped region 18 is located at substrate 12 surfaces, and is electrically coupled to reference potential VSS.Well region 14, substrate 12 and second doped region 18 have just constituted a side direction npn bipolar transistor.Resistance R-the sub that has comprised a parasitism in the substrate 12, relative well region 14 has also comprised the resistance R-well of a parasitism, as shown in Figure 1.
See also Fig. 2 A or Fig. 2 B, Fig. 2 A or Fig. 2 B are the circuit diagram of Fig. 1.By the viewpoint on the circuit, well region 14 (collector area), substrate 12 and second doped region 18 constitute collector electrode (collector), base stage (base) and the emitter (emitter) of side direction npn bipolar transistor respectively.Collector electrode sees through resistance R-well and is electrically coupled to contact 10, and base stage sees through resistance R-sub and is electrically coupled to reference potential VSS, and emitter then directly is electrically coupled to reference potential VSS.The collector electrode of vertical pnp bipolar transistor and base stage are electrically coupled to the base stage and the collector electrode of side direction npn bipolar transistor respectively, and the emitter of vertical pnp bipolar transistor do not receive any contact, present unsteady state, shown in Fig. 2 A.With another kind of angle, resistance R-well has a reverse diode 24 between the emitter of vertical pnp bipolar transistor, shown in Fig. 2 B.
See also Fig. 3, the i-v curve figure (IV curve) of the ESD protection circuit that Fig. 3 is constituted for ESD protection circuit and known SCR among Fig. 1.The IV curve chart of the ESD protection circuit in the solid line presentation graphs 1 among Fig. 3.When first doped region 16 among Fig. 1 directly was electrically coupled to contact 10, entire circuit just became the known ESD protection circuit that constitutes with SCR, and dotted line is exactly the IV curve chart of expression with the ESD protection circuit of SCR formation.The IV curve chart of SCR has been known result, is not going to repeat.And the result of the IV curve of ESD protection circuit of the present invention and known SCR is different, and at this, the section that is divided into I, II, III and IV is explained.
The I-V curve of I section and known SCR is the same, when the current potential of contact 10 arrives when connecing the breakdown voltage (evoked potential Vt just) of face between well region 14 and the substrate 12, side direction npn bipolar transistor is just connect the face leakage current and is triggered, and electric current begins to rise along with voltage.The actual physics principle of II section is unclear as yet, a kind of possible reason is first doped region 16 and the 20 beginning conductings of the 3rd doped region and the SCR that produces a parasitism, but parasitic required overall current gain (current gain) β and the no show 1 of SCR, so the current potential of contact 10 is clamped to one first strangulation current potential Vh1, shown in the II section.Because during strangulation, the present invention only has the conducting of a side direction npn bipolar transistor haply, and SCR is two bipolar transistor conductings, so the first strangulation current potential Vh1 can be than the strangulation current potential Vh-SCR height of SCR.
When electric current during greater than a scheduled current IL, well region 14 just can form high injection state (highinjection status), just the concentration product of the electron hole in the well region 14 greater than essential concentration (intrinsic concentration) square.At this moment, a large amount of electron holes is formed on connecing on the face between first doped region 16 and the well region 14, and the isolated effect of electricity that connects face reduces gradually, and the currentgain of parasitic SCR also moves closer to 1, so the current potential on the contact 10 just descends gradually, shown in the III section among Fig. 3.When a large amount of electric currents may and trigger the conducting of vertical pnp bipolar transistor greater than 0.7 volt by the pressure drop that well region 14 flows into 16 pairs of well regions 14 of first doped region, 16, the first doped regions.Under vertical pnp bipolar transistor and the equal conducting of side direction npn bipolar transistor, ESD protection circuit of the present invention can approximately be 1.6 volts, shown in the IV section with the voltage clamp of contact 10 built in second a very low strangulation current potential.And taking place, the required scheduled current IL of III section can control via empirical value and layout.
See also Fig. 4, the schematic diagram of Fig. 4 for drawing according to four groups of experimental datas.Four groups of curves that experimental data produced are respectively L1, L2, L3 and L4.Distance between first doped region, 16 to the 3rd doped regions 20 in the ESD protection circuit of generation L1, L2 and L3 curve is respectively 1um, 2um and 3um, and the L4 curve is the result who does not have the ESD protection circuit of first doped region 16.It is to the IV curve of collector electrode behind the emitter of a simple bipolar transistor and the base earth that the L4 curve can significantly be found out.The trend of curve L1 to L3 can be explained as follows.The distance that arrives between the 3rd doped region 20 that floats when first doped region 16 is far away more, the conducting chance that means first doped region 16 and the 3rd doped region 20 is low more, just need more electric current just can make first doped region 16 and 20 conductings of the 3rd doped region, shown in right one side of something of Fig. 4.Simultaneously, the distance that arrives between the 3rd doped region 20 that floats when first doped region 16 is far away more, mean that R-well is big more, just that is to say need be littler electric current can make the pressure drop between first doped region 16 and the 3rd doped region 20 arrive 0.7 volt to trigger SCR, shown in left one side of something of Fig. 4.
ESD protection circuit of the present invention has two parameters that can control, the first strangulation current potential Vh1 and scheduled current IL.A kind of state of suggestion is the supply current potential of power supply when making the first strangulation current potential Vh1 greater than the chip normal operation, and scheduled current IL is then between the maximum current when general ESD measuring current and EMC/ESD test.So, when carrying out the EMC/ESD test, ESD protection circuit of the present invention can discharge the ESD electric current via I section and II section, and after the EMC/ESD test, because power supply potential is less than the first strangulation current potential Vh1, the ESD protection circuit will be got back to the dress attitude of closing.When the general ESD that carries out Human Body Model (human body mode) and board pattern (machine mode) tested, the IV section that a large amount of electric currents can see through in the IV curve discharged, and good ESD protection is provided.
See also Fig. 5 A or Fig. 5 B, Fig. 5 A or Fig. 5 B are second embodiment and the 3rd embodiment of ESD protection circuit of the present invention.In order to reduce evoked potential Vt, the present invention provides two kinds of embodiment in addition, shown in Fig. 5 A or Fig. 5 B.Well region 14 and substrate 12 be formed to connect the 5th doped region 28 that face is provided with a n type.Because the doping content of the 5th doped region 28 is relative than the height of well region 14, the 5th doped region 28 formed pn connect the breakdown voltage of face can be lower, so the trigger voltage Vt of ESD protection circuit integral body just can reduce.5B figure has then additionally added a field oxide 30, is located at substrate 12 surfaces that are right after the 5th doped region 28.The substrate 12 of the below of field oxide 30 can add heavy dopant concentration usually, so the pn of the edge of field oxide 30 (edge) and the 5th doped region 28 intersections connects the breakdown voltage of face can be lower, so trigger voltage Vt also and then reduces.
See also Fig. 6 A, Fig. 6 A is the 4th embodiment of ESD protection circuit of the present invention.ESD protection circuit of the present invention can also include a MOS transistor M1, and M1 is located in the substrate 12, includes a grid and one source pole and drain electrode.Wherein, one source pole or drain electrode are electrically coupled to well region 14, and another source electrode or drain electrode are electrically coupled to reference potential VSS.For example, the one source pole of M1 or drain electrode are constituted with the 5th doped region 28, and another source electrode of M1 or drain electrode are constituted with second doped region 18, as shown in Figure 6A.And Fig. 6 B and Fig. 6 C are the equivalent circuit diagram of Fig. 6 A.The one source pole of M1 or drain electrode have two kinds of expression waies on circuit, shown in Fig. 6 B, a kind of is to be connected directly to contact 10, and another kind then is to see through resistance R-well to be electrically coupled to contact 10, shown in Fig. 6 C.M1 can reduce trigger voltage Vt, and this widely knows in known technology, in this few explanation.
See also Fig. 7 A and Fig. 7 B, Fig. 7 A is the fifth embodiment of the present invention, and Fig. 7 B is the circuit diagram of Fig. 7 A.The grid of M1 can be differentiated esd event and trigger the ESD protection circuit with a RC delay circuit, shown in Fig. 7 A.The ESD protection circuit also includes a resistance R G and a capacitor C G.The two ends of resistance R G are electrically coupled to grid and the reference potential VSS of M1 respectively, and capacitor C G two ends are electrically coupled to grid and the contact 10 of M1 respectively.As for circuit diagram only is that 6B figure or 6C figure add a RC delay circuit, shown in Fig. 7 B.When esd event betided contact 10, because the electric coupling effect of capacitor C G, the grid potential of M1 can be enhanced, and then triggered side direction npn bipolar transistor conducting ahead of time and discharge the ESD electric current.
Certain, first conductivity type is that the use of n type or p N-type semiconductor N only is engineer's selection, Fig. 1 to the 7 figure are that first conductivity type is that the p type and second conductivity type are the embodiment of n type, and Fig. 8 is that first conductivity type is that the n type and second conductivity type are the embodiment of p type.As shown in Figure 8, electrostatic discharge protection circuit of the present invention has comprised substrate 12b, the well region 14b of a p type, the first doped region 16b of a n type, the second doped region 18b and the 3rd doped region 20b of a p type and the 4th doped region 22b of a n type of a p type of a n type.The first doped region 16b, well region 14b and substrate 12b have constituted a npn bipolar transistor.Well region 14b, substrate 12b and the second doped region 18b have constituted a pnp bipolar transistor.The first doped region 16b still floats.Well region 14b sees through the 3rd doped region 20b and is coupled in contact 10b.The second doped region 18b is coupled in a reference potential VDD.Substrate 12b sees through the 4th doped region 22b and is coupled in reference potential VDD.Such arrangement also can reach the demand of ESD protection circuit.
The present invention also provides a kind of ESD protection circuit to realize that collector area adds the notion of an electrical opposite floating zone, as shown in Figure 9.Electrostatic storage deflection (ESD) protection circuit of the present invention is electrically coupled to a contact 40 and a reference potential VSS, in order to discharge the static discharge current that produces from contact 40.Electrostatic storage deflection (ESD) protection circuit includes the substrate 42 of a p type, the well region 44 of a n type, first doped region 46 of a p type, second doped region 48 of a n type, the 3rd doped region 50 of a n type and the 4th doped region 52 of a p type.Substrate 42 sees through the 4th doped region 52 formed ohmic contact, is electrically coupled to reference potential VSS.Well region 44 is located in the substrate 42, and is electrically coupled to contact 40.First doped region 46 is located at well region 44 surfaces, and sees through the 3rd doped region 50 formed ohmic contact, is electrically coupled to contact 40.Second doped region 48, what electricity floated is located in the substrate 42.First doped region 46, well region 44 and substrate 42 constitute emitter, base stage and the collector electrode of a pnp bipolar transistor respectively, so substrate 42 is called collector area again.Second doped region 48, that floats is located in this collector area, and connects face with this collector area formation one.Figure 10 A and Figure 10 B are the equivalent circuit diagram of Fig. 9.So the ESD protection circuit also can be reached the IV curve result of Fig. 3, its function preceding example explained, do not stating at this more.
Certain, in order to reduce the trigger voltage Vt of ESD protection circuit, the ESD protection circuit of Fig. 9 can have many kinds to change.First kind of variation is in well region 44 and substrate 42 formed the 5th doped regions 58 that a n type is set on the face that connect, shown in Figure 11 A.Because the concentration of the 5th doped region 58 is higher, so the formed breakdown voltage that connects face is lower.Second kind of variation is in the 5th doped region 58 sides a field oxide 60 to be set, shown in 11B figure.Substrate 42 under the field oxide 60 can add heavy dopant concentration usually, so the breakdown voltage of the edge of field oxide 60 intersection of the 5th doped region 58 (just with) can more reduce.The third variation is then to be that a n type MOS transistor is set in substrate 42, shown in Figure 12 A.The grid 62 of n type MOS transistor is coupled to reference potential VSS.Source electrode or drain electrode are the 5th doped region 58, see through well region 44, are coupled to contact 40.The source electrode of n type MOS transistor or drain electrode to the breakdown voltage of base stage (substrate) than the breakdown voltage of 44 pairs of substrates 42 of well region for low be state known in the field, so the arrangement of Figure 12 A can reduce the trigger voltage Vt of ESD protection circuit.And the grid 62 of n type MOS transistor also can directly not meet reference potential VSS, just receives reference potential VSS but see through a resistance R G, and grid 62 and 40 of contacts be provided with a capacitor C G, shown in Figure 12 B.The RC circuit that capacitor C G and resistance R G are formed can provide grid 62 1 voltages in order to the esd event on the detecting contact 40 then, in order to trigger the ESD protection circuit.
Shown in 13A, if n type the 5th doped region 58 changes p type the 6th doped region 78 into, the effect that reduces the trigger voltage of ESD protection circuit still exists.P type doping content in the 6th doped region 78 is than substrate 42 height.So it is low that the 6th doped region 78 and the well region 44 formed breakdown voltages that connect face also can come than the breakdown voltage of substrate 42 originally and the face that connects between the well region 44.In like manner, a field oxide 60 also can be set, and it is other to be next to the 6th doped region 78, shown in Figure 13 B in the surface of well region 44.Well region 44 under the field oxide 60 has denseer doping mostly and stops (channel stopper) to form passage, and to connect the breakdown voltage of face low so the pn at field oxide edge meets pn that the breakdown voltage of face can general well region 44 surfaces.A p type MOS transistor of being located in the well region 44 also can reduce the trigger voltage of ESD protection circuit of the present invention, shown in Figure 13 C.The grid 72 of p type MOS transistor is coupled in contact 40, and two source electrodes of p type MOS transistor or drain electrode are respectively first doped region 46 and the 6th doped region 78.RC delay circuit (RC delay circuit) also can add in the circuit among the 13C figure, as the detector of detecting esd event, shown in 13D.The grid 72 of p type MOS transistor sees through a resistance R G and is coupled in contact 40, and a capacitor C G then is set between the grid of p type MOS transistor and the reference potential VSS.When esd event took place at the beginning, the grid of p type MOS transistor can be coupled by capacitor C G and be in one and connect low current potential, thereby triggers whole ESD protection circuit.
Certain, first conductivity type is that the use of n type or p N-type semiconductor N only is engineer's selection, Fig. 9 to Figure 13 is that first conductivity type is that the p type and second conductivity type are the embodiment of n type, and Figure 14 is that first conductivity type is that the n type and second conductivity type are the embodiment of p type.As shown in figure 14, electrostatic discharge protection circuit of the present invention has comprised substrate 42b, the well region 44b of a p type, the first doped region 46b, the second doped region 48b of a p type, the 3rd doped region 50b of a p type and the 4th doped region 52b of a n type of a n type of a n type.The first doped region 46b, well region 44b and substrate 42b have constituted a npn bipolar transistor.Well region 44b, substrate 42b and the second doped region 48b have constituted a pnp bipolar transistor.The second doped region 48b still floats.Well region 44b sees through the 3rd doped region 50b and is coupled in contact 40b.The first doped region 46b is coupled in contact 40b.Substrate 52b sees through the 4th doped region 52b and is coupled in reference potential VDD.Such arrangement also can reach the demand of ESD protection circuit.
Generally speaking, to be to provide with a bipolar transistor be main ESD protection circuit to theme of the present invention.Bipolar transistor can be the npn bipolar transistor, also can be the pnp bipolar transistor.And, in the collector electrode of bipolar transistor, a floating zone that conductivity type is opposite with collector electrode being set, unsteady diode just reaches the purpose of the strangulation current potential when reducing high electric current.
With respect to known ESD protection circuit based on SCR, the first strangulation current potential Vh1 of the present invention height next than power supply potential, so can avoid based on the ESD protection circuit of SCR the bolt-lock problem that must face.With respect to known ESD protection circuit based on bipolar transistor, the present invention is provided with first a unsteady doped region more in the transistorized collector area of side direction npn, so when the ESD of high electric current test, can access second a very low strangulation current potential.The power consumption of ESD protection circuit of the present invention can reduce, thus can make with less chip area, and save cost.
Though the present invention discloses as above with a plurality of preferred embodiments; right its is not in order to limit the present invention; anyly know art technology person; without departing from the spirit and scope of the present invention; when doing a little change and retouching; therefore protection scope of the present invention ought be looked claim, and is as the criterion in conjunction with specification and the accompanying drawing person of defining.
Claims (33)
1. the electrostatic storage deflection (ESD) protection circuit of a high current trigger is electrically coupled to a contact and a reference potential, and in order to discharge the static discharge current that produces from this contact, this electrostatic storage deflection (ESD) protection circuit includes:
The substrate of one first conductivity type is electrically coupled to this reference potential;
The well region of one second conductivity type is located in this substrate, and is electrically coupled to this contact;
First doped region of one first conductivity type, electricity floats is located at this well region surface; And
Second doped region of one second conductivity type is located in this substrate, and is electrically coupled to this reference potential;
Wherein, the static discharge current on this contact provides a voltage that the face that connects between this well region and this substrate is collapsed, and triggers the side direction bipolar transistor that this well region, this substrate and this second doped region are constituted, to discharge this static discharge current;
Wherein, this first doped region is in this static discharge current during greater than a scheduled current, in order to reduce the potential difference of this contact to this reference potential.
2. electrostatic storage deflection (ESD) protection circuit as claimed in claim 1, wherein, this electrostatic storage deflection (ESD) protection circuit also includes the 3rd doped region of one second conductivity type, is located in this well region, is electrically coupled to this contact, as the ohmic contact of this well region.
3. electrostatic storage deflection (ESD) protection circuit as claimed in claim 1, wherein, this electrostatic storage deflection (ESD) protection circuit also includes the 4th doped region of one first conductivity type, is located at this substrate surface of contiguous this well region, be electrically coupled to this reference potential, as the ohmic contact of this substrate.
4. electrostatic storage deflection (ESD) protection circuit as claimed in claim 1, wherein, this first conductivity type is to be the p type, and this second conductivity type is the n type.
5. electrostatic storage deflection (ESD) protection circuit as claimed in claim 1, wherein, this electrostatic storage deflection (ESD) protection circuit also includes the 5th doped region of one second conductivity type, is located at connecing on the face of this well region and this substrate formation, in order to reduce the breakdown voltage of the face that connects between this well region and this substrate.
6. electrostatic storage deflection (ESD) protection circuit as claimed in claim 5, wherein, this electrostatic storage deflection (ESD) protection circuit also includes a field oxide, is located at the substrate surface that is next to the 5th doped region.
7. electrostatic storage deflection (ESD) protection circuit as claimed in claim 5, wherein, this electrostatic storage deflection (ESD) protection circuit also includes one first conductivity type mos transistor, be located in this substrate, include a grid and one source pole and drain electrode, wherein one source pole or drain electrode are electrically coupled to this well region, and another source electrode or drain electrode and this grid system are electrically coupled to this reference potential.
8. electrostatic storage deflection (ESD) protection circuit as claimed in claim 7, wherein, the one source pole of this first conductivity type mos transistor or drain electrode are constituted with the 5th doped region, and another source electrode of this first conductivity type mos transistor or drain electrode are constituted with this second doped region.
9. electrostatic storage deflection (ESD) protection circuit as claimed in claim 1, wherein, this electrostatic storage deflection (ESD) protection circuit also includes:
One first conductivity type mos transistor is located in this substrate, include a grid and
One source pole and drain electrode, wherein one source pole or drain electrode are electrically coupled to this well region, and another source electrode or drain electrode are electrically coupled to this reference potential;
One resistance, its two ends are electrically coupled to this grid and this reference potential respectively; And
One electric capacity, its two ends are electrically coupled to this grid and this contact respectively.
10. the electrostatic storage deflection (ESD) protection circuit of a high current trigger is coupled in a contact and a reference potential, and in order to discharge the static discharge current that produces from this contact, it includes:
One bipolar transistor includes an emitter, a base stage and a collector electrode, and wherein this emitter and this base stage all are electrically coupled to this reference potential, and this collector electrode is that the collector area with one second conductivity type is constituted and is electrically coupled to this contact; And
First doped region of one first conductivity type, unsteady is located in this collector area, and connects face with this collector area formation one;
Wherein, this static discharge current makes the face that the connects collapse between this base stage and this collector electrode, triggers this bipolar transistor, to discharge this static discharge current;
Wherein, this first doped region is in this static discharge current during greater than a scheduled current, in order to reduce the potential difference of this contact to this reference potential.
11. electrostatic storage deflection (ESD) protection circuit as claimed in claim 10, wherein, this electrostatic storage deflection (ESD) protection circuit also includes one first conductivity type mos transistor, include a grid and one source pole and drain electrode, wherein one source pole or drain electrode are electrically coupled to this collector electrode, and another source electrode or drain electrode and this grid are to be electrically coupled to this reference potential.
12. electrostatic storage deflection (ESD) protection circuit as claimed in claim 10, wherein, this electrostatic storage deflection (ESD) protection circuit also includes:
One first conductivity type mos transistor includes a grid and one source pole and drain electrode, and wherein one source pole or drain electrode are electrically coupled to contact, and another source electrode or drain electrode system are electrically coupled to this reference potential;
One resistance, its two ends are electrically coupled to this grid and this reference potential respectively; And
One electric capacity, its two ends are electrically coupled to this grid and this contact respectively.
13. electrostatic storage deflection (ESD) protection circuit as claimed in claim 10, wherein, this first conductivity type is to be the p type, and this second conductivity type is to be the n type.
14. as claim 1 or 10 described electrostatic storage deflection (ESD) protection circuit, wherein, this first conductivity type is to be the n type, and this second conductivity type is to be the p type.
15. the electrostatic storage deflection (ESD) protection circuit of a high current trigger is electrically coupled to a contact and a reference potential, in order to discharge the static discharge current that produces from this contact, this electrostatic storage deflection (ESD) protection circuit includes:
The substrate of one first conductivity type is electrically coupled to this reference potential;
The well region of one second conductivity type is located in this substrate, and is electrically coupled to this contact;
First doped region of one first conductivity type is located at this well region surface, and is electrically coupled to this contact; And
Second doped region of one second conductivity type, what electricity floated is located in this substrate;
Wherein, the static discharge current on this contact provides a voltage to make the face that connects collapse between this well region and this substrate, and triggers this first doped region, this well region and bipolar transistor that this substrate constituted, to discharge this static discharge current:
Wherein, this second doped region is in this static discharge current during greater than a scheduled current, in order to reduce the potential difference of this contact to this reference potential.
16. electrostatic storage deflection (ESD) protection circuit as claimed in claim 15, wherein, this electrostatic storage deflection (ESD) protection circuit also includes the 3rd doped region of one second conductivity type, is located in this well region, is electrically coupled to this contact, as the ohmic contact of this well region.
17. electrostatic storage deflection (ESD) protection circuit as claimed in claim 15, wherein, this electrostatic storage deflection (ESD) protection circuit also includes the 4th doped region of one first conductivity type, is located at this substrate surface of contiguous this well region, be electrically coupled to this reference potential, as the ohmic contact of this substrate.
18. electrostatic storage deflection (ESD) protection circuit as claimed in claim 15, wherein, this electrostatic storage deflection (ESD) protection circuit also includes the 5th doped region of one second conductivity type, is located at connecing on the face of this well region and this substrate formation, in order to reduce the breakdown voltage of the face that connects between this well region and this substrate.
19. electrostatic storage deflection (ESD) protection circuit as claimed in claim 18, wherein, this electrostatic storage deflection (ESD) protection circuit also includes a field oxide, is located at the substrate surface that is next to the 5th doped region.
20. electrostatic storage deflection (ESD) protection circuit as claimed in claim 18, wherein, this electrostatic storage deflection (ESD) protection circuit also includes one first conductivity type mos transistor, be located in this substrate, include a grid and one source pole and drain electrode, wherein one source pole or drain electrode are electrically coupled to this well region, and another source electrode or drain electrode and this grid are to be electrically coupled to this reference potential.
21. electrostatic storage deflection (ESD) protection circuit as claimed in claim 20, wherein, the one source pole of this first conductivity type mos transistor or drain electrode are constituted with the 5th doped region, and another source electrode of this MOS transistor or drain electrode are constituted with this second doped region.
22. electrostatic storage deflection (ESD) protection circuit as claimed in claim 15, wherein, this electrostatic storage deflection (ESD) protection circuit also includes:
One first conductivity type mos transistor is located in this substrate, includes a grid and one source pole and drain electrode, and wherein one source pole or drain electrode are electrically coupled to this well region, another source electrode or drain electrode and be electrically coupled to this reference potential;
One resistance, its two ends are electrically coupled to this grid and this reference potential respectively; And
One electric capacity, its two ends are electrically coupled to this grid and this contact respectively.
23. electrostatic storage deflection (ESD) protection circuit as claimed in claim 15, wherein, this electrostatic storage deflection (ESD) protection circuit includes the 6th doped region of one first conductivity type in addition, is located at connecing on the face of this well region and this substrate formation, in order to reduce the breakdown voltage of the face that connects between this well region and this substrate.
24. electrostatic storage deflection (ESD) protection circuit as claimed in claim 23, wherein, this electrostatic storage deflection (ESD) protection circuit includes a field oxide in addition, is located at the well region surface that is next to the 6th doped region.
25. electrostatic storage deflection (ESD) protection circuit as claimed in claim 24, wherein, this electrostatic storage deflection (ESD) protection circuit includes one second conductivity type mos transistor in addition, be located on this well region, include a grid and one source pole and drain electrode, wherein one source pole or drain electrode are electrically coupled to this substrate, and another source electrode or drain electrode and this grid are to be electrically coupled to this contact.
26. electrostatic storage deflection (ESD) protection circuit as claimed in claim 25, wherein, the one source pole of this second conductivity type mos transistor or drain electrode are constituted with the 6th doped region, and another source electrode of this MOS transistor or drain electrode are constituted with the 3rd doped region.
27. electrostatic storage deflection (ESD) protection circuit as claimed in claim 23, wherein, this electrostatic storage deflection (ESD) protection circuit includes in addition:
One second conductivity type mos transistor includes a grid and one source pole and drain electrode, and wherein one source pole or drain electrode are electrically coupled to this contact, and another source electrode or drain electrode are to be electrically coupled to this reference potential;
One electric capacity, its two ends are electrically coupled to this grid and this reference potential respectively; And
One resistance, its two ends are electrically coupled to this grid and this contact respectively.
28. electrostatic storage deflection (ESD) protection circuit as claimed in claim 15, wherein, this first conductivity type is to be the p type, and this second conductivity type is to be the n type.
29. electrostatic storage deflection (ESD) protection circuit as claimed in claim 15, wherein, this first conductivity type is to be the n type, and this second conductivity type is to be the p type.
30. the electrostatic storage deflection (ESD) protection circuit of a high current trigger is coupled in a contact and a reference potential, in order to discharge the static discharge current that produces from this contact, it includes:
One bipolar transistor includes an emitter, a base stage and a collector electrode, and wherein this emitter and this base stage all are electrically coupled to this contact, and this current collection polar system is constituted with the collector area of one first conductivity type and is electrically coupled to this reference potential; And
Second doped region of one second conductivity type, unsteady is located in this collector area, and connects face with this collector area formation one;
Wherein, this static discharge current makes the face that the connects collapse between this base stage and this collector electrode, triggers this bipolar transistor, to discharge this static discharge current;
Wherein, this second doped region is in this static discharge current during greater than a scheduled current, in order to reduce the potential difference of this contact to this reference potential.
31. electrostatic storage deflection (ESD) protection circuit as claimed in claim 30, wherein, this electrostatic storage deflection (ESD) protection circuit includes one first conductivity type mos transistor in addition, include a grid and one source pole and drain electrode, wherein one source pole or drain electrode are electrically coupled to this collector electrode, and another source electrode or drain electrode and this grid system are electrically coupled to this reference potential.
32. electrostatic storage deflection (ESD) protection circuit as claimed in claim 30, wherein, this electrostatic storage deflection (ESD) protection circuit includes in addition:
One first conductivity type mos transistor includes a grid and one source pole and drain electrode, and wherein one source pole or drain electrode are electrically coupled to contact, and another source electrode or drain electrode are to be electrically coupled to this reference potential;
One resistance, its two ends are electrically coupled to this grid and this reference potential respectively; And
One electric capacity, its two ends are electrically coupled to this grid and this contact respectively.
33. electrostatic storage deflection (ESD) protection circuit as claimed in claim 30, wherein, this first conductivity type is to be the p type, and this second conductivity type is to be the n type.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB011097906A CN1303686C (en) | 2001-04-24 | 2001-04-24 | High-current triggered electrostatic discharge protector |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB011097906A CN1303686C (en) | 2001-04-24 | 2001-04-24 | High-current triggered electrostatic discharge protector |
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| Publication Number | Publication Date |
|---|---|
| CN1383207A CN1383207A (en) | 2002-12-04 |
| CN1303686C true CN1303686C (en) | 2007-03-07 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB011097906A Expired - Fee Related CN1303686C (en) | 2001-04-24 | 2001-04-24 | High-current triggered electrostatic discharge protector |
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Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100420014C (en) * | 2004-06-14 | 2008-09-17 | 旺宏电子股份有限公司 | Static discharge protective circuit |
| CN101777554B (en) * | 2009-01-12 | 2011-08-24 | 立锜科技股份有限公司 | Electrostatic protection element of bidirectional silicon-controlled rectifier |
| CN102290418B (en) * | 2010-06-21 | 2015-12-16 | 慧荣科技股份有限公司 | Electrostatic discharge protective equipment |
| CN102142440B (en) * | 2010-12-30 | 2012-08-22 | 浙江大学 | Thyristor device |
| US8390070B2 (en) * | 2011-04-06 | 2013-03-05 | Nanya Technology Corp. | Electrostatic discharge protection device and electrostatic discharge protection circuit thereof |
| TWI724256B (en) * | 2017-11-24 | 2021-04-11 | 源芯半導體股份有限公司 | Transient voltage suppressor |
| TWI710096B (en) * | 2019-09-04 | 2020-11-11 | 智原科技股份有限公司 | Electrostatic discharge protection apparatus |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1213177A (en) * | 1997-09-26 | 1999-04-07 | Lg半导体株式会社 | Electrostatic discharge protection circuit |
| US5962876A (en) * | 1998-04-06 | 1999-10-05 | Winbond Electronics Corporation | Low voltage triggering electrostatic discharge protection circuit |
-
2001
- 2001-04-24 CN CNB011097906A patent/CN1303686C/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1213177A (en) * | 1997-09-26 | 1999-04-07 | Lg半导体株式会社 | Electrostatic discharge protection circuit |
| US5962876A (en) * | 1998-04-06 | 1999-10-05 | Winbond Electronics Corporation | Low voltage triggering electrostatic discharge protection circuit |
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| CN1383207A (en) | 2002-12-04 |
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