CN1289920C - Earthquake data acquisition board for geophysical exploration - Google Patents
Earthquake data acquisition board for geophysical exploration Download PDFInfo
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- CN1289920C CN1289920C CN 200510066006 CN200510066006A CN1289920C CN 1289920 C CN1289920 C CN 1289920C CN 200510066006 CN200510066006 CN 200510066006 CN 200510066006 A CN200510066006 A CN 200510066006A CN 1289920 C CN1289920 C CN 1289920C
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Abstract
The present invention discloses an earthquake data collecting board for geophysical exploration. The present invention comprises two sections: the first section is provided with an earthquake data collecting interface, a prime amplifier module, a selection control module and a simulation power supply, and the second section is provided with an earthquake data collecting nest plate, an on-site programmable logic gate array, a clock source, a digital power supply and a communication interface; socket connectors for mutual communication is arranged between the two sections; the prime amplifier module adopts a two-stage amplifier structure; the communication interface adopts an RS485 cable interface; the on-site programmable logic gate array can realize the reception and the processing of ascending data format conversion and descending control signals. When the earthquake data collecting board is used, the calculation speed of data collection can be improved, earthquake exploration with high precision and high resolution can be realized, and earthquake data with high quality can be collected.
Description
Technical field
The present invention relates to the geophysical survey field, especially relate to a kind of earthquake data acquisition board that is used for geophysical survey.
Background technology
Earthquake data acquisition and register system are equipment the most key in the oil seismic exploration, seismic exploration requires distortionless receiving record seismic event, and earthquake data acquisition and register system must have great dynamic range, low noise, abilities such as low drift, broadband and compacting interference wave; Therefore whether the collection plate function of front end is perfect, and the quality of record data quality is directly connected to the quality of final image data.
The collection plate of existing earthquake data acquisition and register system, because it adopts traditional computed in software mode, it is the microcontroller processing mode, so arithmetic speed is not high, and owing to adopt traditional electronic devices and components and method for designing, so equipment is outmoded, be difficult to finish the seismic prospecting of high-accuracy high-resolution.Thereby the performance of traditional earthquake data acquisition board can't satisfy the more seismic prospecting requirement of high performance index, is difficult to collect the high geological data data of quality.
Summary of the invention
The technical issues that need to address of the present invention provide a kind of earthquake data acquisition board that is used for geophysical survey, adopt this earthquake data acquisition board, can improve the arithmetic speed of data acquisition, realize the seismic prospecting of high-accuracy high-resolution, and collect the high geological data data of quality.
In order to solve the problems of the technologies described above, the invention provides described earthquake data acquisition board and be divided into two parts, first is provided with the earthquake data acquisition interface, the prime amplifier module that links to each other with the earthquake data acquisition interface, the selection control module that links to each other with the prime amplifier module, analog power for prime amplifier module and the power supply of selection control module, second portion is provided with the earthquake data acquisition nest plate, the field programmable gate array that links to each other with the earthquake data acquisition nest plate, be connected with field programmable gate array with the earthquake data acquisition nest plate respectively and the clock source of clock signal is provided, digital power for earthquake data acquisition nest plate and field programmable gate array power supply, and the communication interface that links to each other and be used for communicating with the field programmable gate battle array with external unit, between two parts, be provided with the connector that is used for intercoming mutually, wherein, described prime amplifier module adopts the two-stage amplifier structure, first order amplifier is used to collect the signal of piezoelectric sensor, and second level amplifier then is used to realize conversion and the gain selection of differential signal to single-ended signal.
Further, the present invention also has following characteristics: described first order amplifier adopts the difference I/O mode, form by positive signal passage and negative signal passage that structure is identical, and each passage includes by integrated transporting discharging, input resistance, feedback resistance and feedback capacity and constitutes, wherein feedback capacity adopts the metallization polycarbonate capacitor, the electric capacity precision is 1%, and capability value is 0.27 μ F.
Further, the present invention also has following characteristics: described second level amplifier adopts difference to import the mode of unidirectional output, form by positive signal passage, negative signal passage and integrated transporting discharging, each passage constitutes by analog multichannel switch, input resistance, build-out resistor, the positive signal passage links to each other with the backward end of integrated transporting discharging, the negative signal passage links to each other with the forward end of integrated transporting discharging, and the analog multichannel switch output terminal of forward channel links to each other with the output signal end of second level amplifier, the analog multichannel switch output head grounding of backward channel; Analog multichannel switch is selected corresponding build-out resistor according to the gain control signal that receives, thereby realizes the gain selection.
Further, the present invention also has following characteristics: this collection plate adopts double-deck buckle structure, and the module of described first and second portion is separately positioned on wherein one deck buckle.
Further, the present invention also has following characteristics: the special-purpose earthquake data acquisition nest plate that described earthquake data acquisition nest plate adopts CS4373, CS5376A and the CS5372 chip by U.S. Cirrus Logic to constitute.
Further, the present invention also has following characteristics: the crystal oscillator of 32.768MHz is adopted in described clock source, the CS5376A chip of the clock signal of its output 32.768MHz to field programmable gate array and the earthquake data acquisition nest plate.
Further, the present invention also has following characteristics: after described CS5376A chip carries out frequency division with the 32.768MHz clock signal that receives, the clock signal of output 2.048MHz is to the CS5372 chip, after field programmable gate array can carry out frequency division with the 32.768MHz clock signal that receives, the clock signal of output 1.024MHz was to communication interface.
Further, the present invention also has following characteristics: described field programmable gate array can be realized the reception and the processing of upstream data format conversion, downgoing control signal, and wherein the reception of downgoing control signal and processing comprise the configuration and the command analysis function of analog gate control, self check waveform generation, control earthquake data acquisition nest plate.
Compared with prior art, the present invention has the following advantages:
The present invention fully uses modern electronic technology, the hardware logic design of more employing high speed field programmable gate arrays substitutes traditional computed in software, and adopt parallel data to handle and the pipeline organization circuit design, improved the arithmetic speed of data acquisition greatly; In addition, the present invention also adopts the special-purpose earthquake-capturing nest plate of function admirable, make that this earthquake data acquisition board has great dynamic range, system noise is low, intertrack crosstalk is little, harmonic distortion is little, the common-mode rejection ratio advantages of higher, characteristic requirement based on seismic prospecting, the present invention can realize the seismic prospecting of high-accuracy high-resolution, and can collect the high geological data data of quality.
Description of drawings
Fig. 1 is the structural representation of one deck buckle among the present invention;
Fig. 2 is the structural representation of another layer buckle among the present invention;
Fig. 3 is the structural representation of first order amplifier among the present invention;
Fig. 4 is the structural representation of second level amplifier among the present invention;
Fig. 5 is the structural representation of analog-to-digital conversion module and interface module among the present invention;
Fig. 6 is clock distribution figure among the present invention;
Fig. 7 is the form of upstream data that field programmable gate array is changed among the present invention;
Fig. 8 is the high-level schematic functional block diagram of field programmable gate array among the present invention.
Fig. 9 is a voltage distribution situation synoptic diagram among the present invention.
Embodiment
For understanding the present invention in depth, the present invention is described in detail below in conjunction with drawings and the specific embodiments.
The earthquake data acquisition board that the present invention is used for geophysical survey adopts double-deck buckle structure, is provided with to be used for the connector that double-deck buckle intercoms mutually between double-deck buckle.One deck buckle is provided with earthquake data acquisition interface, prime amplifier module, selects control module and analog power, as shown in Figure 1, wherein, earthquake data acquisition interface (not showing on the figure) links to each other with the prime amplifier module, the prime amplifier module adopts the two-stage amplifier structure, wherein first order amplifier is used to collect the signal of piezoelectric sensor, second level amplifier then is used to realize conversion and the gain selection of differential signal to single-ended signal, select control module to comprise simulation multiselect switch and control module, be used to control the prime amplifier module.
As shown in Figure 3, first order amplifier adopts the difference I/O mode, be made up of positive signal passage and negative signal passage that structure is identical, and each passage includes by integrated transporting discharging, input resistance, feedback resistance R
fWith feedback capacity C
fConstitute.The characteristics of this circuit are that the open-loop gain of output voltage and operational amplifier is irrelevant, only are decided by charge Q and feedback capacity C that piezoelectric sensor is collected
fSize, have fabulous stability.In order to obtain necessary measuring accuracy, require feedback capacity to have excellent temperature stability and time stability.In the present embodiment, it is the metallization polycarbonate capacitor of 0.27uF that feedback capacity adopts electric capacity precision 1% and capability value, can satisfy the needs of measurement.Feedback resistance R
fRealize the DC feedback function, can reduce drift, make the amplifier working stability.In addition, TS+ and TS-refer to the input of self-checking signal.
As shown in Figure 4, second level amplifier adopts difference to import the mode of unidirectional output, form by positive signal passage, negative signal passage and integrated transporting discharging, each passage constitutes by analog multichannel switch, input resistance, build-out resistor, the positive signal passage links to each other with the backward end of integrated transporting discharging, the negative signal passage links to each other with the forward end of integrated transporting discharging, and the analog multichannel switch output terminal of forward channel links to each other with the output signal end SIGNAL_OUT of second level amplifier, the analog multichannel switch output head grounding of backward channel; Control end C1, the C2 of analog multichannel switch receives and comes from the gain control signal GAIN_CONTROL that selects control module, and selects corresponding build-out resistor according to this gain control signal, realizes the gain selection.
As Fig. 2 and shown in Figure 5, another layer buckle is provided with special-purpose earthquake data acquisition nest plate, FPGA (Field Programmable Gate Array, field programmable gate array), the clock source, digital power and communication interface, wherein, special-purpose earthquake data acquisition nest plate is by the CS4373 of U.S. Cirrus Logic (CirrusLogic Inc.), CS5376A and CS5372 chip constitute, the CS4373 chip is highly integrated difference output digital to analog converter (DAC), be applicable to the high-precision low frequency measurement of test system, have small size, low-power consumption, optional decay, characteristics such as many outputs and programmable test pattern; The CS5372 chip is single channel and the binary channels 4 rank Delta-Sigma modulators that are used for geophysics and sonar, compares with existing industrial modulator standard, and it has higher dynamic range, lower total harmonic distortion and extremely low consumed power; The CS5376A chip is multi-functional digital filtering chip, can realize effective filtering for 4 Delta-Sigma modules at the most, therefore, by the Delta-Sigma module of CS5376A chip, CS5372 chip and the Delta-Sigma test digital to analog converter (DAC) of CS4373 are combined, can realize synchronous high resolving power multi-channel measurement, improve the test performance of seismic prospecting greatly.
Among Fig. 2, DAC realizes that by the CS4373 chip this DAC links to each other with FPGA; ADC realizes that by two CS5372 chips it links to each other with digital filtering module; Digital filtering module realizes that by the CS5376A chip it links to each other with memory module (ROM) with FPGA respectively; FPGA adopts the chip of U.S. A Ertela, and EPC is the configuration flash memory of this FPGA; Communication interface adopts the RS485 cable interface.
Among Fig. 5, DC_DC Regulator is the direct supply modular converter, be used for of the conversion of 375V direct current to the 12V direct current, REF is the reference configuration voltage of CS5372 chip, EEPROM is the electrically-erasable ROM (read-only memory), is used to dispose the CS5376A chip, adopts two CS5372 chips to carry out 4 channel data collections among the present invention, the CS5376A chip is controlled two CS5372 chips, and FPGA controls CS5376A chip and RS485 cable interface respectively.
In the present embodiment, the crystal oscillator of 32.768MHz is adopted in the clock source, as shown in Figure 6, the clock signal of its output 32.768MHz is to FPGA and CS5376A chip, after the CS5376A chip carries out frequency division with the 32.768MHz clock signal that receives, export the clock signal of 2.048MHz to the CS5372 chip by the MCLK port; FPGA carries out frequency division with the 32.768MHz clock signal that receives and obtains internal clock signal, and the frequency of this internal clock signal includes 1.024MHz, 2.048MHz, 4.096MHz and 16.384MHz; The clock signal of FPGA output 1.024MHz makes that to the RS485 cable interface transfer clock frequency of RS485 cable interface is 1.024MHz; Other internal clock signal offers other module among the present invention respectively.
And the clock frequency default value of the SCK1 port of SPI1 on the CS5376A chip (Serial Peripheral Interface 1, serial peripheral interface module 1) is 1.024MHz; The optional 32KHz of clock frequency, 128KHz, 512KHz, 1.024MHz, 2.048MHz and the 4.096MHz of the SCK2 port of SPI2 (SerialPeripheral Interface 2, serial peripheral interface module 2) are several; The clock frequency of the TBCLK port of test bit stream clock module (Test Bit Stream Clock) is 1/8 of a CS5376A chip internal clock frequency, and maximal value is 2.048MHz; The SDCLK port of serial data port module (Serial Data Port) provides clock signal by external unit, and frequency can be 62.5Hz～4K OWR (word output speed).
FPGA can be used for realizing the reception and the processing of upstream data format conversion, downgoing control signal among the present invention, as shown in Figure 8, the function sub-modules of this FPGA includes Data Format Transform submodule, digital filtering chip controls submodule, self check waveform generation submodule, command analysis submodule and analog gate and other controlling sub.Wherein, the upstream data format conversion is meant that FPGA will collect data-switching and become as shown in Figure 7 UART (universal asynchronous reception/transmission) formatted data, and is transferred to the transmission board of digital packets by the RS485 cable interface, and the bit stream clock is 1MHz; The reception of downgoing control signal and processing finger print are intended gate control (being resonance-amplifier gain and self check control etc.), control the configuration (read-write of promptly controlling EEPROM is with functions such as configuration CS5376 chip and RESET) of special-purpose earthquake data acquisition nest plate, produce self check waveform (being that itself and DAC acting in conjunction provide the self-checking signal), and the command analysis of finishing various Auto-Sensing Modes.Wherein, the self check sinusoidal signal is to be obtained after the DAC digital-to-analog conversion by digital signal among the FPGA, exports TS+, TS-input end in the amplification of the prime amplifier first order then to, and command signal relevant with self check control in the native system is as shown in table 1.
Table 1: self check control signal classification table
| The control signal name | Logical value | Realize function |
| PH_CONN | 0 | Disconnection is connected with |
| 1 | Before put with sensor and link to each other | |
| PH_FAKE | 0 | Do not insert |
| 1 | Insert artificial capacitor | |
| TS1 | 0 | PH1 passage |
| 1 | PH1 passage input termination test signal | |
| TS2 | 0 | PH2 passage |
| 1 | PH2 passage input termination test signal | |
| TS3 | 0 | PH3 passage |
| 1 | PH3 passage input termination test signal | |
| TS4 | 0 | PH4 passage |
| 1 | PH4 passage input termination test signal | |
| GN_CON1，GN_CON0 | 0，0 | |
| 0，1 | Gain | |
| 1，0 | Gain | |
| 1，1 | Gain 24dB |
Analog power adopts the linear power supply chip among the present invention, with input ± the 12V voltage transitions is ± 8V, ± 3V ,+aanalogvoltage of 5V; Digital power adopt switching power source chip, general ± 12V voltage transitions be+1.5V ,+3.3V ,+3V ,+digital voltage of 5V.
As shown in Figure 9, adopt the LT3765 chip input voltage of 12V to be converted to the digital voltage of 5V, export RS485 cable interface chip and MAX1972 chip to, the digital voltage of exporting 3.3V and 1.5V respectively through the conversion of MAX1972 chip is to FPGA again, and wherein the digital voltage of 3.3V also exports DAC and digital filtering chip respectively to.Adopt the LM78M08 chip input voltage of 12V to be converted to the aanalogvoltage of 8V, the aanalogvoltage that is converted to 5V behind the 78M05 chip exports DAC to, adopt the input voltage of LM79M08 chip general-12V to be converted in addition-aanalogvoltage of 8V, so the aanalogvoltage of general ± 8V exports the prime amplifier module to; The aanalogvoltage of 8V is converted to the aanalogvoltage of 3V behind the LM1086 chip, and the aanalogvoltage of-8V is converted to behind the LM337 chip-aanalogvoltage of 3V, so the aanalogvoltage of general ± 8V exports ADC to; Be converted to the digital voltage of 3V behind the analog electrical crimping inductance with 3V and export digital filtering chip and ADC respectively to.
Claims (9)
1, a kind of earthquake data acquisition board that is used for geophysical survey, it is characterized in that: described earthquake data acquisition board is divided into two parts, first is provided with the earthquake data acquisition interface, the prime amplifier module that links to each other with the earthquake data acquisition interface, the selection control module that links to each other with the prime amplifier module, analog power for prime amplifier module and the power supply of selection control module, second portion is provided with the earthquake data acquisition nest plate, the field programmable gate array that links to each other with the earthquake data acquisition nest plate, be connected with field programmable gate array with the earthquake data acquisition nest plate respectively and the clock source of clock signal is provided, digital power for earthquake data acquisition nest plate and field programmable gate array power supply, and the communication interface that links to each other and be used for communicating with the field programmable gate battle array with external unit, between two parts, be provided with the connector that is used for intercoming mutually, wherein, described prime amplifier module adopts the two-stage amplifier structure, first order amplifier is used to collect the signal of piezoelectric sensor, and second level amplifier then is used to realize conversion and the gain selection of differential signal to single-ended signal.
2, the earthquake data acquisition board that is used for geophysical survey according to claim 1, it is characterized in that: described first order amplifier adopts the difference I/O mode, form by positive signal passage and negative signal passage that structure is identical, and each passage includes by integrated transporting discharging, input resistance, feedback resistance and feedback capacity and constitutes.
3, the earthquake data acquisition board that is used for geophysical survey according to claim 2 is characterized in that: described feedback capacity adopts the metallization polycarbonate capacitor, and the electric capacity precision is 1%, and capability value is 0.27 μ F.
4, the earthquake data acquisition board that is used for geophysical survey according to claim 1, it is characterized in that: described second level amplifier adopts difference to import the mode of unidirectional output, by the positive signal passage, negative signal passage and integrated transporting discharging are formed, each passage is by analog multichannel switch, input resistance, build-out resistor constitutes, the positive signal passage links to each other with the backward end of integrated transporting discharging, the negative signal passage links to each other with the forward end of integrated transporting discharging, and the analog multichannel switch output terminal of forward channel links to each other with the output signal end of second level amplifier, the analog multichannel switch output head grounding of backward channel; Analog multichannel switch is selected corresponding build-out resistor according to the gain control signal that receives, thereby realizes the gain selection.
5, the earthquake data acquisition board that is used for geophysical survey according to claim 1, it is characterized in that: this collection plate adopts double-deck buckle structure, and the module of described first and second portion is separately positioned on wherein one deck buckle.
6, the earthquake data acquisition board that is used for geophysical survey according to claim 1 is characterized in that: the special-purpose earthquake data acquisition nest plate that described earthquake data acquisition nest plate adopts CS4373, CS5376A and the CS5372 chip by U.S. Cirrus Logic to constitute
7, the earthquake data acquisition board that is used for geophysical survey according to claim 6, it is characterized in that: the crystal oscillator of 32.768MHz is adopted in described clock source, the CS5376A chip of the clock signal of its output 32.768MHz to field programmable gate array and the earthquake data acquisition nest plate.
8, the earthquake data acquisition board that is used for geophysical survey according to claim 7, it is characterized in that: after described CS5376A chip carries out frequency division with the 32.768MHz clock signal that receives, the clock signal of output 2.048MHz is to the CS5372 chip, after field programmable gate array can carry out frequency division with the 32.768MHz clock signal that receives, the clock signal of output 1.024MHz was to communication interface.
9, the earthquake data acquisition board that is used for geophysical survey according to claim 6, it is characterized in that: described field programmable gate array can be realized the reception and the processing of upstream data format conversion, downgoing control signal, and wherein the reception of downgoing control signal and processing comprise the configuration and the command analysis function of analog gate control, self check waveform generation, control earthquake data acquisition nest plate.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200510066006 CN1289920C (en) | 2005-04-19 | 2005-04-19 | Earthquake data acquisition board for geophysical exploration |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200510066006 CN1289920C (en) | 2005-04-19 | 2005-04-19 | Earthquake data acquisition board for geophysical exploration |
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Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101382597B (en) * | 2008-09-18 | 2011-03-30 | 中国海洋石油总公司 | High speed data communication plate for geophysics exploration |
| US8570829B2 (en) * | 2009-12-22 | 2013-10-29 | Pgs Geophysical As | Depth steerable seismic source array |
| CN103048682B (en) * | 2011-10-16 | 2016-08-03 | 山西晋明海科技开发有限公司 | The multimode starter of earthquake data acquisition |
| CN102512174B (en) * | 2011-11-21 | 2014-10-01 | 中国人民解放军第四军医大学 | Portable type physical ability consumption and physiological parameter monitoring instrument |
| CN103147745B (en) * | 2013-02-22 | 2016-03-23 | 电子科技大学 | A kind of three-dimensional acoustic wave log data high-speed transfer device based on LVDS technology |
| CN105448071A (en) * | 2015-11-02 | 2016-03-30 | 中国科学技术大学 | Data transceiver and data transmission system |
| CN106772611A (en) * | 2016-11-28 | 2017-05-31 | 中国海洋石油总公司 | One kind collection cable |
| CN107170349A (en) * | 2017-07-19 | 2017-09-15 | 东华理工大学 | Exploration geophysics teaching experiment data harvester based on wireless network |
| CN109343109B (en) * | 2018-11-27 | 2024-03-08 | 四川省地震局水库地震研究所 | Embedded dominant second-order pole type seismic data collector |
| CN109946684B (en) * | 2019-03-08 | 2022-10-25 | 哈尔滨工程大学 | Broadband sonar transmitter with large output dynamic range |
| CN111443383B (en) * | 2020-04-07 | 2023-02-10 | 中国地震局地震预测研究所 | Data acquisition device for coal mine |
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