CN105448071A - Data transceiver and data transmission system - Google Patents
Data transceiver and data transmission system Download PDFInfo
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- CN105448071A CN105448071A CN201510738077.3A CN201510738077A CN105448071A CN 105448071 A CN105448071 A CN 105448071A CN 201510738077 A CN201510738077 A CN 201510738077A CN 105448071 A CN105448071 A CN 105448071A
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- G—PHYSICS
- G08—SIGNALLING
- G08C—TRANSMISSION SYSTEMS FOR MEASURED VALUES, CONTROL OR SIMILAR SIGNALS
- G08C19/00—Electric signal transmission systems
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- G—PHYSICS
- G08—SIGNALLING
- G08C—TRANSMISSION SYSTEMS FOR MEASURED VALUES, CONTROL OR SIMILAR SIGNALS
- G08C2200/00—Transmission systems for measured values, control or similar signals
Abstract
The invention discloses a data transceiver and a data transmission system. The data transceiver comprises a driver and a receiver, wherein the driver comprises an adjustable current source, a first single-pole double-throw switch connected with the adjustable current source and a second single-pole double-throw switch connected with the adjustable current source; the adjustable current source is used for controlling the driving capacity by adjusting the current; the connection directions of the first single-pole double-throw switch and the second single-pole double-throw switch are controlled according to the high/low level of a digital signal received by the data transceiver. The data transceiver realizes dynamic adjustment and transmission driving, thus reducing power consumption of data transmission.
Description
Technical field
The present invention relates to technical field of data transmission, particularly relate to a kind of data collector and data transmission system.
Background technology
At present, in large-scale geophysical survey system, the acquisition station of such as geophysical survey, wave detector cascade mostly in a serial fashion, its data produced are transmitted and are converged.And the power consumption of data transceiver circuit is that the decay to signal is directly proportional with the hop rate of data and cable, so high performance index just means high power consumption.Geophysical survey system is very responsive to the demand of power supply, and stations at different levels body needs to reduce power consumption to increase the working time as far as possible, changes to reduce the manpower and materials and the consumption of time that power supply brings.Therefore, a kind of adaptation geophysical survey environment is needed badly, the data transmission scheme of low-power consumption.
The technology of serial communication of at present conventional transmission of seismic data method mainly low speed, as RS-485, LVDS etc.RS-485 is the specification formulated by Electronic Industries Association's (ElectronicIndustriesAssociation is abbreviated as EIA), and it is a kind of conventional remote differential signal transmission agreement, uses voltage differential signal to transmit.The advantages such as RS-485 has long transmission distance, and transmission speed is high, and antijamming capability is strong, its exemplary block diagram as shown in Figure 1.RS-485 adopts differential signal negative logic, and-2V ~-6V represents " 0 ", and+2V ~+6V represents " 1 ", and driver changes driving voltage according to input signal, guarantees to produce in the build-out resistor of receiving end the pressure reduction being greater than 200mV.For ensureing enough driving forces, the voltage of receiving end build-out resistor can reach ± about 1.5V, which results in larger power consumption.Consider the dynamic power consumption of driver, under typical 4Mbps transfer rate, the power consumption of a pair RS-485 transceiver is greater than 70mW.
Relative with RS-485, low-voltage differential signal (LowVoltageDifferentialSignal, be abbreviated as LVDS) to upload defeated at cable be current difference signal, the electric current of driver drives is through the build-out resistor of the receiving end of differential transfer cable, form loop, drive current can produce voltage difference at the two ends of build-out resistor, obstructed according to direction of current, and the voltage difference at build-out resistor two ends is also different.Receiving end produces corresponding 0 and 1 digital signal according to the voltage at build-out resistor two ends, completes data transmission.The representative value of drive current is 3.5mA, and the representative value of end build-out resistor is 100 Ω, and the typical pressure difference at build-out resistor two ends is ± 350mV, and its typical structure as shown in Figure 2.The signal of the low amplitude of oscillation makes LVDS have higher transfer rate, decreases noise simultaneously.The build-out resistor pressure reduction of typical 350mV calculates, and under 4Mbps transfer rate, the power consumption of a pair LVDS transceiver is about 30mW.
The deployment of a sensor network affects by several factors.Node wherein can not always be evenly distributed in a panel region, so the distance between node may be different; To different sampling rates, the data transfer rate needed for link also likely changes; To the cable of diverse location, the disturbed condition of suffered neighbourhood noise is also likely different.Cable is longer, and signal frequency is higher, or neighbourhood noise is larger, and the signal attenuation caused is more serious, and required data transmission drives intensity larger.Most transceiver, such as RS-485 and LVDS etc., in order to meet specific communication standard, intensity is driven to be changeless, so for different length of cable, data rate and noise circumstance, the driving intensity of existing data collector is constant, and the power consumption of data transmission is too large, big energy-consuming.
Summary of the invention
The object of this invention is to provide a kind of data collector and data transmission system, drive to realize dynamic conditioning transmission, reduce the power consumption of data transmission.
For solving the problems of the technologies described above, the invention provides a kind of data collector, described data collector comprises:
Driver; The second single-pole double-throw switch (SPDT) that described driver comprises adjustable current source, the first single-pole double-throw switch (SPDT) be connected with described adjustable current source and is connected with described adjustable current source; Described adjustable current source is used for by regulating electric current to control driving force;
Receiver;
Wherein, what the low and high level of digital signal that described data collector receives controlled described first single-pole double-throw switch (SPDT) and the second single-pole double-throw switch (SPDT) opens direction.
Preferably, described receiver comprises:
The receiving end resistance be connected with the second single-pole double-throw switch (SPDT) with described first single-pole double-throw switch (SPDT);
With the difference channel of described receiving end resistor coupled in parallel, for going out described digital signal according to the Polarity restoration of described receiving end resistance both end voltage.
Preferably, the control port of described first single-pole double-throw switch (SPDT) is connected with one end of described receiving end resistance, and the control port of described second single-pole double-throw switch (SPDT) is connected with the other end of described receiving end resistance.
Preferably, the first output port of described first single-pole double-throw switch (SPDT) is connected with the output port of described adjustable current source, the second output port ground connection of described first single-pole double-throw switch (SPDT); First output port of described second single-pole double-throw switch (SPDT) is connected with the output port of described adjustable current source, the second output port ground connection of described second single-pole double-throw switch (SPDT).
Preferably, described adjustable current source comprises MOS discrete device, for by producing constant current source, controls mos gate pole tension by different voltage, changes drive current size; Described difference channel comprises Schmidt's comparator circuit, for detecting the both end voltage of described receiving end resistance, recovers digital signal.
The present invention also provides a kind of data transmission system, comprising:
First back end; Described first back end comprises the first data collector, first microprocessor MCU and the first programmable logic device (PLD) FPGA; Described first data collector is connected with a described FPGA, and a described MCU is connected with a described FPGA; Described first data collector is above-mentioned data collector;
And carry out the second back end of data transmission between described first back end;
Described first data collector, for receiving the bit error rate of the abnormal notice of the bit error rate that described second back end sends and data link, if the described bit error rate exceeds the most high threshold of preset range, increase driving force, if the described bit error rate exceeds the lowest threshold of preset range, reduce driving force.
Preferably, described second back end comprises: the second data collector, the second Micro-processor MCV and the second programmable logic device (PLD) FPGA; Described second data collector is connected with described 2nd FPGA, and described 2nd MCU is connected with described 2nd FPGA; Described second data collector is above-mentioned data collector.
Preferably, described second data collector, for detecting the bit error rate of data link and judging, if the described bit error rate exceeds preset range, determines that the described bit error rate is abnormal, sends the abnormal notice of the bit error rate and the described bit error rate to described first data collector.
A kind of data collector provided by the present invention and data transmission system, this data collector comprises: driver; The second single-pole double-throw switch (SPDT) that described driver comprises adjustable current source, the first single-pole double-throw switch (SPDT) be connected with described adjustable current source and is connected with described adjustable current source; Described adjustable current source is used for by regulating electric current to control driving force; Receiver; Wherein, what the low and high level of digital signal that described data collector receives controlled described first single-pole double-throw switch (SPDT) and the second single-pole double-throw switch (SPDT) opens direction.Visible, described data collector is made up of driver and receiver, driver is made up of adjustable current source and a pair single-pole double-throw switch (SPDT), current source can regulate size of current to control driving force, the low and high level of digital signal controls the gating direction of single-pole double-throw switch (SPDT), receiver goes out digital signal according to the Polarity restoration of receiving end resistance both end voltage, realizes dynamic conditioning transmission and drives, reduce the power consumption of data transmission.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only embodiments of the invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to the accompanying drawing provided.
Fig. 1 is the basic structure schematic diagram of RS-485 transceiver in prior art;
Fig. 2 is the basic structure schematic diagram of LVDS transceiver in prior art;
Fig. 3 is the structural representation of a kind of data collector provided by the present invention;
Fig. 4 is RS485, two kinds of LVDS chips and data collector data transmitting portion power consumption comparison diagram of the present invention;
Fig. 5 is RS485, two kinds of LVDS chips and data collector data receiver part power consumption comparison diagram of the present invention;
Fig. 6 is RS485, two kinds of LVDS chips and data collector data transmit-receive total power consumption comparison diagram of the present invention;
Fig. 7 is the structural representation of a kind of data transmission system provided by the present invention.
Fig. 8 is the decision flow chart of A node in Fig. 7;
Fig. 9 is the decision flow chart of B node in Fig. 7.
Embodiment
Core of the present invention is to provide a kind of data collector and data transmission system, drives, reduce the power consumption of data transmission to realize dynamic conditioning transmission.
The present invention program is understood better in order to make those skilled in the art person, below in conjunction with the accompanying drawing in the embodiment of the present invention, technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
Please refer to Fig. 3, Fig. 3 is the structural representation of a kind of data collector provided by the present invention, and this data collector comprises:
Driver 11; Driver 11 comprises adjustable current source 21, the first single-pole double-throw switch (SPDT) 22 be connected with adjustable current source and the second single-pole double-throw switch (SPDT) 23 be connected with adjustable current source;
Wherein, adjustable current source 21 is for controlling driving force by adjustment electric current;
Receiver 12;
Wherein, what the low and high level of digital signal that described data collector receives controlled described first single-pole double-throw switch (SPDT) and the second single-pole double-throw switch (SPDT) opens direction.
Wherein, receiver 12 comprises:
The receiving end resistance 31 be connected with the second single-pole double-throw switch (SPDT) 23 with the first single-pole double-throw switch (SPDT) 22;
The difference channel 32 in parallel with receiving end resistance 31, for going out digital signal according to the Polarity restoration of receiving end resistance 31 both end voltage.
Wherein, the control port of the first single-pole double-throw switch (SPDT) is connected with one end of receiving end resistance, and the control port of the second single-pole double-throw switch (SPDT) is connected with the other end of receiving end resistance.
Wherein, the first output port of the first single-pole double-throw switch (SPDT) is connected with the output port of adjustable current source, the second output port ground connection of the first single-pole double-throw switch (SPDT); First output port of the second single-pole double-throw switch (SPDT) is connected with the output port of adjustable current source, the second output port ground connection of the second single-pole double-throw switch (SPDT).
Wherein, adjustable current source comprises MOS discrete device, for by producing constant current source, controls mos gate pole tension by different voltage, changes drive current size; Difference channel comprises Schmidt's comparator circuit, for detecting the both end voltage of receiving end resistance, recovers digital signal.Data collector receives digital signal, and what control the first single-pole double-throw switch (SPDT) and the second single-pole double-throw switch (SPDT) by the low and high level of digital signal opens direction, and data collector goes out digital signal, output digit signals according to the Polarity restoration of receiving end resistance both end voltage.
When the digital signal that data collector receives is high level, first single-pole double-throw switch (SPDT) connects the first output port, second single-pole double-throw switch (SPDT) connects the second output port, at this moment electric current is by the first single-pole double-throw switch (SPDT), flow into receiving end resistance, then after outflow of bus current receiving end resistance through the second double throw switch ground connection, on receiving end resistance, produce forward voltage like this, difference channel recovers the digital signal of noble potential according to receiving the forward voltage that resistance produces.When the digital signal that data collector receives is low level, first single-pole double-throw switch (SPDT) connects the second output port, second single-pole double-throw switch (SPDT) is communicated with the first output port, at this moment electric current is by the second single-pole double-throw switch (SPDT), flow into receiving end resistance, then after outflow of bus current receiving end resistance through the first double throw switch ground connection, receiving end resistance produces negative voltage, and difference channel recovers the digital signal of electronegative potential according to receiving the forward voltage that resistance produces.
Concrete, the structure of driver and receiver is as shown in Figure 3.Driver is made up of adjustable current source and a pair single-pole double-throw switch (SPDT).Current source can regulate size of current to control driving force, the low and high level of digital signal controls the gating direction of single-pole double-throw switch (SPDT), when transmission data bit is " 1 ", electric current arrives ground through K switch 1, receiving end resistance R, K switch 2 successively, and receiving end resistance R produces forward voltage; When transmission data bit is " 0 ", electric current arrives ground through K switch 2, receiving end resistance R, K switch 1 successively, and receiving end resistance R produces negative voltage.Receiving end goes out digital signal according to the Polarity restoration of resistance both end voltage.
Wherein, MOS discrete device and some half integrated IC is adopted to achieve said structure.Produce constant current source by metal-oxide-semiconductor, control mos gate pole tension by different voltage, thus change drive current size, single-pole double-throw switch (SPDT) K1 and K2 adopts low-voltage simulation switch chip to realize; Receiver then adopts Schmidt's comparator circuit, detects receiving end resistance both end voltage, recovers " 0,1 " signal.
Wherein, all components and parts all have employed lower voltage components, and data collector can work under the low-voltage of 1.8V, and compared with the 3.3V operating voltage of RS-485, LVDS, its power consumption can reduce about 70%.This data collector has been carried out contrast test with RS-485 and two conventional LVDS circuit chip under same environment, test result is as Fig. 4, shown in Fig. 5 and Fig. 6, Fig. 4 is RS485, the data sending power consumption comparison diagram of two kinds of LVDS chips and data collector of the present invention, Fig. 5 is RS485, the data receiver power consumption comparison diagram of two kinds of LVDS chips and data collector of the present invention, Fig. 6 is RS485, the transmitting-receiving total power consumption comparison diagram of two kinds of LVDS chips and data collector data of the present invention, can see no matter being that data send, data receiver still receives and dispatches total process, the transmitting-receiving process of data collector of the present invention all significantly reduces power consumption.Wherein under the speed of 4Mbps, transmitting-receiving summation power consumption is compared with RS-485 and is reduced 87%, compares reduce 60% with LVDS.
To sum up, a kind of data collector provided by the present invention, data collector comprises: driver; The second single-pole double-throw switch (SPDT) that described driver comprises adjustable current source, the first single-pole double-throw switch (SPDT) be connected with described adjustable current source and is connected with described adjustable current source; Described adjustable current source is used for by regulating electric current to control driving force; Receiver; Wherein, what the low and high level of digital signal that described data collector receives controlled described first single-pole double-throw switch (SPDT) and the second single-pole double-throw switch (SPDT) opens direction.Visible, data collector is made up of driver and receiver, driver is made up of adjustable current source and a pair single-pole double-throw switch (SPDT), current source can regulate size of current to control driving force, the low and high level of digital signal controls the gating direction of single-pole double-throw switch (SPDT), receiver goes out digital signal according to the Polarity restoration of receiving end resistance both end voltage, realizes dynamic conditioning transmission and drives, reduce the power consumption of data transmission.
Please refer to Fig. 7, Fig. 7 is the structural representation of a kind of data transmission system provided by the present invention, and this data transmission system comprises:
First back end 41, the A node namely in figure;
First back end 41, i.e. A node, comprise the first data collector 53, first microprocessor MCU52 and the first programmable logic device (PLD) FPGA51; First data collector 53 is connected with a FPGA51, and a MCU52 is connected with a FPGA51; First data collector 53 be above-mentioned in data collector;
And the B node carried out between the first back end 41 in second back end 42, the second back end 42 i.e. figure of data transmission;
First data collector 41, for receiving the bit error rate of the abnormal notice of the bit error rate that the second back end sends and data link, if the bit error rate exceeds the most high threshold of preset range, increase driving force, if the bit error rate exceeds the lowest threshold of preset range, reduce driving force.
Wherein, the second back end, i.e. Node B, comprising: the second data collector 63, second Micro-processor MCV 62 and the second programmable logic device (PLD) FPGA61; Second data collector 63 is connected with the 2nd FPGA61, and the 2nd MCU62 is connected with the 2nd FPGA61; Second data collector 63 be above-mentioned in data collector.
Wherein, the second data collector, for detecting the bit error rate of data link and judging, if the bit error rate exceeds preset range, determines that the bit error rate is abnormal, sends the abnormal notice of the bit error rate and the bit error rate to the first data collector.
First microprocessor MCU is connected with the first data collector, and data stream through the first programmable logic device (PLD) FPGA, then through first microprocessor MCU, returns the first data collector by the first data collector.Second Micro-processor MCV is connected with the second data collector, and data stream through the second programmable logic device (PLD) FPGA, then through the second Micro-processor MCV, returns the second data collector by the second data collector.
Concrete, this system can be followed and be regulated driving intensity in real time according to Link State, thus reaches the object reducing power consumption.Characterize station volume data transmission state by the bit error rate, if cable increases or neighbourhood noise becomes large, the signal to noise ratio (S/N ratio) of signal transmission will be caused to reduce, thus make the bit error rate increase.This system take the bit error rate as the self-adaptation negotiation mechanism of basis.Each number passes node by coding/decoding module and Micro-processor MCV, real-time statistics link error rates, if the bit error rate detected is higher than design threshold, then this node informs neighbor node statistics, driving force can be strengthened after the other side is notified, then continue to wait for new statistics notice, until set up the reliable data transmission passage that meets designing requirement; Otherwise if the bit error rate detected is in a long time all lower than designing requirement, for fully reducing power consumption, neighbor node can suitably reduce to drive intensity.Control through this negotiation mechanism, each number passes the transmission of internodal data and drives intensity in suitable level by controlling, can meet design requirement, sufficiently lower power consumption again.
Wherein, FPGA and MCU is adopted to achieve the negotiation mechanism of this system.Data transmission adopts 8b10b coding, adds up the bit error rate by the coding and decoding module that FPGA realizes.Can communicate with neighbor node containing digital analog converter DAC, MCU in MCU, and regulate drive current by control DAC output.Two nodes A, B, i.e. first node and Section Point, first node and Section Point all comprise data and send and data reception module, send out B for A and receive the detailed process describing negotiation mechanism and realize, with reference to Fig. 8 and Fig. 9, Fig. 8 position is the decision flow chart of A node in Fig. 7, Fig. 9 is the decision flow chart of B node in Fig. 7, W represents that data are sent to the bit error rate of B node from A node, Wh represents the maximal value of the bit error rate of system requirements, and Wh less expression system is stricter to data transmission reliability requirement; Wl represents the lower limit controlling the bit error rate, namely when the bit error rate is lower than thinking during Wl that driving intensity is excessive, causes power wastage.For fully reducing power consumption, the bit error rate is controlled between Wh and Wl.
To sum up, a kind of data transmission system provided by the present invention, comprising: the first back end; First back end comprises the first data collector, first microprocessor MCU and the first programmable logic device (PLD) FPGA; First data collector is connected with a FPGA, and a MCU is connected with a FPGA; First data collector be above-mentioned in data collector; And carry out the second back end of data transmission between the first back end; First data collector, for receiving the bit error rate of the abnormal notice of the bit error rate that the second back end sends and data link, if the bit error rate exceeds the most high threshold of preset range, increase driving force, if the bit error rate exceeds the lowest threshold of preset range, reduce driving force.Visible, first data collector receives the abnormal notice of the bit error rate of the second back end transmission and the bit error rate of data link, if the bit error rate exceeds the most high threshold of preset range, increase driving force, if the bit error rate exceeds the lowest threshold of preset range, reduce driving force, such driving force carrying out adjustment System according to the bit error rate, the bit error rate is too high, show to drive intensity too small, then adjust driving force and become large, improve data transmission credibility, the bit error rate is too low, show to drive intensity excessive, then adjust driving force to diminish minimizing power consumption, realize dynamic conditioning transmission to drive, reduce the power consumption of data transmission, and improve data transmission credibility.
Above a kind of data collector provided by the present invention and data transmission system are described in detail.Apply specific case herein to set forth principle of the present invention and embodiment, the explanation of above embodiment just understands method of the present invention and core concept thereof for helping.It should be pointed out that for those skilled in the art, under the premise without departing from the principles of the invention, can also carry out some improvement and modification to the present invention, these improve and modify and also fall in the protection domain of the claims in the present invention.
Claims (8)
1. a data collector, is characterized in that, comprising:
Driver; The second single-pole double-throw switch (SPDT) that described driver comprises adjustable current source, the first single-pole double-throw switch (SPDT) be connected with described adjustable current source and is connected with described adjustable current source; Described adjustable current source is used for by regulating electric current to control driving force;
Receiver;
Wherein, what the low and high level of digital signal that described data collector receives controlled described first single-pole double-throw switch (SPDT) and the second single-pole double-throw switch (SPDT) opens direction.
2. data collector as claimed in claim 1, it is characterized in that, described receiver comprises:
The receiving end resistance be connected with the second single-pole double-throw switch (SPDT) with described first single-pole double-throw switch (SPDT);
With the difference channel of described receiving end resistor coupled in parallel, for going out described digital signal according to the Polarity restoration of described receiving end resistance both end voltage.
3. data collector as claimed in claim 2, it is characterized in that, the control port of described first single-pole double-throw switch (SPDT) is connected with one end of described receiving end resistance, and the control port of described second single-pole double-throw switch (SPDT) is connected with the other end of described receiving end resistance.
4. data collector as claimed in claim 2, it is characterized in that, the first output port of described first single-pole double-throw switch (SPDT) is connected with the output port of described adjustable current source, the second output port ground connection of described first single-pole double-throw switch (SPDT); First output port of described second single-pole double-throw switch (SPDT) is connected with the output port of described adjustable current source, the second output port ground connection of described second single-pole double-throw switch (SPDT).
5. data collector as claimed in claim 2, it is characterized in that, described adjustable current source comprises MOS discrete device, for by producing constant current source, controls mos gate pole tension by different voltage, changes drive current size; Described difference channel comprises Schmidt's comparator circuit, for detecting the both end voltage of described receiving end resistance, recovers digital signal.
6. a data transmission system, is characterized in that, comprising:
First back end; Described first back end comprises the first data collector, first microprocessor MCU and the first programmable logic device (PLD) FPGA; Described first data collector is connected with a described FPGA, and a described MCU is connected with a described FPGA; Described first data collector is for as the data collector in claim 1 to 5 as described in any one;
And carry out the second back end of data transmission between described first back end;
Described first data collector, for receiving the bit error rate of the abnormal notice of the bit error rate that described second back end sends and data link, if the described bit error rate exceeds the most high threshold of preset range, increase driving force, if the described bit error rate exceeds the lowest threshold of preset range, reduce driving force.
7. system as claimed in claim 6, it is characterized in that, described second back end comprises: the second data collector, the second Micro-processor MCV and the second programmable logic device (PLD) FPGA; Described second data collector is connected with described 2nd FPGA, and described 2nd MCU is connected with described 2nd FPGA; Described second data collector is for as the data collector in claim 1 to 5 as described in any one.
8. system as claimed in claim 7, it is characterized in that, described second data collector, for detecting the bit error rate of data link and judging, if the described bit error rate exceeds preset range, determine that the described bit error rate is abnormal, send the abnormal notice of the bit error rate and the described bit error rate to described first data collector.
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| CN112162895B (en) * | 2020-08-26 | 2022-04-26 | 东风汽车集团有限公司 | Abnormal state detection method, device, system, equipment and medium |
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Application publication date: 20160330 |