CN1278364A - 安全的集成电路装置和这种装置的制造方法 - Google Patents

安全的集成电路装置和这种装置的制造方法 Download PDF

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CN1278364A
CN1278364A CN98810670A CN98810670A CN1278364A CN 1278364 A CN1278364 A CN 1278364A CN 98810670 A CN98810670 A CN 98810670A CN 98810670 A CN98810670 A CN 98810670A CN 1278364 A CN1278364 A CN 1278364A
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比阿特丽斯·邦瓦洛特
罗伯特·莱迪尔
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Abstract

本发明涉及一种安全的集成电路装置,该装置首先包括一个活性层(10),其由一种半导体材料和集成在所述半导体材料中的电路制成,并在其活性表面(11)上有触点接片(15);其次包括一个附加层(20);所述装置的特征在于,该活性层(10)通过加在该活性层(10)的活性表面(11)上的一个中间层(30),与该附加层(20)连接在一起;并且,与该活性层(10)的活性表面(11)相对的活性层(10)的表面(12)被弄薄。本发明可应用于,例如,具有集成电路的便携式物体,和一种存储器卡的信息安排格式的领域。

Description

安全的集成电路装置和 这种装置的制造方法
本发明涉及一种安全的集成电路装置，该装置首先包括由一种半导体材料制成、和集成在所述半导体材料中的电路，并在其活性表面上具有触点接片的一个活性层；其次包括一个附加层。本发明还涉及制造这种装置的一种方法。
一般来说，本发明可应用于集成电路领域；更具体地，但不是限制性地说，可应用于具有集成电路的便携式物品，和一张存储器卡或多张存储器卡的形式的领域。
目前制造的存储器卡，通常包括一个由塑料制成，并带有一个可放入一个电子组件的腔的卡片体。该电子组件包括一个集成电路，和一个所述集成电路的支承。当该卡利用触点工作时，该集成电路与该电子组件的支承中，与该卡片体的表面齐平的区域连接；而当该卡不用触点工作时，则该集成电路与一个无线的终端连接。
这种存储器卡设计用于进行各种不同的操作；例如：与获得编成密码的电视频道有关的付费操作；与健康服务领域有关的操作；在公共交通车辆、电话业务或银行业务中的借方操作等。这种操作是利用该存储器卡的电子组件和读出装置之间的电气耦合或电磁耦合，以读的模式或读/写模式进行的。
为了避免，或至少是限制舞弊和/或破坏公民的自由的行为，已经开发了许多不同的装置。具体地说，这些装置包括密码、加密或授权钥匙，或转换表格。在具有微型控制器的卡中，这种装置，以及芯片中所包含的秘密信息，基本上是包含在用电气方法可擦除可编程只读存储器(EEPROM)，和只读存储器(ROM)中；而这些存储器是由中央处理单元(CPU)管理的。
有时，可以通过实际分析芯片所包含的集成电路，来进入芯片所包含的秘密信息中。这就是为什么要开发各种不同的方法，来保证集成电路安全的原因。
某些这种方法，是利用聚合物层和金属层，覆盖该集成电路的表面，特别是，覆盖所述集成电路的存储器平面的表面。这些聚合物和金属层的象迷宫一样和纠缠在一起的性质，使得难以辨认该集成电路的设计。
不幸的是，利用这些方法得到的安全程度并不是绝对的，因为有时，可以通过依次地和有选择地，对各种不同的聚合物和金属层进行化学腐蚀，仍有可能进入该集成电路，和该集成电路包含的信息中。
另一些方法是将第二个“从属的”集成电路，放在一个要保护的“主要的”集成电路上面；并将所述二个集成电路互相连接起来。这样，如果将这二个集成电路分开，则(例如)保密数据就不可逆地丢失。这种装置，如同在所公布的2727227号法国专利中所述的那样，只是在所述装置总是接通的应用场合下是有效的。
考虑到上述各点，本发明要解决的技术问题是：以较低的成本和更有效的方式，不需要使该装置连续通电，而能限制实际进入一个集成电路装置的集成电路中的可能性。
为了解决这个问题，本发明提供了一种安全的集成电路装置，该装置首先包括一个活性层，它由一种半导体材料和集成在所述半导体材料中的电路制成，并在其活性表面上有触点接片；其次包括一个附加层；所述装置的特征在于，该活性层通过加在该活性层的活性表面上的一个中间层，与该附加层连接在一起；另外，将与该活性层的活性表面相对的活性层的表面弄薄。
本发明还提供了一种安全的集成电路装置的制造方法，该装置首先包括一个活性层，其由一种半导体材料和集成在所述半导体材料中的电路制成，并在其活性表面上有触点接片；其次包括一个附加层；所述方法的特征在于，该活性层，通过加在该活性层的活性表面上的一个中间层，与该附加层粘接在一起；并且，将与该活性层的活性表面相对的该活性层的表面弄薄了。
通过利用物理处理方法，使该活性层的活性表面恢复，就可以得到一个安全的集成电路装置。另外，由该活性层和该附加层组成的组件的厚度，即该安全的集成电路装置的厚度，大约与通常的、不安全的集成电路装置的厚度相同。
通过结合附图给出的下述非限制性的说明，可以实际上更好地理解本发明的实现方式。其中：
图1为本发明的装置的横截面图；
图2为带有多个本发明的装置的一个集成电路晶片的透视图；
图3A～3F为制造本发明的安全的集成电路装置的一个附加层的不同工序的横截面图；
图4A～4C为制造本发明的安全的集成电路装置的一个活性层的不同工序的横截面图；和
图5A～5D为利用图3A～3F和图4A～4C所示的工序制成的附加层和活性层，来得到本发明的安全的集成电路装置的不同工序的横截图。
如图1所示，本发明的安全的集成电路装置由二个主要的层构成，即：一个被弄薄的活性层10和一个附加层20。所述二个层10，20由一个中间层、30粘接在一起。
该被弄薄的活性层10有一个活性表面11，和与该活性表面ll相对的表面12。该附加层20有一个顶面21和一个底面22。
该二个层10和20，由一个中间层30粘接在一起。在图1所示的结构中，该被弄薄的活性层10放在该附加层20的下面；该活性层10的活性表面11，和该附加层20的底面22，分别与该中间层30的底面31和中间层30的顶面32接触。
叠放在一起的三个层10、20和30组成的组件的厚度，最好大约与硅晶片制造厂家销售的、通常的、不安全的集成电路装置的厚度相同，即：大约为150微米。这个组件可以毫无困难地集成在用于制造存储器卡的电子组件中。这个上述三个层组成的组件还可以利用已知的Mosa c(注册商标)式的方法，“照原样”集成在上述卡片体中。
该被弄薄的活性层10的厚度，在5～50微米范围内(例如，大约10微米)；即：该厚度比上述带有集成电路的、通常的装置的活性层的厚度小得多。该活性层10由各种不同的、叠放在一起的子层(最好为一个子层13和一个活性子层14)构成。
厚度在0.1～3微米(例如，大约为0.4微米)范围内的该子层13，由绝缘材料，特别是二氧化硅(SiO2)制成。该子层13的一个功能，是限制在构成集成电路的凹陷部分(sink)处漏电。然而，该子层13也可以用其他某种材料制造。例如，该子层13可由具有一定厚度的硅基片制成；在使该子层变薄的过程中，该子层13被加上电位与该活性子层14的电位不同的偏压。该子层13至少有一个物理一化学特性，与该活性子层14不同。
放置在该子层13上面的活性子层14的厚度，在5～50微米范围内(例如，大约10微米)。该活性子层14为一个电子线路集成在其中的外延生长的子层。因此，通常将这个活性子层14作成具有多个交错的厚度，并将该活性子层14的表面再细分成各种不同的区域，具体地说，分成储存需要保护的秘密信息的ROM和EEPROM区域。
金属制的输入/输出触点接片15，与该活性子层14的表面齐平，或从该表面突起出来。
中间层30由化学上惰性很大，和特别是对通常的溶剂非常不敏感的一种绝缘材料制成。具体地说，该中间层30可以是一层聚酰亚胺。该中间层30带有多个位于该触点接片15上面的开口33。
该附加层20的厚度，根据该层是否被弄薄，处在80～600微米范围内。该附加层20由强度高，刚性大和不透明，并且具有可被腐蚀或被加工的性质的材料(最好为半导体)制成。这个半导体材料最好与构成上述活性层10的活性子层14的半导体材料相同，即：该半导体材料为硅，特别是单晶硅。结果，不可能根据其物理化学反应能力来区别该活性层10和附加层20。应当注意，由于该被弄薄的活性层10的厚度小，因此很关键的一点是，要使该附加层20的材料的物理性质，与该被弄薄的活性层10的材料的物理性质相同或非常相似。否则，该活性层10和中间层30的各种不同的物理反应，可能会妨碍本发明的装置的实际完整性。例如，该活性层10和中间层30之间的热膨胀系数的差别，可以使该被弄薄的活性层10中的显微裂纹增大，从而使得在温度升高的作用下，该活性层10特别脆，容易损坏。
另外，该活性层10还带有多个通道23，或能够与上述触点接片15建立电气连接的任何其他装置，特别是经过电镀的通孔。当使用没有经过电镀的通道时，可以通过金属导线2(例如，黄金丝或铝丝)，在本发明的装置1中建立电气连接。
这样，如果攻击者企图进入本发明的安全的集成电路装置中的集成电路中，以确定集成电路的结构，和从中抽取所述集成电路装置所包含的任何秘密信息时；则攻击者必需要将该附加层20与该活性层10分开。
为此目的，攻击者可能要对该活性层10和附加层20构成的组件加一个拉力。在这种情况下，作成相当脆的该被弄薄的活性层10，会在许多地方破裂，使得攻击者不可能确定该集成电路的结构，和从中抽出秘密信息。
攻击者还可能企图破坏该附加层20和中间层30。由于该中间层所用的粘接剂是能耐受通常的溶剂的，为了破坏所述的附加层20和中间层30，则攻击者必须使用强酸或强碱。这种强碱可破坏硅，所破坏的不仅是该附加层20的硅，而且可破坏该活性层10的硅。这种强酸也可破坏形成集成电路的线路的金属。因此，攻击者也不可能确定该集成电路的结构，和不可能从其中抽出信息。
这种装置对光学侵入方法也适用。应当指出，该附加层20是紫外线(UV)或红外线(IR)辐射的有效障碍，因此，可以防止由紫外线或红外线造成的对集成电路的干扰。
为了制造本发明的装置1，首先制造该附加层20。将粘接剂涂在如图4C所示形式的、没有弄薄的活性层10上；然后将该附加层20与涂有粘接剂的该没有弄薄的活性层10粘接起来。在接下去的一个工序中，将该粘接的活性层10弄薄。
为了简单起见，制造本发明的安全的集成电路装置的工序，主要是针对一个单一的装置1(即，一块芯片)来说明的。然而，在实践中，这些工序最好是在硅晶片上成批地进行。为了制造该活性层10，可使用每一块上都具有并排放置的许多集成电路装置4的硅片3(图2)；而为了制造该附加层20，可以使用基本上为同一规格，但没有集成电路的硅片。通过使用上述硅片，可以迅速地得到大量的安全的集成电路装置。因此，这种不需要事先对硅片制造厂家提供的硅片作改造的，实现本发明的装置的方法，是本发明的一个明显的优点。
为了形成附加层20，可采用图3A～3F所示的工序。
在第一个工序中，对半导体基片24(具体地说，是厚度大约为400微米的一块硅晶片)(图3A)进行氧化；然后，可随意而非强制性地，进行氮化。这时，在该硅晶片24的周边上，出现一层氧化物25，并且还可能出现一层氮化物(图3B)。
然后，在硅晶片24的一个氧化表面上，沉积一层感光层26(图3C)。
再将该感光层26通过一块掩模曝光，所述感光层26露出的表面部分，与开口27相通(图3D)。
然后，可以有选择地，在没有被该感光层26保护的位置处(即，具体地是开口27的位置处)；和还可以在该硅晶片24的，与带有所述开口27相对的表面上，破坏上述氧化层25(图3E)。
为了得到附加层20，可对图3E所示的硅晶片24进行加工(图3F)。这种加工是利用干式或湿式的腐蚀方法进行的，这样，可制成上述通道23。另外，这种加工还同时可使所述硅晶片24变薄，使其厚度减小至大约100微米，或甚至80微米。
在进行上述工序的同时，还可将粘接剂涂在没有弄薄的活性层10上。
又如图4A所示，该没有弄薄的活性层10有一个硅的子层16。由于在该没有弄薄的活性层10内，有一个SiO2的子层，因此，三个层16、13和14组成的组件，形成一个硅覆盖在绝缘体上(SOI)形式的基片。在该SOI式基片中，集成电路安装在由氧化物层使之与硅片绝缘的一个区域上。
在该没有弄薄的活性层10的活性表面11上，涂敷一层粘性的聚合物粘接剂，形成覆盖上述触点接片15的层30(图4B)。
在粘接剂为感光粘接剂的优选情况下，该粘接剂可直接通过掩模曝光。在该层30上形成开口33；这些开口至少部分地与上述触点接片15相通(图4C)。否则，需要在粘接剂层30的表面上涂上一层感光层，并按照图3C～3E所述的方法，打开所述感光层。
最后，进行使本发明的装置变得安全的工序。这些工序表示在图5A～5E中。
首先，将图3F所示的附加层20，放在图4C所示的由二个层10和30组成的组件表面上，使上述通道23放置在该触点接片15上面。
然后，通过热压的方法，将该附加层20粘接在该没有弄薄的活性层10上。实际上，叠放在一起的活性层10和附加层20受到大约为10巴(bar)的压力；和比与形成该集成电路的铝的线路，所能承受的极限温度相适应的(大约400℃)温度低的大约为300℃的温度的共同作用。
另外，为了使该活性层10变薄，将由上述三个层10、20和30粘接在一起形成的组件，用压在所述组件顶面、该附加层20的表面和该通道23的底面上的一个机械式保护块体40，保护起来(图5B)。这样，完全有可能加工该活性层10的背面，将上述粘接在一起的组件弄薄，使其厚度减小至大约为150微米；即减小至基本上与现代通常用的不安全的集成电路装置的厚度相等。当然，将该活性层10弄薄时要考虑到，不使其所包括的上述活性子层14被加工到。另外，在该活性层10中有子层13的存在，也可以保证使加工停止下来；并且，可以与集成电路晶片两个表面的平行度特性无关地，精确地控制该活性层上的活性区的厚度。
当加工完成后，可以取下该保护块体40(图5D)。
然后，利用已知的通常的方法(金属丝焊接，或特别是楔焊)，使导线2与上述触点接片15连接。
当然，在导线与上述触点接片焊接连接的工序之前，在一块集成电路晶片上采用本发明的方法时，要将安全装置从该集成电路晶片上切下。例如，可将所述的安全装置输送至一条镀有金属的条带上，或“引线框架”上；并在所述工序以后，接着在将电子组件安装在存储器卡的卡片体中之前，用树脂涂覆每一个电子组件。

Claims (9)

1.一种安全的集成电路装置，该装置首先包括一个活性层(10)，其由一种半导体材料和集成在所述半导体材料中的电路制成，并在其活性表面(11)上有触点接片(15)；其次包括一个附加层(20)；所述装置的特征在于，该活性层(10)通过加在该活性层(10)的活性表面(11)上的一个中间层(30)，与该附加层(20)连接在一起；并且，与该活性层(10)的活性表面(11)相对的活性层(10)的表面(12)被弄薄。
2.如权利要求1所述的装置，其特征为，该被弄薄的活性层(10)的厚度，在5～50微米范围内。
3.如权利要求1或2所述的装置，其特征为，该附加层(20)由一种半导体材料制成。
4.如权利要求3所述的装置，其特征为，该半导体材料为硅。
5.如上述权利要求中任何一项所述的装置，其特征为，该附加层(20)带有通孔(23)；或任何其他可以与该触点接片(15)建立电气连接的构件。
6.如上述权利要求中任何一项所述的装置，其特征为，在与活性层(10)的活性表面(11)相对的活性层(10)的表面(12)上，该所述的活性层具有与活性子层(14)至少有一个物理化学特性不相同的一个子层(13)。
7.如权利要求6所述的装置，其特征为，该子层(13)为由二氧化硅制成的一个子层。
8.一种半导体材料晶片，其特征为，该晶片具有多个根据上述权利要求中任何一项所述的装置。
9.一种制造安全的集成电路装置的制造方法，该集成电路装置首先包括一个活性层(10)，其由一种半导体材料和集成在所述半导体材料中的电路制成，并在其活性表面(11)上有触点接片(15)；其次包括一个附加层(20)；所述方法的特征在于，该活性层(10)，通过加在该活性层(10)的活性表面(11)上的一个中间层(30)，与该附加层(20)连接在一起；并且将与该活性层(10)的活性表面(11)相对的该活性层(10)的表面(12)弄薄。
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