CN1258213C - Wafer grade pre-burning device - Google Patents
Wafer grade pre-burning device Download PDFInfo
- Publication number
- CN1258213C CN1258213C CN 02146857 CN02146857A CN1258213C CN 1258213 C CN1258213 C CN 1258213C CN 02146857 CN02146857 CN 02146857 CN 02146857 A CN02146857 A CN 02146857A CN 1258213 C CN1258213 C CN 1258213C
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- wafer
- signal
- burn
- test circuit
- circuit plate
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- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
The present invention relates to a wafer level burn-in device which comprises a burn-in board and a wafer clamping group, wherein the burn-in board is used for receiving test signals from a burn-in oven; the wafer clamping group is fixed to the burn-in board and is used for fixing a wafer to be tested, the wafer clamping group comprises a signal test circuit board which uses a probe for transferring the test signals to signal input and output contact points of individual dies on the wafer to be tested, the probe has retractility or can be replaced by a micro-spring, and the signal test circuit board also comprises micro fuse wires which are arranged between the signal input and output contact points and the signal test circuit board so as to avoid generating high heat when the test current is excessive. The wafer clamping group also comprises contraposition holes used for detecting the placing position of the wafer to be tested in the wafer clamping group; in addition, springs are arranged between the wafer clamping group and the signal test circuit board to balance and buffer the pressure applied to the wafer to be tested.
Description
Technical field
The present invention relates to manufacture of semiconductor, particularly relate to a kind of wafer-level burn device that is used in the burn-in test processing procedure.
Background technology
Burn-in test processing procedure (burn-in test process) is important reliability processing procedure in the manufacture of semiconductor, traditional encapsulation procedure is after the wafer process is cut into chip (die), next chip passes through the connection of lead frame, impose colloid at last again and be coated on wherein chip is whole, form the wafer particle of tool pin.
The particle processing procedure that next must wear out through encapsulation; The wafer particle is inserted in the slot (socket) on the burn-in board (burn-in board), and along with the difference of granular size, the amounts of particles that every burn-in board can wear out is also different.Next burn-in board is inserted that (burn-in oven) carries out burn-in test in the ageing oven.Burn-in test mainly is the reliability of checking product, the wafer particle is risen to high temperature, and under the condition of high temperature, the wafer particle is imposed test signal, with with the low reliability circuit in the wafer particle, via high temperature and the aging processing procedure of high voltage it is blown, so that filter out the wafer particle of high reliability via test.
Yet, encapsulation technology now, gradually (Wafer Level Chip ScalePackage is main WLCSP), and so-called wafer-class encapsulation is before the wafer cutting, promptly finishes encapsulation procedure on entire wafer with wafer-class encapsulation.Therefore directly carry out burn-in test at wafer, can effectively shorten the processing procedure time and save cost, yet existing aging equipment can't provide the wafer-level burn test, therefore a kind of wafer-level burn device that is used on the existing aging equipment needs.
Summary of the invention
In above-mentioned background of invention, many shortcomings that traditional burn-in test processing procedure is produced the invention provides a kind of wafer-level burn device, the problem of deriving in order to overcome traditionally.
Main purpose of the present invention is for saving the wafer-level burn testing cost.
Another object of the present invention is for saving the wafer-level burn testing time.
Tested number of chips when another object of the present invention is carried out burn-in test for improving.
Another object of the present invention is for avoiding when the burn-in test, because the unusual high heat that short circuit produced.
Another object of the present invention has preferable contacting for probe is provided with the tin ball.
Another object of the present invention is that wafer-level burn device of the present invention can be used on the existing aging equipment.
For reaching above-mentioned purpose, the invention provides a kind of wafer-level burn testing apparatus, it comprises:
One burn-in board is in order at least one group of test signal of accepting to be transmitted by an ageing oven;
One wafer chuck group, in order to clamping one wafer, this wafer chuck group comprises at least one signal test circuit plate, this signal test circuit plate has at least one signal connector and is connected to this burn-in board to receive this test signal, and this signal test circuit plate also is sent to this test signal the signal of individual chip on this wafer and exports into contact;
One gim peg is in order to fix this wafer chuck group on this burn-in board;
It is characterized in that this wafer chuck group comprises also whether at least one contraposition hole is correct in order to detect the putting position of this wafer in this wafer chuck group.
Because according to above-described purpose, the invention provides a kind of wafer-level burn device (Wafer Level Chip Scale Burn-In Apparatus), it comprises burn-in board (burn-inboard) and wafer chuck group, wherein, the test signal of burn-in board in order to accept to transmit by ageing oven (burn-in oven); The wafer chuck group is fixed on the burn-in board, and in order to fixing tested wafer.The wafer chuck group comprises the signal test circuit plate, and this signal test circuit plate uses probe that the signal that test signal is sent to individual chip on the tested wafer is exported into contact, and wherein this probe can be had a retractility, or replaces with Microspring.Wherein above-mentioned signal test circuit plate more comprises little fuse and exports between contact and signal test circuit plate in signal, in order to avoid because the high heat that measuring current is produced when excessive, and the wafer chuck group more comprises registration holes, in order to detect the putting position of tested wafer in the wafer chuck group.Moreover, have spring between wafer chuck group and signal test circuit plate and apply pressure to pressure on the tested wafer with average and buffering.
Description of drawings
Fig. 1 shows preferred embodiment of the present invention;
Lower clamp in Fig. 2 A shows wafer anchor clamps group;
The front of the last anchor clamps in Fig. 2 B shows wafer anchor clamps group;
The back side of the last anchor clamps in Fig. 2 C shows wafer anchor clamps group;
Fig. 3 A and Fig. 3 B are the end view of wafer chuck group.
Symbol description among the figure
102 wafer chuck groups
The last anchor clamps of 102A
The 102B lower clamp
1020 testing circuit board gim pegs
1021 lower clamps are keyhole fixedly
The fixing keyhole of anchor clamps on 1022
1023 times fixing keyholes
Fixing keyhole on 1024
1025 openwork parts
1026 registration holes
104 burn-in board
104A secondary signal connector
The 104B golden finger
106 gim pegs
108 signal test circuit plates
108A first signal connector
The 108B probe
110 wafers
110A tin ball
The 110B loci
114 springs
116 Microsprings
Embodiment
Preferred embodiment meeting of the present invention is described in detail as follows.Yet except describing in detail, the present invention can also implement in other embodiments widely, and scope of the present invention do not limited, and its scope with claims is as the criterion.
The present invention is a kind of wafer-level burn device (Wafer Level Chip Scale Burn-InApparatus), it comprises burn-in board (burn-in board) and wafer chuck group, wherein, the test signal of burn-in board in order to accept to transmit by ageing oven (burn-in oven); The wafer chuck group is fixed on the burn-in board, and in order to fixing tested wafer.The wafer chuck group comprises the signal test circuit plate, and this signal test circuit plate uses probe that the signal that test signal is sent to individual chip on the tested wafer is exported into contact, and wherein this probe can be had a retractility, or replaces with Microspring.
Wherein above-mentioned signal test circuit plate more comprises little fuse and exports between contact and signal test circuit plate in signal, in order to avoid because the high heat that measuring current is produced when excessive, and the wafer chuck group more comprises registration holes, in order to detect the putting position of tested wafer in the wafer chuck group.Moreover, have spring between wafer chuck group and signal test circuit plate and apply pressure to pressure on the tested wafer with average and buffering.
Fig. 1 is preferred embodiment of the present invention, in order to wafer-level burn device of the present invention (Wafer Level Chip Scale Burn In Apparatus) to be described, wherein wafer chuck group 102 is positioned on the burn-in board (Burn In Board) 104, on burn-in board 104, wherein wafer chuck group 102 comprises anchor clamps 102A and lower clamp 102B to gim peg 106 in order to fixed wafer anchor clamps group 102.Signal test circuit plate 108 is connected with last anchor clamps 102A, and has the first signal connector 108A and be connected with secondary signal connector 104A on the burn-in board 104, when being used to wear out (burnin), transmits test signal.In this preferred embodiment, the first signal connector 108A and secondary signal connector 104A are a slot.In addition, burn-in board 104 has golden finger 104B can be inserted in the slot of ageing oven (burn in oven) (not being shown in the icon), accepts the test signal that is transmitted by ageing oven.
Again, above-mentioned burn-in board 104 can be changed along with the ageing oven specification of reality, and the specification of its golden finger 104B also can cooperate the signal slot (slot) of different ageing ovens.
Fig. 2 A, Fig. 2 B and Fig. 2 C are in order to further specify the wafer chuck group 102 among Fig. 1.Fig. 2 A shows lower clamp 102B, the front of anchor clamps 102A in Fig. 2 B demonstration, Fig. 2 C then shows the back side of anchor clamps 102A, and shown in Fig. 2 C, signal test circuit plate 108 is by testing circuit board gim peg 1020, with last anchor clamps 102A fixed engagement, and has probe 108B on it to transmit test signal.As shown in Fig. 2 A and Fig. 2 B, lower clamp 102B has lower clamp gim peg 1021, can with the last anchor clamps of last anchor clamps 102A fixedly keyhole 1022 engage, in order in conjunction with last lower clamp.Last anchor clamps 102A and lower clamp 102B have following fixedly keyhole 1023 respectively and go up fixedly keyhole 1024, in order to allow gim peg 106 can pass anchor clamps and fixing with burn-in board 104.Moreover lower clamp 102B can have openwork part 1025, to alleviate the weight of lower clamp 102B, also can accelerate anchor clamps reach stable temperature in ageing oven time.Yet the shape of openwork part 1025 in other embodiment, the position, the neither qualification of quantity is identical with present embodiment, and lower clamp 102B is any openwork part 1025 of tool not also.
In addition, above-mentioned last anchor clamps 102A and lower clamp 102B in this preferred embodiment for using magnesium alloy, or hydronalium, however in other embodiment also spendable other material.
With reference to figure 2B, last anchor clamps 102A has registration holes 1026, is used to adjust the position of anchor clamps 102A.For example, in Fig. 2 D, one wafer 110 is flat on the lower clamp 102B, this wafer 110 is process wafer-class encapsulation (Wafer Level Chip Scale Package, WLCSP) fabrication process, therefore tin ball 110A be wafer after encapsulation, in order to export as signal into contact point (signal contact).And has loci 110B on this wafer 110, therefore when last anchor clamps 102A is placed on the wafer 110, can watch the position of loci 110B by registration holes 1026, when loci 110B comes across in the registration holes 1026, expression this moment, wafer 110 was positioned on the correct position, that is to say that signal test circuit plate 108 can be correctly contacts with tin ball 110A on the wafer 110.Whether above-mentioned loci can provide the operator visual aligning, or provides automatic board when putting wafer, use the putting position of inductor detecting wafer appropriate.
Fig. 3 A is the end view of wafer chuck group 102, and wherein signal test circuit plate 108 uses probe 108B contact tin ball 110A, in order to transmit and the acceptance test signal.Has spring 114 between signal test circuit plate 108 and last anchor clamps 102A, buffering when exerting pressure, pressure when making probe 108B contact tin ball 110A can disperse on average, and allow the contact-making surface of probe 108B and tin ball 110A more fit tightly, so can avoid because probe 108B and tin ball 110A are because the test yield that loose contact caused descends, or avoid causing the damage of wafer 110 because exerting pressure inequality.In addition, also probe 108B can be replaced to Microspring (micro spring) 116, or the probe of tool Telescopic, shown in Fig. 3 B, so can further provide better buffer protection.
In aging processing procedure (burn in process), test signal is conveyed to tin ball 110A on the wafer 110 via the probe 108B on the signal test circuit plate 108.But when carrying out wafer level test, the bad chip on the wafer 110 may make temperature rise because short circuit causes the electric current rising of the bad chip of flowing through and causes producing a large amount of heats.Will influence the correctness of ageing test result like this, or damage normal chip on the wafer 110.
Therefore, the signal test circuit plate 108 among the present invention more comprise little fuse (microfuse) (not being shown in the icon) in signal test circuit plate 108 test circuit and last other chip of wafer between.When current test signal becomes big, surpass the scope that little fuse can bear, this fuse will be burnt, and cuts off current test signal and continues the bad chip of flowing through, and so can avoid because unusual pyrogenic damage.Wherein, the current range that this little fuse can bear is less than 700mA, yet in this preferred embodiment, preferable little fuse bears and is limited to 450mA～550mA.
The above is preferred embodiment of the present invention only, is not in order to limit protection scope of the present invention; All other do not break away from the equivalence of being finished under the disclosed spirit and changes or modification, all should be included in the scope of claims.
Claims (8)
1. wafer-level burn testing apparatus, it comprises:
One burn-in board is in order at least one group of test signal of accepting to be transmitted by an ageing oven;
One wafer chuck group, in order to clamping one wafer, this wafer chuck group comprises at least one signal test circuit plate, this signal test circuit plate has at least one signal connector and is connected to this burn-in board to receive this test signal, and this signal test circuit plate also is sent to this test signal the signal of individual chip on this wafer and exports into contact;
One gim peg is in order to fix this wafer chuck group on this burn-in board;
It is characterized in that this wafer chuck group comprises also whether at least one contraposition hole is correct in order to detect the putting position of this wafer in this wafer chuck group.
2. wafer-level burn testing apparatus as claimed in claim 1 is characterized in that, above-mentioned signal test circuit plate uses a probe to export into contact with this signal and contacts.
3. wafer-level burn testing apparatus as claimed in claim 1, it is characterized in that, above-mentioned signal test circuit plate is more indivedual to be comprised at least one little fuse and exports between contact and this signal test circuit plate in this signal, in order to avoid because the high heat that electric current is produced when excessive.
4. wafer-level burn testing apparatus as claimed in claim 1 is characterized in that, the material of above-mentioned wafer chuck group is a magnesium alloy.
5. wafer-level burn testing apparatus as claimed in claim 1, it is characterized in that, above-mentioned wafer chuck group is made up of anchor clamps on one and a lower clamp, and should go up anchor clamps and have on one fixedly keyhole of anchor clamps, and this lower clamp have a lower clamp gim peg hole with should on anchor clamps fixedly keyhole engage.
6. wafer-level burn testing apparatus as claimed in claim 5 is characterized in that, also comprises a spring between anchor clamps on this and this signal test circuit plate, applies pressure to pressure on this wafer in order to average and buffering.
7. wafer-level burn testing apparatus as claimed in claim 5 is characterized in that, above-mentioned lower clamp has openwork part to alleviate lower clamp weight.
8. wafer-level burn testing apparatus as claimed in claim 1 is characterized in that above-mentioned wafer has been cut separation, but also place on the adhesive tape with aluminium matter or stainless steel framework on.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02146857 CN1258213C (en) | 2002-10-15 | 2002-10-15 | Wafer grade pre-burning device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02146857 CN1258213C (en) | 2002-10-15 | 2002-10-15 | Wafer grade pre-burning device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1490862A CN1490862A (en) | 2004-04-21 |
| CN1258213C true CN1258213C (en) | 2006-05-31 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 02146857 Expired - Fee Related CN1258213C (en) | 2002-10-15 | 2002-10-15 | Wafer grade pre-burning device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1258213C (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP3153873A1 (en) * | 2015-10-07 | 2017-04-12 | Lantiq Beteiligungs-GmbH & Co. KG | On-chip test pattern generation |
| TWI825662B (en) * | 2022-04-11 | 2023-12-11 | 南亞科技股份有限公司 | Package structure of semiconductor and electrical testing method thereof |
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2002
- 2002-10-15 CN CN 02146857 patent/CN1258213C/en not_active Expired - Fee Related
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| Publication number | Publication date |
|---|---|
| CN1490862A (en) | 2004-04-21 |
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Granted publication date: 20060531 Termination date: 20091116 |