CN218099323U - Probe card and semiconductor test apparatus - Google Patents
Probe card and semiconductor test apparatus Download PDFInfo
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- CN218099323U CN218099323U CN202221586924.0U CN202221586924U CN218099323U CN 218099323 U CN218099323 U CN 218099323U CN 202221586924 U CN202221586924 U CN 202221586924U CN 218099323 U CN218099323 U CN 218099323U
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Abstract
The utility model relates to the field of semiconductor technology, specifically provide a probe card and semiconductor testing device, there is voltage loss in the wiring keysets that aims at solving current probe card, leads to the problem that the test accuracy reduces. Mesh for this reason, the utility model discloses a probe card includes: a wiring adapter plate; the first probe is arranged on the wiring adapter plate and is used for detecting signals of a chip; and the signal sensing line is directly and electrically connected with the first probe so as to directly acquire the signal of the chip through the first probe. Because the signal perception line is directly and electrically connected with the first probe, the signal perception line can directly acquire the signal of the chip through the first probe, the voltage drop of the signal generated by the signal passing through the wiring adapter plate is reduced, the accuracy of the detection signal is greatly improved, and the accuracy of the chip test is greatly improved.
Description
Technical Field
The utility model relates to the field of semiconductor technology, specifically provide a probe card and semiconductor testing device.
Background
There is an important process in the manufacture of semiconductors: and (5) carrying out wafer testing. And testing the round crystal to detect whether the round crystal is qualified or not.
In wafer testing, a tester and a probe card are typically required to test the wafers. As shown in fig. 1, the probe card of the related art mainly includes a wiring interposer 10' and a probe 20' provided on the wiring interposer 10 '; the semiconductor tester 70' has a signal applying line 60' for applying a signal to the chip 30' and a signal sensing line 40' for detecting the signal, and both the signal applying line 60' and the signal sensing line 40' are connected to the wiring switching board 10' and electrically connected to the probe 20' through the wiring switching board 10', thereby achieving signal conduction. During detection, the probe is in contact with the chip 30', the signal applying line 60' applies voltage to the chip 30' through the probe 20' to generate a signal, and the signal sensing line 40' detects whether the signal on the wafer reaches the expectation through the probe, so that the wafer test is realized.
However, since the signal sensing line 40 'is electrically connected to the probe through the wiring patch panel 10', the wiring patch panel 10 'will cause a loss of the power supply voltage, and the voltage reaching the power utilization end is not a desired voltage, which may cause a false judgment in the test of the chip 30' and a low test accuracy.
SUMMERY OF THE UTILITY MODEL
The utility model discloses aim at solving above-mentioned technical problem, promptly, there is voltage loss in the wiring keysets of solving current probe card, leads to the problem that the test accuracy reduces.
According to an aspect of the present invention, there is provided a probe card including: a wiring adapter plate; the first probe is arranged on the wiring adapter plate and used for detecting signals of a chip; and the signal sensing line is directly and electrically connected with the first probe so as to directly acquire the signal of the chip through the first probe.
Further, the first probe comprises: the connecting bulge is arranged on the wiring adapter plate, and the signal sensing line is electrically connected with the connecting bulge; the first probe is arranged on the connecting protrusion, and the signal sensing line is electrically connected with the first probe through the connecting protrusion.
Further, the connecting protrusion and the wiring adapter plate are integrally formed.
Furthermore, the signal sensing lines comprise a first signal sensing line and a second signal sensing line, the first signal sensing line and the second signal sensing line are respectively and electrically connected with different first probes, and the voltage on one side of the first signal sensing line is higher than the voltage on one side of the second signal sensing line.
Further, the probe card further includes: the second probe is arranged on the wiring adapter plate, is electrically connected with the wiring adapter plate and is used for applying signals to the chip; and the signal applying line is electrically connected with the wiring adapter plate, and is electrically connected with the second probe through the wiring adapter plate.
Furthermore, the wiring adapter plate comprises a loading plate, a connecting layer is arranged on the loading plate, and the loading plate is electrically connected with the first probe through the connecting layer.
Furthermore, the connecting layer is made of multiple layers of organic materials or multiple layers of ceramic materials.
Further, the probe card is a vertical probe card.
According to another aspect of the present invention, a semiconductor testing apparatus is also disclosed, which includes the above probe card.
Further, the method also comprises the following steps: and the semiconductor testing machine is electrically connected with the signal sensing line.
Under the condition that adopts above-mentioned technical scheme, the utility model discloses a probe card and semiconductor testing arrangement are through setting up first probe to be connected signal perception line and the direct electricity of first probe, make signal perception line can directly acquire the signal of chip through first probe, reduce the pressure drop that the signal produced through the wiring keysets, improved the accuracy of signal greatly, thereby make the rate of accuracy of chip test improve greatly.
Drawings
Preferred embodiments of the present invention are described below with reference to the accompanying drawings, in which:
FIG. 1 is a schematic diagram of a semiconductor testing apparatus in the prior art;
fig. 2 is a schematic structural diagram of a probe card according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a semiconductor test apparatus according to an embodiment of the present invention;
list of reference numerals:
10. a wiring adapter plate; 11. loading a plate; 12. a connection layer; 20. a first probe; 21. a connecting projection; 22. a first probe; 30. a chip; 31. a bump; 40. a signal sensing line; 41. a first signal sensing line; 42. a second signal sensing line; 50. a second probe; 60. a signal applying line; 61. a first signal applying line; 62. a second signal applying line; 70. a semiconductor tester; 10', a wiring adapter plate; 20', a probe; 30', a chip; 40', signal sensing lines; 60', a signal applying line; 70', semiconductor tester.
Detailed Description
The present invention will be further described with reference to the following examples, but the scope of the present invention is not limited to the content of the description.
As shown in fig. 1, the semiconductor test apparatus in the related art includes a probe card and a semiconductor test machine 70', and the probe card is electrically connected to the semiconductor test machine 70' through a signal applying line 60 'and a signal sensing line 40', thereby realizing signal transmission. The probe card comprises a probe 20' and a wiring adapter plate 10', wherein the probe 20' is arranged on the wiring adapter plate 10', and a signal applying line 60' and a signal sensing line 40' are respectively connected to the wiring adapter plate 10' and are electrically connected with the probe 20' through the wiring adapter plate 10 '. In the process of performing the wafer test, the probes in the probe 20' are electrically connected to the chip 30' in the wafer, and the semiconductor tester 70' applies an electrical signal to the chip 30' through the signal applying line 60' and detects the applied signal through the signal sensing line 40', thereby implementing the test on the chip 30 '. However, since the signal sensing line 40' is connected to the wiring adaptor board 10', and a voltage drop occurs when the signal passes through the wiring adaptor board 10', the voltage obtained by the signal sensing line 40' is not the actual voltage of the chip 30', thereby affecting the test accuracy.
In order to solve the above problem, according to a first embodiment of the present invention, a probe card is provided, which is a vertical probe card for wafer level testing of chips 30. As shown in fig. 2, the probe card includes a first probe 20, a second probe 50, a wiring interposer 10, a signal sensing line 40, and a signal applying line 60. The first probe 20 and the second probe 50 are respectively fixed on the wiring adapter board 10, the first probe 20 is used for detecting the signal of the chip 30, and the second probe 50 is used for applying the signal to the chip 30. The signal sensing line 40 is directly electrically connected to the first probe 20 so as to directly acquire the signal of the chip 30 through the first probe 20. The signal applying line 60 is electrically connected to the wiring connection board 10, and the signal applying line 60 is electrically connected to the second probe 50 through the wiring connection board 10. When the chips 30 are placed on the probe card, each first probe 20 corresponds to a bump 31 on one chip 30, each second probe 50 also corresponds to a bump 31 on one chip 30, and the electrical connection of the PC to the chip 30 is established through probes or MEMS (micro electro mechanical system) pins inside the first probe 20 and the second probe 50. When the chip 30 is tested, the signal sensing line 40 can directly acquire the signal of the chip 30 through the first probe 20, and the signal does not need to pass through the wiring adapter plate 10, so that the voltage drop of the signal cannot be generated, the signal acquired by the signal sensing line 40 is more accurate, and the accuracy of the chip 30 test is greatly improved.
The utility model discloses a probe card is through setting up first probe 20 to be connected signal perception line 40 and the direct electricity of first probe 20, make signal perception line 40 can directly acquire chip 30's signal through first probe 20, reduce the signal and produce the pressure drop through wiring keysets 10, improved signal detection's accuracy greatly, thereby make the rate of accuracy of chip 30 test improve greatly.
In the first embodiment shown in fig. 2, the first probe 20 includes a connection protrusion 21 and a first probe 22, the connection protrusion 21 is disposed on the wiring adapter board 10, and the signal sensing line 40 is electrically connected to the connection protrusion 21; the first probe 22 is disposed on the connection protrusion 21, and the signal sensing line 40 is electrically connected to the first probe 22 through the connection protrusion 21. Through setting up connecting protrusion 21, on the one hand can be fixed first probe 22 and wiring keysets 10 through connecting protrusion 21, on the other hand, can also realize electric connection through connecting protrusion 21 between first probe 22 and the signal perception line 40 to the acquisition of chip 30 signal is realized, belongs to a typical dual-purpose thing.
It should be noted that, in the embodiment shown in fig. 2, the connection bump 21 is a pad. Besides the bonding pads, the first probe 22 and the wiring adapter board 10 can be connected by other methods, for example, in some embodiments not shown in the drawings, the first probe 22 and the wiring adapter board 10 can be fixedly connected by means of adhesion or structural members, and the signal sensing line 40 can also be directly welded with the first probe 22 without being electrically connected by the connecting protrusion 21, as long as the method of connecting the signal sensing line 40 to the first probe 22 and realizing signal transmission can be realized, which is within the protection scope of the present invention.
In the first embodiment shown in fig. 2, the first probe 20 includes a high voltage group and a low voltage group, and the signal sensing line 40 includes a first signal sensing line 41 and a second signal sensing line 42, wherein the first signal sensing line 41 is a high voltage side, and the first signal sensing line 41 is electrically connected to the high voltage group of the first probe 20; the second signal sensing line 42 is a low voltage side, and the second signal sensing line 42 is electrically connected to the low voltage group of the first probe 20.
Similarly, the second probe 50 includes a high voltage group and a low voltage group, and the signal applying line 60 includes a first signal applying line 61 and a second signal applying line 62, wherein the first signal applying line 61 is a high voltage side, and the first signal applying line 61 is electrically connected to the high voltage group of the second probe 50; the second signal applying line 62 is a low voltage side, and the second signal applying line 62 is electrically connected to the low voltage group of the second probe 50.
In testing, a current applied from the power supply flows from the first signal applying line 61 through the high voltage set of the second probe 50 through the chip 30, and then enters the second signal applying line 62 through the low voltage set of the second probe 50, thereby applying a test voltage to the chip 30. Meanwhile, the first signal sensing line 41 acquires the current flowing through one end of the chip 30 through the high voltage group of the first probe 20, and the second signal sensing line 42 acquires the current flowing through the other end of the chip 30 through the low voltage group of the first probe 20, so that the voltage at the two ends of the chip 30 can be detected.
Further, as shown in fig. 2, the wiring adapter board 10 includes a loading board 11, a connection layer 12 is disposed on the loading board 11, and the loading board 11 is electrically connected to the second probe 50 through the connection layer 12. The signal applying line 60 is electrically connected to the loading plate 11, and the signal applying line 60 is electrically connected to the second probe 50 through the loading plate 11 and the connection layer 12. It should be noted that the connection layer 12 is made of multiple layers of organic materials or multiple layers of ceramic materials, and in the specific implementation process, the connection protrusion 21 and the connection layer 12 are integrally formed, or the connection protrusion 21, the connection layer 12 and the loading plate 11 are integrally formed, in order to facilitate the process for manufacturing and installing the probe.
As shown in fig. 3, the present invention also discloses a semiconductor testing apparatus, which includes the probe card and the semiconductor testing machine 70, wherein the power supply of the semiconductor testing machine 70 is electrically connected to the signal sensing line 40 and the signal applying line 60, respectively. Specifically, the power supply is divided into a FORCE + terminal, a FORCE-terminal, a SENSE + terminal, and a SENSE-terminal, wherein the first signal sensing line 41 is electrically connected to the SENSE + terminal, the second signal sensing line 42 is electrically connected to the SENSE-terminal, the first signal applying line 61 is electrically connected to the FORCE + terminal, and the second signal applying line 62 is electrically connected to the FORCE-terminal. During testing, the semiconductor testing device applies voltage to the chip 30 through the signal applying line 60, the semiconductor testing device obtains the voltage of the chip 30 through the signal sensing line 40, and the signal sensing line 40 can directly obtain the voltage of the chip 30 through the first probe 20, so that voltage drop generated by signals is small, the signals obtained by the signal sensing line 40 are more accurate, and the accuracy of testing the chip 30 is greatly improved.
It should be noted that, the correspondence between the chinese terms in the above embodiments and the english commonly used in the art is as follows: wafer, bump, load Board, multi-layer organic material, multi-layer ceramic material, probe head, DIE, force line and Sense line.
So far, the technical solutions of the present invention have been described in connection with the preferred embodiments shown in the drawings, but it is easily understood by those skilled in the art that the scope of the present invention is obviously not limited to these specific embodiments. Equivalent changes or substitutions can be made on the related technical features by those skilled in the art without departing from the principle of the invention, and the technical scheme after the changes or substitutions will fall into the protection scope of the invention.
Claims (10)
1. A probe card, comprising:
a wiring adapter plate (10);
a first probe (20), wherein the first probe (20) is arranged on the wiring adapter plate (10), and the first probe (20) is used for detecting signals of a chip (30);
a signal sensing line (40), wherein the signal sensing line (40) is directly and electrically connected with the first probe (20) so as to directly acquire the signal of the chip (30) through the first probe (20).
2. Probe card according to claim 1, characterized in that said first probe head (20) comprises:
the connecting protrusion (21), the connecting protrusion (21) is arranged on the wiring adapter plate (10), and the signal sensing line (40) is electrically connected with the connecting protrusion (21);
a first probe (22) disposed on the connection protrusion (21), the signal sensing line (40) being electrically connected with the first probe (22) through the connection protrusion (21).
3. The probe card of claim 2,
the connecting protrusion (21) and the wiring adapter plate (10) are integrally formed.
4. The probe card of claim 1 or 2,
the signal sensing line (40) comprises a first signal sensing line (41) and a second signal sensing line (42), the first signal sensing line (41) and the second signal sensing line (42) are respectively and electrically connected with different first probes (20), and the voltage on one side of the first signal sensing line (41) is higher than the voltage on one side of the second signal sensing line (42).
5. The probe card of claim 1, further comprising:
a second probe (50), the second probe (50) being disposed on the wiring interposer (10), the second probe (50) being electrically connected to the wiring interposer (10), the second probe (50) being for applying a signal to the chip (30);
a signal application line (60), the signal application line (60) being electrically connected to the wiring adaptor board (10), the signal application line (60) being electrically connected to the second probe (50) through the wiring adaptor board (10).
6. The probe card of claim 5,
the wiring adapter plate (10) comprises a loading plate (11), a connecting layer (12) is arranged on the loading plate (11), and the loading plate (11) is electrically connected with the second probe (50) through the connecting layer (12).
7. The probe card of claim 6,
the connecting layer (12) is made of multiple layers of organic materials or multiple layers of ceramic materials.
8. The probe card of claim 1,
the probe card is a vertical probe card.
9. A semiconductor test apparatus comprising the probe card according to any one of claims 1 to 8.
10. The semiconductor test apparatus of claim 9, further comprising:
a semiconductor testing machine (70), the semiconductor testing machine (70) being electrically connected to the signal sense line (40).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202221586924.0U CN218099323U (en) | 2022-06-22 | 2022-06-22 | Probe card and semiconductor test apparatus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202221586924.0U CN218099323U (en) | 2022-06-22 | 2022-06-22 | Probe card and semiconductor test apparatus |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN218099323U true CN218099323U (en) | 2022-12-20 |
Family
ID=84477329
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202221586924.0U Active CN218099323U (en) | 2022-06-22 | 2022-06-22 | Probe card and semiconductor test apparatus |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN218099323U (en) |
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2022
- 2022-06-22 CN CN202221586924.0U patent/CN218099323U/en active Active
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