CN1250588A - 用于在电绝缘的底座上形成金属的线路图的方法 - Google Patents
用于在电绝缘的底座上形成金属的线路图的方法 Download PDFInfo
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- 238000001465 metallisation Methods 0.000 claims abstract description 18
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 15
- 229910052802 copper Inorganic materials 0.000 claims description 14
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- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims 2
- 229910001128 Sn alloy Inorganic materials 0.000 claims 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 1
- 229910052737 gold Inorganic materials 0.000 claims 1
- 239000010931 gold Substances 0.000 claims 1
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Abstract
为了在绝缘的底座(U1)上形成金属的、具有可焊的和/或可键合的连接范围(CA1、LA1)的线路图,首先,金属化覆层被覆到底座上并至少在与所需的线路图交界的范围内重新被去除。然后,把可焊的和/或可键合的终端表面(E)电镀淀积到连接范围(CA1、LA1)上。净化室条件是不需要的。
Description
US-A-4 804 615公开了一种用于形成具有可焊的连接范围的、金属的线路图的方法，该方法从双侧覆铜的、电绝缘的、平的底座出发。在钻出金属化孔之后，一铜层在化学的淀积槽浴中被淀积，该铜淀积层也沿孔壁伸展。然后，一层抗电镀剂被覆到上述被淀积的铜层上，所述的抗电镀剂唯独不覆盖后来的连接范围，据此，在后来的连接范围上可以电镀方式相继淀积铜和锡-铅合金。其中，锡-铅合金形成连接范围的可焊的终端表面。在完全去除抗电镀剂之后，涂覆抗蚀剂，该抗蚀剂覆盖后来的线路图的整个范围，其中的连接范围除外。随后，以化学方式淀积的铜层的和铜镀覆层的所有的、不是线路图的范围被蚀刻掉，直到蚀刻至底座的表面为止。在该蚀刻过程中，不仅是原来的抗蚀剂，而且还有连接范围的抗蚀的终端表面均保护处于其下方的铜，使其免受腐蚀。在完全去除抗蚀剂之后，覆上止焊胶，该止焊胶唯独不覆盖线路图的可焊的连接范围。
US-A-4 608 274公开了一种用于形成具有可焊的连接范围的、金属的线路图的方法，该方法从预先钻过孔的、电绝缘的、平的底座出发，在底座两侧和在孔中无电地淀积铜之后，抗蚀刻被涂覆到铜层上，上述抗蚀剂覆盖后来的线路图的所有范围，后来的连接范围除外。随后，敷上抗电镀剂，该抗电镀剂唯独不覆盖后来的连接范围，据此，在后来的连接范围上可以电镀方式相继淀积铜和锡-铅合金。在完全去除抗电镀剂之后，暴露的铜层的所有范围被蚀刻掉，直到蚀刻至底座的表面为止，届时，在线路图的范围内，抗蚀剂和连接范围的抗蚀的终端表面均保护处于其下方的铜层，使其免受腐蚀。在全部去除抗蚀剂之后，也重新敷上止焊胶。该止焊胶唯独不覆盖线路图的可焊的连接范围。
WO 95/29573公开了另一种用于在电绝缘的底座上形成具有可焊的和/或可键合的连接范围的、金属的线路图的方法。该方法包括如下方法步骤：
1)把金属化覆层覆到底座上，
2)在电浸渍槽浴中把一有机的、抗电镀和抗蚀的保护层覆到金属
化覆层上，
3)借助激光辐射去除后来的连接范围中的保护层，
4)通过电镀把抗蚀的、可焊的和/或可键合的终端表面淀积到金属
化覆层的在方法步骤3)中暴露的范围，
5)借助激光辐射去除至少在紧靠后来的线路图的范围中的保护
层，
6)蚀刻掉金属化覆层的在方法步骤5)中暴露的范围，直到蚀刻至
底座的表面为止。
上述方法的优点特别是在于，在电浸渍槽浴中只须覆上一层唯一的、有机的保护层，该保护层在借助激光辐射第一次建立结构之后用作抗电镀剂和在借助激光辐射第二次建立结构之后用作抗蚀剂并且在形成线路图之后也无需被去除。根据情况，事前被用作抗电镀剂和抗蚀剂的保护层尚还可附加地被用作止焊掩膜。
有WO 96/09646中描述了一种所谓的、由聚合物构成的柱状栅阵列(Polymer Stud Grid Array，简称PSGA)，该PSGA兼有球状栅阵列(Ball Grid Array，简称BGA)和MID工艺两者的优点。其中，把新的结构形式称作聚合物构成的柱状栅阵列)(PSGA)的根据是球状栅阵列(BGA)，其中，概念“由聚合物构成的柱”应提及在注塑底座时一并被成型的、由聚合物构成的凸起。新的适合于单、少或多芯片模件的结构形式包括
-注塑的、三维的、由电绝缘的聚合物构成的底座，
-呈面状位于底座的下侧上的、在注塑中被一并成型的、由聚合物构成的凸起，
-在由聚合物构成的凸起上通过可焊的终端表面形成的外接头，
-至少在底座的下侧上形成的、用以使外接头与内接头相连的线路和
-至少一个位于底座上的芯片，该芯片的接头与内接头导电地相连。
在权利要求1中所描述的本发明的任务在于，提供一种简单的和经济的、用于在电绝缘的底座上形成具有可焊的和/或可键合的连接范围的、金属的线路图的方法，该方法特别是还适于建立挠性电路和由聚合物构成的柱状栅阵列(PSGA)。在该方法中，在对现代化芯片封装提出的要求方面，应在底座上形成具有极显微的结构的线路图。
发明的解决问题的技术方案的基础是借助激光建立显微结构，使在譬如5×5cm2的加工面上在没有净化室的条件下能实现导线宽度为约80微米的和绝缘距离为30微米的结构。据此，在单列或多列芯片接头和多列线路板接头之间可实现密集的、单层的布线。
在从属权利要求中描述了发明的优选的实施形式。
在附图中示出了发明的实施例，下面详细描述这些实施例。
附图所示为：
图1至8以极简化的示意形式示出了在电绝缘的底座上形成金属的、具有可焊的连接范围的线路图时的不同的方法阶段，
图9具有位于薄膜的相互面对的侧上的连接范围的、薄膜结构的底座的截面图，
图10具有在集成的、由聚合物构成的凸起上形成的连接范围的PSGA截面，
图11线路图的各条导线的导电连接的一个实施例，
图12具有单侧设置的芯片接头的挠性电路的第一实施例，
图13具有双列设置的芯片接头的挠性电路的第二实施例。
按照图1，发明的方法从电绝缘的底座U1出发，该底座U1在所述的实施例为一柔性薄膜。
为了提高以后待覆的线路图的附着强度，在图1中示出的底座U1首先被蚀镂并随后被清洗。在清洗过后，譬如通过浸入Pd-Cl2-SnCl2槽浴使底座长出在附图中不能详细看出的籽晶。
在籽晶活化后，一层可在图2中看到的金属化覆层M1被覆到底座U1上，其中，该金属化覆层通过一无外电地化学淀积的铜层被形成。根据情况，金属化层M1还可通过随后进行的铜的电镀淀积得以加厚。
随后，按照图3，借助激光辐射LS，在紧靠所需的线路图的范围内去除金属化覆层M1，其去除准则在于，线路图的各条导线L1保持相互电气连接。在后文中，将结合图11详细说明各条导线L1的在图3中看不出的电气连接。
随后，如图4所示，在电浸渍槽浴中，一层有机的、抗电镀的保护层S被敷到线路图上，届时，线路图的相互电气连接的导线L1根据电浸渍槽浴的具体结构被阳极地或阴极地键合。
按照图5，保护层S也可被用作抗蚀刻，届时，金属化覆层M1的所有不是线路图的范围在一个相应的蚀刻槽浴中被去除。可是，金属化覆层M1的不是线路图的范围也可保留在底座U1上并且后来譬如被用作电磁屏蔽。在后一情况下，金属化覆层M1的保留的范围同样被阳极地或阴极地键合并被覆加保护层S。
图6以底座U1的相对于图5转90°的截面形式示出了导线L1的和覆于其上的保护层S的纵向伸展情况。
如图7所示，保护层S现借助激光辐射LS在线路图的后来的连接范围中重新被去除。在图7中可看到后来待用作芯片接头的连接范围CA1和后来待用作线路板接头的连接范围LA1。
随后，如图8所示，一个可焊的终端表面E通过金属的电镀淀积被覆到线路图的借助激光辐射被暴露了的范围上。在图示的实施例中，该终端表面E是一种锡-铅合金。
图9示出了一个派生形式，在该派生形式中，通过挠性薄膜构成的底座U1在后来用作芯片接头的连接范围CA1的范围内具有金属化孔DL。据此，在底座U1的下侧上可设置线路板接头结构的连接范围LA1和由此引出的导线L1，而芯片接头结构的连接范围CA1被设在底座U1的上侧上。其中，芯片接头结构的连接范围CA1通过可焊的终端表面E的电镀淀积在金属化孔DL的范围内被建立。
图10示出了另一实施例，在该实施例中，图1至8所述的方法步骤被用于建立由聚合物构成的柱状栅阵列。在该实施例中，采用三维的，通过注塑热塑性成型料建立的底座U2，在注塑时，呈面状位于底座U2的下侧上的、由聚合物构成的凸起被一并成型。此外，从该图中还可看到的是，在注塑时，还在底座U2的下侧上一并成型出用于容纳芯片的凹穴M并且在注塑时，在该凹穴M的范围内同样地一并成型出由聚合物构成的凸起PH。然后，芯片接头结构的连接范围CA2被建立在这些由聚合物构成的凸起PH上。线路板接头结构的连接范围LA2和芯片接头结构的连接范围CA2之间的连接是通过导线L2进行的。保护层S覆盖线路图的所有的、不是连接范围LA2和CA2的范围。
图11示出了一个对线路图的导线L1进行导电连接的实施例。该连接是通过一个横向桥形接片QS进行的，该横向桥形接片QS使所有的芯片接头结构的连接范围CA1相互连接。然后，该横向桥形接片QS在电浸渍槽浴中涂覆保护层S时，根据槽浴的具体结构形式被阳极或阴极地键合。在电镀淀积终端表面之后，横向桥形接头QS可譬如通过冲压被切除。另一简单的和经济的可能性在于，借助激光辐射，从所属的连接范围去除横向桥形接片QS。
图12示出了挠性电路的第一实施例，在该挠性电路中，芯片接头结构的连接范围CA1和导线L1被形成在底座U1的一侧上。其中芯片接头结构的连接范围CA1单列地位于底座U1的边部。线路板接头结构的连接范围LA1两列地位于底座U1的另一侧上。这些线路板接头的建立是根据结合图9所述的方法步骤在金属化孔的范围内进行的，而在图12中没有详细示出这些金属化孔。
图13示出了挠性电路的第二实施例，该挠性电路中，与图12所示的实施形式的区别在于，规定了两列相互交错设置的、芯片接头结构的连接范围CA1。通过连接范围CA1的两列交错设置，可在各导线L1之间实现特别小的绝缘距离。
Claims (20)
1.用于在电绝缘的底座(U1、U2)上形成金属的、具有可焊的和/或可键合的连接范围(CA1、LA1、CA2、LA2)的线路图的方法，具有如下方法步骤：
1)把金属化覆层(M1、M2)覆到底座(U1、U2)上，
2)至少在紧靠所需的线路图的范围内去除金属化覆层(M1、M2)，
其去除准则在于，线路图的各条导线(L1、L2)保持电气相互
连接，
3)在电浸渍槽浴中，把一有机的、抗电镀的保护层(S)覆到线路
图上，
4)去除后来的连接范围(CA1、LA1、CA2、LA2)中的保护层(S)，
5)把可焊的和/或可键合的终端表面(E)电镀淀积到金属化覆层
(M1、M2)的在方法步骤4)中被暴露了的范围上。
2.按照权利要求1所述的方法，其特征在于，挠性薄膜被用作底座(U1)。
3.按照权利要求2所述的方法，其特征在于，线路板接头结构的连接范围(LA1)和由此引出的线路(LZ1)被布置在底座(U1)的下侧上，并且芯片接头结构的连接范围(CA1)被布置在底座(U1)的上侧上，其中，芯片接头结构的连接范围(CA1)通过在金属化孔(DL)的范围中电镀淀积可焊的和/或可键合的终端表面(E)被建立。
4.按照权利要求1所述的方法，其特征在于，三维的、通过注塑热塑性成型料建立的底座(U2)被采用。
5.按照权利要求4所述的方法，其特征在于，呈面状布置的、由聚合物构成的凸起(PS)在注塑时被一并成型在底座(U2)的下侧上、并且线路板接头结构的连接范围(LA2)被建立在这些由聚合物构成的凸起(PS)上。
6.按照权利要求5所述的方法，其特征在于，在注塑时，用于容纳芯片的凹穴(M)被成型在底座(U2)的下侧上并且由聚合物构成的凸起(PS)被布置在凹穴范围之外。
7.按照权利要求6所述的方法，其特征在于，在注塑时，由聚合物构成的凸起(PH)被一并成型在凹穴(M)的范围中并且芯片接头结构的连接范围(CA2)被建立在这些由聚合物构成的凸起(PH)上。
8.按照以上权利要求之一所述的方法，其特征在于，金属化覆层(M1、M2)通过化学的金属淀积被覆到底座(U1、U2)上。
9.按照权利要求8所述的方法，其特征在于，金属化覆层(M1、M2)通过铜的化学淀积被建立。
10.按照权利要求8或9所述的方法，其特征在于，金属化覆层(M1、M2)在其建立结构之前或之后在方法步骤2)中通过电镀淀积金属被加厚。
11.按照权利要求10所述的方法，其特征在于，金属化覆层(M1、M2)通过电镀淀积铜被加厚。
12.按照以上权利要求之一所述的方法，其特征在于，借助激光建立显微结构，在方法步骤2)中，局部地去除金属化覆层(M1、M2)。
13.按照权利要求12所述的方法，其特征在于，在借助激光建立显微结构时，具有宽度(b)约35～45微米和绝缘距离(a)约25-35微米的线路被建立。
14.按照以上权利要求之一所述的方法，其特征在于，金属化覆层(M1、M2)全面地被覆到底座(U1、U2)上。
15.按照权利要求1所述的方法，其特征在于，在方法步骤(3)中，在电浸渍槽浴中，作为保护层(S)，一种耐热的、适用作止焊掩膜的胶被覆到线路图上。
16.按照权利要求15所述的方法，其特征在于，保护层(S)在覆到线路图上之后被干燥。
17.按照权利要求15或16所述的方法，其特征在于，在方法步骤4)中建立结构后保留的保护层(S)被固化。
18.按照以上权利要求之一所述的方法，其特征在于，在方法步骤4)中，通过激光建立结构，建立保护层(S)的结构。
19.按照以上权利要求之一所述的方法，其特征在于，在权利要求1的方法步骤3)中或在权利要求2的方法步骤5)中，作为终端表面(E)，锡或锡-铅合金被淀积。
20.按照以上权利要求之一所述的方法，其特征在于，在权利要求1的方法步骤3)中或在权利要求2的方法步骤5)中，作为终端表面(E)，镍和金被淀积。
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| DE19709954 | 1997-03-11 |
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| CN103094126A (zh) * | 2013-01-16 | 2013-05-08 | 东莞市凯昶德电子科技股份有限公司 | 陶瓷元器件细微立体导电线路的制备方法 |
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| US20020140096A1 (en) * | 2001-03-30 | 2002-10-03 | Siemens Dematic Electronics Assembly Systems, Inc. | Method and structure for ex-situ polymer stud grid array contact formation |
| US6815126B2 (en) | 2002-04-09 | 2004-11-09 | International Business Machines Corporation | Printed wiring board with conformally plated circuit traces |
| DE10217700A1 (de) * | 2002-04-20 | 2003-11-06 | Festo Ag & Co | Spritzgegossener Schaltungsträger und damit ausgestattete elektrische Schaltungsanordnung |
| DE10217698B4 (de) * | 2002-04-20 | 2008-04-24 | Festo Ag & Co. | Elektrische Schaltanordnung mit einem spritzgegossenen Schaltungsträger |
| US20050031840A1 (en) * | 2003-08-05 | 2005-02-10 | Xerox Corporation | RF connector |
| US7052763B2 (en) * | 2003-08-05 | 2006-05-30 | Xerox Corporation | Multi-element connector |
| DE102006033269B4 (de) * | 2006-07-18 | 2010-10-28 | Continental Automotive Gmbh | Verfahren zum Herstellen einer Anordnung mit einem flexiblen Leiterträger, einer Basisplatte und einem Dichtkörper |
| DE102006037093B3 (de) * | 2006-08-07 | 2008-03-13 | Reinhard Ulrich | Fügeverfahren und Vorrichtung zum Verlegen von dünnem Draht |
| CN103545222B (zh) * | 2013-10-24 | 2017-04-26 | 中国电子科技集团公司第四十一研究所 | 一种高可靠性软介质电路的加工制作方法 |
| DE102014206558A1 (de) * | 2014-04-04 | 2015-10-08 | Robert Bosch Gmbh | Verfahren zum Herstellen eines MID-Schaltungsträgers und MID-Schaltungsträger |
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| JPS5559795A (en) | 1978-10-30 | 1980-05-06 | Nippon Electric Co | Printed circuit board and method of manufacturing same |
| US4608274A (en) | 1982-08-06 | 1986-08-26 | Faultless Pcbs | Method of manufacturing circuit boards |
| US4804615A (en) | 1985-08-08 | 1989-02-14 | Macdermid, Incorporated | Method for manufacture of printed circuit boards |
| EP0370133A1 (de) * | 1988-11-24 | 1990-05-30 | Siemens Aktiengesellschaft | Verfahren zur Herstellung von Leiterplatten |
| JP2753746B2 (ja) | 1989-11-06 | 1998-05-20 | 日本メクトロン株式会社 | Ｉｃ搭載用可撓性回路基板及びその製造法 |
| US5160579A (en) | 1991-06-05 | 1992-11-03 | Macdermid, Incorporated | Process for manufacturing printed circuit employing selective provision of solderable coating |
| JP3159841B2 (ja) | 1993-08-26 | 2001-04-23 | ポリプラスチックス株式会社 | レーザーによる回路形成方法及び導電回路形成部品 |
| WO1995029573A1 (de) | 1994-04-25 | 1995-11-02 | Siemens S.A. | Verfahren zur bildung metallischer leitermuster auf elektrisch isolierenden unterlagen |
| ATE194249T1 (de) * | 1994-09-23 | 2000-07-15 | Siemens Nv | Polymer stud grid array package |
| JP3645926B2 (ja) * | 1994-11-17 | 2005-05-11 | ポリプラスチックス株式会社 | 回路形成方法及び導電回路形成部品 |
| JPH08167769A (ja) * | 1994-12-12 | 1996-06-25 | Polyplastics Co | レーザーによる回路形成方法及び導電回路形成部品 |
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| CN103094126A (zh) * | 2013-01-16 | 2013-05-08 | 东莞市凯昶德电子科技股份有限公司 | 陶瓷元器件细微立体导电线路的制备方法 |
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| KR100333775B1 (ko) | 2002-04-25 |
| JP3442403B2 (ja) | 2003-09-02 |
| CN1173614C (zh) | 2004-10-27 |
| ATE209846T1 (de) | 2001-12-15 |
| JP2000513152A (ja) | 2000-10-03 |
| WO1998041070A1 (de) | 1998-09-17 |
| KR20000076177A (ko) | 2000-12-26 |
| EP0968631B1 (de) | 2001-11-28 |
| DE59802234D1 (de) | 2002-01-10 |
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| EP0968631A1 (de) | 2000-01-05 |
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