CN1231968C - 一种芯片倒装焊封装结构 - Google Patents

一种芯片倒装焊封装结构 Download PDF

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CN1231968C
CN1231968C CNB02160567XA CN02160567A CN1231968C CN 1231968 C CN1231968 C CN 1231968C CN B02160567X A CNB02160567X A CN B02160567XA CN 02160567 A CN02160567 A CN 02160567A CN 1231968 C CN1231968 C CN 1231968C
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chip
shape
welding
solder joint
substrate
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CN1512573A (zh
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杜黎光
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Riyueguang Packaging & Test (shanghai) Co., Ltd.
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WEIYU TECH TEST PACKING Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

本发明涉及一种芯片倒装焊封装结构。传统的封装结构存在着因芯片与基板材料不同，由热膨胀引起的边缘焊点易开裂的现象。本发明的芯片倒装焊封装结构，包括芯片和基板，所述芯片上的焊点与所述基板上的焊盘相对应，且通过焊接工艺焊接在一起，其特征在于，所述芯片焊点的形状从中心向外逐渐扩大，所述基板上的焊盘的形状相应地从中心向外逐渐扩大。所述芯片外围焊点的形状呈长方形，其径向与从所述芯片中央向外的延伸线相一致；所述基板外围焊盘的形状呈长方形，其径向与从所述基板中央向外的延伸线相一致。焊点和焊盘的形状也可以是椭圆形或泪滴形等。

Description

一种芯片倒装焊封装结构
技术领域
本发明涉及集成电路封装技术，尤其涉及一种芯片倒装焊封装结构。
背景技术
倒装焊(Flip Chip)工艺是一种取代常用的丝焊(wire bonding)工艺的用于芯片和外界电互连的先进的封装技术。其优势在于电性能好，适合高速高密度电子器件的应用。图1示出了这种倒装焊技术的流程图。
如图1所示，该倒装焊技术的大致流程为：
在衬底层100具到焊盘101的一面上，通过滴嘴110滴涂助焊剂，在衬底层100表面上形成助焊剂层120；(如图1A所示)
然后，把待封装的芯片130倒置到衬底层100上，使芯片130上的焊点131与衬底层100上的焊盘101对齐；(如图1B所示)
然后，用再流焊工艺使芯片130上的焊点131与衬底层100上的焊盘101之间键合(即电连接)；(如图1C所示)
然后，清洗衬底层100与芯片130之间的助焊剂层120；(如图1D所示)
然后，在衬底层100与芯片130之间充填底充胶，底充胶靠表面张力自行流入芯片130与基板100间的间隙，形成底充胶层140；(如图1E所示)
最后，对底充胶层140进行加热固化，完成倒装焊，将芯片焊接到基板上。(如图1F所示)
这种倒装焊的缺点在于：芯片130上的焊点131的形状以及衬底层100上的焊盘101的形状大都采用圆形等形状，且，无论处于中央位置还是边缘位置的焊点或焊盘，其形状和大小都是一致的。而由于芯片130和有机衬底层100的热膨胀系数不同，造成器件在制造过程中和工作时由于热失配导致焊点可靠性下降。主要表现在，距离芯片中心越远的焊点越容易出现焊点开裂现象。这是因为，由于热膨胀效应，芯片或衬底层周围受力的程序要大于中央位置，位置出现边缘焊点开裂严重的情况。
发明内容
因此，本发明的目的在于提供一种新颖的芯片倒装焊封装结构，以克服上述边缘焊点易开裂的现象。
根据本发明的芯片倒装焊封装结构，包括芯片和基板，所述芯片上的焊点与所述基板上的焊盘相对应，且通过焊接工艺焊接在一起，所述芯片焊点的形状从中心向外逐渐扩大，所述基板上的焊盘的形状相应地从中心向外逐渐扩大，所述芯片外围焊点的形状呈泪滴形，其径向与从所述芯片中央向外的延伸线相一致，且所述泪滴形外围焊点较大的一端向外；所述基板外围焊盘的形状呈泪滴形，其径向与从所述基板中央向外的延伸线相一致，且所述泪滴形外围焊盘较大的一端向外。
本发明中，由于将芯片上的焊点以及基板上的焊盘作了如上的改进，将外缘处的焊点和焊盘的形状作了扩大，这样，可以有效地抵消由于热膨胀不一致造成的边缘易开裂的情况。
附图说明
图1是一种传统的倒装焊工艺的流程图；
图2是传统的芯片焊点的分布和形状示意图；
图3示出了本发明的芯片的焊点或基板上的焊盘的形状和分布示意图；
图4示出了本发明的又一种芯片的焊点或基板上的焊盘的形状和分布示意图。
具体实施方式
本发明的整体封装结构与传统的基本相同，包括芯片和基板，芯片上具有多个焊点，一般呈阵列状。相应地，基板上也具有多个焊盘，也呈阵列状。芯片上的焊点与基板上的焊盘通过常规的焊接工艺焊接在一起。
本发明的改进之处在于，改进了芯片上的焊点以及基板上的焊盘的形状。图3示意性的示出了几种芯片和基板上的焊点和焊盘的形状以及分布情况。从图3各图中可以看出，本发明对芯片和基板的焊点以及焊盘的主要改进点是，使芯片的焊点的形状从中心向外逐渐扩大，对基板上的焊盘的形状也作了相应的改动。
图3A示出了芯片外围焊点的形状呈长方形的例子，焊点的径向与从芯片中央向外的延伸线相一致；基板外围焊盘的形状也呈长方形，其径向与从基板中央向外的延伸线相一致。
图3B示出了芯片外围焊点的形状呈椭圆形的例子，焊点的径向与从芯片中央向外的延伸线相一致；基板外围焊盘的形状也呈椭圆形，其径向与从基板中央向外的延伸线相一致。
图3C示出了芯片外围焊点的形状呈泪滴形的例子，焊点的径向与从芯片中央向外的延伸线相一致，且泪滴形外围焊点较大的一端向外；基板外围焊盘的形状也呈泪滴形，其径向与从基板中央向外的延伸线相一致，且泪滴形外围焊盘较大的一端向外。
图3D示出了芯片外围焊点的形状呈圆形的例子，外围焊点沿芯片中央向外的延伸线逐渐扩大；基板外围焊盘的形状也作了相应的改进。
在图3的实施例中，为方便和清楚起见，仅例举了3*3阵列的芯片焊点结构。但本领域技术人员应当理解，本发明的上述构思同样可以应用于更多行列的阵列中，图4示出了一个9*9阵列的例子，从图4中可以看出，中间一组3*3阵列的焊点或焊盘形状不变，而其周围的焊点或焊盘从中心向外逐渐扩大。

Claims (1)

1、芯片倒装焊封装结构，包括芯片和基板，所述芯片上的焊点与所述基板上的焊盘相对应，且通过焊接工艺焊接在一起，所述芯片焊点的形状从中心向外逐渐扩大，所述基板上的焊盘的形状相应地从中心向外逐渐扩大，所述芯片外围焊点的形状呈泪滴形，其径向与从所述芯片中央向外的延伸线相一致，且所述泪滴形外围焊点较大的一端向外；所述基板外围焊盘的形状呈泪滴形，其径向与从所述基板中央向外的延伸线相一致，且所述泪滴形外围焊盘较大的一端向外。
CNB02160567XA 2002-12-30 2002-12-30 一种芯片倒装焊封装结构 Expired - Fee Related CN1231968C (zh)

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CN109037113A (zh) * 2018-08-17 2018-12-18 桂林电子科技大学 一种实现倒装焊芯片焊点灌封及打磨的装夹装置
CN109784458B (zh) * 2019-03-18 2024-04-05 上扬无线射频科技扬州有限公司 一种适于倒装焊的电子标签芯片及带温度传感器的无源超高频rfid标签
CN110660771B (zh) * 2019-10-09 2021-03-30 中新国际联合研究院 一种半导体封装中焊点形状的优化结构
CN118070749B (zh) * 2024-04-17 2024-07-23 淄博芯材集成电路有限责任公司 一种基板收缩方法

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