CN1217834A - Circuit arrangement for generating random bit sequences - Google Patents
Circuit arrangement for generating random bit sequences Download PDFInfo
- Publication number
- CN1217834A CN1217834A CN97194365A CN97194365A CN1217834A CN 1217834 A CN1217834 A CN 1217834A CN 97194365 A CN97194365 A CN 97194365A CN 97194365 A CN97194365 A CN 97194365A CN 1217834 A CN1217834 A CN 1217834A
- Authority
- CN
- China
- Prior art keywords
- oscillator
- circuit arrangement
- random bit
- vco1
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B29/00—Generation of noise currents and voltages
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/84—Generating pulses having a predetermined statistical distribution of a parameter, e.g. random pulse generators
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
- H04L9/065—Encryption by serially and continuously modifying data stream elements, e.g. stream cipher systems, RC4, SEAL or A5/3
- H04L9/0656—Pseudorandom key sequence combined element-for-element with data sequence, e.g. one-time-pad [OTP] or Vernam's cipher
- H04L9/0662—Pseudorandom key sequence combined element-for-element with data sequence, e.g. one-time-pad [OTP] or Vernam's cipher with particular pseudorandom sequence generator
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- Engineering & Computer Science (AREA)
- Computer Security & Cryptography (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
A circuit arrangement for generating random bit sequences has a first oscillator (OSZ1) and a second oscillator (VCO1) whose outputs are connected to the inputs of a phase detector (PD) that generates the random bit sequence. The second oscillator (VCO1) is frequency modulated.
Description
In many data handling procedures, especially in encryption technology, bit sequence needs the Random assignment bit sequence.The length of this definite random bit sequences can be decided as random number.
The so-called pseudo random number of general application, its shift register by feedback produces.Pseudo random number is at random, and can not be connected to next value with bigger number pseudorandom number generator in succession.It does not contain the periodicity relevant with the length of applied shift register.The dateout of shift register is relevant with the structure of input data and shift register in addition.
Also do not know the effective random number in the digital circuit till now.
The task of foregoing invention is to provide the circuit arrangement that is used to produce effective random bit sequences.
This task solves by the circuit arrangement of claim 1.The favourable improvement of the present invention provides in the dependent claims.
In circuit arrangement of the present invention, the respective phase of output signal is analyzed the numeral of two oscillators.Oscillator is with the hunting of frequency of approximately constant, and another oscillator is with this frequency modulation(FM).Quantizing noise has been arranged the frequency shift (FS) of being satisfied.So existing random bit sequences can be used as random number.
In improvement of the present invention, preferably carry out frequency modulation(FM) by other with the oscillator of another hunting of frequency in especially favourable mode.Its output signal preferably contains sawtooth waveforms.Another oscillator can carry out frequency modulation(FM) by additional oscillator in of the present invention another improves and this oscillator can be modulated.
Warbled oscillator is realized as voltage-controlled oscillator with favourable structure, so that it can directly be controlled by the output signal of another oscillator.
The detection of phase place can be favourable realize by shift register in simple mode that especially its data input pin is preferably by the modulation by the oscillator signal constant frequency of warbled oscillator signal and its input end of clock.
Oscillator with constant frequency is replaced by warbled oscillator in improvement of the present invention.
Shift register feeds back in favourable improvement of the present invention.
Explain the present invention below by accompanying drawing in detail by means of embodiment.Figure is
Fig. 1 is the schematic diagram of circuit arrangement of the present invention,
Fig. 2 is the schematic diagram of voltage-controlled oscillator.
Exporting 2 according to the first input end of Fig. 1 phase detectors PD by second output signal of the first oscillator OSZ1 loads.Second input of phase detectors PD loads by second output signal output 2 of the first voltage-controlled oscillator VCO1.
Second output signal output 2 of oscillator OSZ1, VCO1 is square waves.Oscillator OSZ1, VCO1 provide the output signal output 1 with about zigzag fashion.
The first voltage-controlled oscillator VCO1 is by the second voltage-controlled oscillator VCO2 control, this is actual in another voltage-controlled oscillator, it does not illustrate but indicates by line, by having the free-running second oscillator OSZ2 control of first output signal output 1.The first oscillator OSZ1 constitutes as voltage-controlled oscillator in principle, and its a plurality of oscillators by one or a chain or voltage-controlled oscillator are with its output signal output 1 control.This indicates by the oscillator OSZ of line in Fig. 1.
Phase detectors PD constitutes by the shift register that the professional is familiar with in an advantageous manner.This in a preferred manner second output signal output 2 of first oscillator 1 be transferred to the data input pin of shift register, and second output signal of first voltage-controlled oscillator output 2 is transferred to the input end of clock of shift register.Also can in principle, second output signal output 2 of the first voltage-controlled oscillator VCO1 is applied to data input pin, and second output signal of first oscillator OSZ1 output 2 has been applied to the input end of clock of the shift register of phase detectors PD effect.
The formation that in favourable improvement of the present invention, can feed back as the shift register of phase detectors PD.Carry out logical transition by data input signal and be transferred to the input of shift register then in the output signal of this shift register.Can and feed back to input with the conversion of the centre tap signal logic of shift register in addition.
Fig. 2 shows the principle assumption diagram of the oscillator of digital voltage control.The output of inverter INV links to each other with the earth terminal by capacitor C and links to each other with the input of the comparator ST that constitutes as schmitt trigger in addition.The output output 2 of comparator ST provides the signal of about rectangle and feeds back to the input of inverter INV.If for example the output state of inverter INV is " 1 ", capacitor C is recharged.If the voltage on the capacitor C has surpassed the division of a ci poem value of comparator ST, so switch:, show as logical one also constituting the output output 2 of oscillator output end.It can feed back to the input of inverter INV, so that this state becomes logical zero at output.Again discharge from capacitor C with this, so that comparator ST switched again according to the known time.Have the oscillatory regime of one-period at this, its frequency mainly resistance in the load circuit of the capacitance by capacitor C and inverter INV is determined.This resistance can controllablely constitute, p-for example shown in Figure 1 and n-MOS transistor, its be connected between the p-MOS transistor of positive power supply voltage terminal and distinctive inverter respectively and the n-MOS transistor of inverter and negative power supply voltage terminal between.This controllable inverter INV must have access to control signal input 1, the input 2 of two complementations.
The fundamental frequency of voltage-controlled oscillator is determined by the size of the capacitance of capacitor C.The variation of frequency realizes by the changes in resistance of the load of inverter INV by means of control signal input 1, input 2.
Contain an output in addition, it provides first output signal output 1 with about sawtooth waveform, and links to each other with capacitor C.
Can produce effective random bit sequences by circuit arrangement of the present invention, it can be applied in the data handling procedure of encryption technology as random number.
Claims (7)
1. be used to produce the circuit arrangement of random bit sequences, have one first oscillator (OSZ1) and one second oscillator (VCO1), its output provides the input of the phase detectors (PD) of random bit sequences to link to each other with preparation, and wherein second oscillator (VCO1) is by frequency modulation(FM).
2. circuit arrangement as claimed in claim 1 is characterized in that, second oscillator (VCO1) constitutes as voltage-controlled oscillator, and by the 3rd oscillator (VCO2) control.
3. circuit arrangement as claimed in claim 2 is characterized in that, the 3rd oscillator (VCO2) constitutes as voltage-controlled oscillator, and by the 4th oscillator (OSZ2) control.
4. as the circuit arrangement of one of above-mentioned claim, it is characterized in that phase detectors (PD) constitute by shift register.
5. circuit arrangement as claimed in claim 4 is characterized in that shift register is fed.
6. as the circuit arrangement of one of claim 2-5, it is characterized in that first oscillator (OSZ1) approximately has identical frequency with second oscillator (VCO1), the 3rd oscillator (VCO2) and the 4th oscillator (OSZ2) are with another hunting of frequency.
7. as the circuit arrangement of one of above-mentioned claim, it is characterized in that first oscillator (OSZ1) is as voltage-controlled oscillator formation and by frequency modulation(FM).
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19618098A DE19618098C1 (en) | 1996-05-06 | 1996-05-06 | Random bit sequence generation circuit |
| DE19618098.8 | 1996-05-06 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1217834A true CN1217834A (en) | 1999-05-26 |
Family
ID=7793447
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN97194365A Pending CN1217834A (en) | 1996-05-06 | 1997-04-25 | Circuit arrangement for generating random bit sequences |
Country Status (7)
| Country | Link |
|---|---|
| EP (1) | EP0897613A1 (en) |
| JP (1) | JPH11509707A (en) |
| KR (1) | KR20000010804A (en) |
| CN (1) | CN1217834A (en) |
| BR (1) | BR9708977A (en) |
| DE (1) | DE19618098C1 (en) |
| WO (1) | WO1997042706A1 (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2325361B (en) * | 1997-05-16 | 2001-06-27 | Motorola Inc | Random number generator arrangement and method of generation thereof |
| DE19744586A1 (en) * | 1997-10-09 | 1999-04-15 | Guenther Dipl Phys Magens | Coding digital data for distant transmission |
| US6522210B1 (en) * | 2000-02-16 | 2003-02-18 | Honeywell International Inc. | Random pulse generator |
| WO2006054476A1 (en) * | 2004-11-18 | 2006-05-26 | Niigata Tlo Corporation | Random number generating method and device |
| PL237196B1 (en) * | 2017-08-08 | 2021-03-22 | Politechnika Warszawska | Random generator |
| WO2019030667A1 (en) | 2017-08-08 | 2019-02-14 | Politechnika Warszawska | Random number generator |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3713142A (en) * | 1972-01-17 | 1973-01-23 | Signatron | Alarm system |
| DE3020481C2 (en) * | 1980-05-29 | 1988-10-20 | Siemens AG, 1000 Berlin und 8000 München | Settable pseudo-random generator |
| US4644299A (en) * | 1986-02-14 | 1987-02-17 | Hughes Aircraft Company | Multimode noise generator using digital FM |
| FR2621191B3 (en) * | 1987-09-29 | 1989-08-04 | Cit Alcatel | JIGS SIGNAL GENERATOR |
| US5153532A (en) * | 1989-05-24 | 1992-10-06 | Honeywell Inc. | Noise generator using combined outputs of two pseudo-random sequence generators |
| DE4002569C3 (en) * | 1990-01-30 | 1996-04-25 | Sensys Ag | mine |
-
1996
- 1996-05-06 DE DE19618098A patent/DE19618098C1/en not_active Expired - Fee Related
-
1997
- 1997-04-25 JP JP9539414A patent/JPH11509707A/en active Pending
- 1997-04-25 BR BR9708977A patent/BR9708977A/en not_active Application Discontinuation
- 1997-04-25 KR KR1019980708938A patent/KR20000010804A/en not_active Application Discontinuation
- 1997-04-25 CN CN97194365A patent/CN1217834A/en active Pending
- 1997-04-25 EP EP97924868A patent/EP0897613A1/en not_active Withdrawn
- 1997-04-25 WO PCT/DE1997/000831 patent/WO1997042706A1/en not_active Application Discontinuation
Also Published As
| Publication number | Publication date |
|---|---|
| JPH11509707A (en) | 1999-08-24 |
| WO1997042706A1 (en) | 1997-11-13 |
| DE19618098C1 (en) | 1997-06-05 |
| BR9708977A (en) | 1999-08-03 |
| KR20000010804A (en) | 2000-02-25 |
| EP0897613A1 (en) | 1999-02-24 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C01 | Deemed withdrawal of patent application (patent law 1993) | ||
| WD01 | Invention patent application deemed withdrawn after publication |