CN1217834A - Circuit arrangement for generating random bit sequences - Google Patents
Circuit arrangement for generating random bit sequences Download PDFInfo
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- CN1217834A CN1217834A CN97194365A CN97194365A CN1217834A CN 1217834 A CN1217834 A CN 1217834A CN 97194365 A CN97194365 A CN 97194365A CN 97194365 A CN97194365 A CN 97194365A CN 1217834 A CN1217834 A CN 1217834A
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- oscillator
- circuit arrangement
- controlled
- random bit
- voltage
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B29/00—Generation of noise currents and voltages
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/84—Generating pulses having a predetermined statistical distribution of a parameter, e.g. random pulse generators
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
- H04L9/065—Encryption by serially and continuously modifying data stream elements, e.g. stream cipher systems, RC4, SEAL or A5/3
- H04L9/0656—Pseudorandom key sequence combined element-for-element with data sequence, e.g. one-time-pad [OTP] or Vernam's cipher
- H04L9/0662—Pseudorandom key sequence combined element-for-element with data sequence, e.g. one-time-pad [OTP] or Vernam's cipher with particular pseudorandom sequence generator
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- Engineering & Computer Science (AREA)
- Computer Security & Cryptography (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
用于产生随机位序列的电路装置,具有一个第一振荡器(OSZ1)和一个第二振荡器(VCO1),其输出端与准备提供随机位序列的相位检测器(PD)的输入端相连,其中第二振荡器(VCO1)被频率调制。
A circuit arrangement for generating a random bit sequence, having a first oscillator (OSZ1) and a second oscillator (VCO1), the output of which is connected to the input of a phase detector (PD) intended to provide the random bit sequence, Wherein the second oscillator (VCO1) is frequency modulated.
Description
在许多数据处理过程中，尤其是在加密技术中，位序列需要随机分配位序列。这种确定随机位序列的长度能够作为随机数而定。In many data processing procedures, especially in encryption techniques, bit sequences require random assignment of bit sequences. The length of this defined random bit sequence can be determined as a random number.
一般应用所谓的伪随机数，其通过反馈的移位寄存器产生。伪随机数是随机的，并且与较大的数相继的伪随机数发生器不能连接到下一个值。其不含有与所应用的移位寄存器的长度有关的周期性。另外移位寄存器的输出数据与输入数据和移位寄存器的结构有关。In general, so-called pseudo-random numbers are used, which are generated by means of a fed-back shift register. Pseudorandom numbers are random, and successive pseudorandom number generators with larger numbers cannot be connected to the next value. It does not contain a periodicity related to the length of the shift register used. In addition, the output data of the shift register is related to the input data and the structure of the shift register.
到现在为止还不知道数字电路中的有效随机数。Effective random numbers in digital circuits are not known until now.
上述发明的任务在于给出用于产生有效随机位序列的电路装置。The object of the above-mentioned invention is to specify a circuit arrangement for generating an efficient random bit sequence.
此任务通过权利要求1的电路装置解决。本发明有利的改进在从属权利要求中给出。This object is achieved by the circuit arrangement of claim 1 . Advantageous developments of the invention are given in the dependent claims.
在本发明的电路装置中，输出信号的相应相位分析两个振荡器的数字。一个振荡器以近似恒定的频率振荡，而另一个振荡器以该频率调制。量化噪声支配了所满足的频率偏移。所以所存在的随机位序列能够作为随机数应用。In the circuit arrangement according to the invention, the respective phases of the output signals are evaluated digitally of the two oscillators. One oscillator oscillates at an approximately constant frequency, while the other oscillator is modulated at that frequency. Quantization noise dominates the frequency offset that is met. The existing random bit sequence can therefore be used as a random number.
在本发明的改进中以尤其有利的方式通过其他的优选以另一频率振荡的振荡器进行频率调制。其输出信号优选的含有锯齿波。另一振荡器在本发明的另一改进中能够通过附加的振荡器进行频率调制并且此振荡器能够调制。In a development of the invention, the frequency modulation takes place in a particularly advantageous manner by means of a further oscillator, which preferably oscillates at a different frequency. Its output signal preferably contains a sawtooth wave. In a further refinement of the invention, the other oscillator can be frequency-modulated by the additional oscillator and this oscillator can be modulated.
频率调制的振荡器以有利的结构作为电压控制的振荡器实现，以致其能够通过另一振荡器的输出信号进行直接控制。The frequency-modulated oscillator is advantageously implemented as a voltage-controlled oscillator, so that it can be directly controlled via the output signal of another oscillator.
相位的检测能够有利的尤其是以简单的方式通过移位寄存器实现，其数据输入端优选的通过频率调制的振荡器信号并且其时钟输入端通过振荡器信号恒定频率的调制。The detection of the phase can advantageously be realized in a particularly simple manner by means of a shift register, the data input of which is preferably modulated by a frequency-modulated oscillator signal and the clock input of which is modulated by a constant frequency of the oscillator signal.
具有恒定频率的振荡器在本发明的改进中通过频率调制的振荡器替换。In a development of the invention, the oscillator with a constant frequency is replaced by a frequency-modulated oscillator.
在本发明的有利改进中移位寄存器进行反馈。In an advantageous development of the invention, the shift register provides feedback.
下面通过附图借助于实施例详细解释本发明。图为The invention is explained in more detail below by means of an exemplary embodiment with reference to the drawings. The picture shows
图1是本发明的电路装置的原理图，Fig. 1 is the schematic diagram of the circuit device of the present invention,
图2是电压控制的振荡器的原理图。Figure 2 is a schematic diagram of a voltage controlled oscillator.
按照图1相位检测器PD的第一输入端通过第一振荡器OSZ1的第二输出信号输出2加载。相位检测器PD的第二输入端通过第一电压控制振荡器VCO1的第二输出信号输出2加载。According to FIG. 1, the first input of the phase detector PD is loaded via the second output signal output 2 of the first oscillator OSZ1. The second input of the phase detector PD is loaded via the second output signal OUT2 of the first voltage-controlled oscillator VCO1 .
振荡器OSZ1、VCO1的第二输出信号输出2是矩形波。振荡器OSZ1、VCO1提供具有大约锯齿形状的输出信号输出1。The second output signal output 2 of the oscillator OSZ1 , VCO1 is a rectangular wave. Oscillator OSZ1 , VCO1 provides an output signal output 1 with an approximately sawtooth shape.
第一电压控制振荡器VCO1通过第二电压控制的振荡器VCO2控制，此实际通过另一电压控制的振荡器，其没有示出而是通过划线标明，通过具有第一输出信号输出1的自由振荡的第二振荡器OSZ2控制。原则上第一振荡器OSZ1作为电压控制的振荡器构成，其通过一个或者一链的多个振荡器或者电压控制的振荡器以其输出信号输出1控制。这在图1中通过划线的振荡器OSZ标明。The first voltage-controlled oscillator VCO1 is controlled by the second voltage-controlled oscillator VCO2, which is actually controlled by another voltage-controlled oscillator, which is not shown but is marked by a dash, by having the freedom of the first output signal output 1 Oscillation is controlled by the second oscillator OSZ2. In principle, the first oscillator OSZ1 is designed as a voltage-controlled oscillator which is controlled with its output signal OUT1 by one or a chain of several oscillators or voltage-controlled oscillators. This is indicated in FIG. 1 by the dashed oscillator OSZ.
相位检测器PD以有利的方式通过专业人员熟悉的移位寄存器构成。在此以优选的方式第一振荡器1的第二输出信号输出2传输到移位寄存器的数据输入端，而第一电压控制振荡器的第二输出信号输出2传输到移位寄存器的时钟输入端。原则上也是能够的，第一电压控制振荡器VCO1的第二输出信号输出2施加到数据输入端，并且第一振荡器OSZ1的第二输出信号输出2施加到起相位检测器PD作用的移位寄存器的时钟输入端。The phase detector PD is advantageously formed by a shift register familiar to the person skilled in the art. In this case, the second output signal output 2 of the first oscillator 1 is preferably transferred to the data input of the shift register, while the second output signal output 2 of the first voltage-controlled oscillator is transferred to the clock input of the shift register end. In principle it is also possible that the second output signal OUT2 of the first voltage-controlled oscillator VCO1 is applied to the data input and the second output signal OUT2 of the first oscillator OSZ1 is applied to the shifter functioning as phase detector PD. Register clock input.
作为相位检测器PD的移位寄存器在本发明的有利改进中能够反馈的构成。在此移位寄存器的输出信号通过数据输入信号进行逻辑转换并且然后传输到移位寄存器的输入端。另外能够将移位寄存器的中间抽头信号逻辑的转换并且反馈到输入端。In an advantageous development of the invention, the shift register as phase detector PD is capable of a feedback configuration. In this case, the output signal of the shift register is logically converted by the data input signal and then passed to the input of the shift register. In addition, the center tap signal of the shift register can be switched logically and fed back to the input.
图2示出了数字电压控制的振荡器的原理结构图。反相器INV的输出端通过电容C与大地端子相连并且另外与作为史密特触发器构成的比较器ST的输入端相连。比较器ST的输出端输出2提供大约矩形的信号并且反馈到反相器INV的输入端。如果例如反相器INV的输出状态是“1”，电容C被充电。如果电容C上的电压超过了比较器ST的阕值，如此切换：在也构成振荡器输出端的输出端输出2，表现为逻辑“1”。其可以反馈到反相器INV的输入端，以使该状态在输出端变为逻辑“0”。以此重新从电容C放电，以致比较器ST根据已知的时间重新切换。在此存在一个周期性的振荡状态，其频率主要通过电容C的电容量和反相器INV的负载电路中的电阻确定。此电阻能够可控制的构成，例如图1所示的p-和n-MOS晶体管，其分别接在正的电源电压端子和特有的反相器的p-MOS晶体管之间以及反相器的n-MOS晶体管和负的电源电压端子之间。此可控制的反相器INV必需接入有两个互补的控制信号输入1、输入2。Figure 2 shows the schematic structure diagram of the digital voltage controlled oscillator. The output of the inverter INV is connected via a capacitor C to the ground terminal and also to the input of a comparator ST configured as a Schmitt trigger. The output OUT2 of the comparator ST provides an approximately rectangular signal and is fed back to the input of the inverter INV. If eg the output state of the inverter INV is "1", the capacitor C is charged. If the voltage across the capacitor C exceeds the threshold value of the comparator ST, the switching is such that a 2 is output at the output which also forms the output of the oscillator, representing a logical "1". It can be fed back to the input of the inverter INV so that this state becomes a logic "0" at the output. Capacitor C is thus discharged again, so that comparator ST switches again according to a known time. There is a periodic oscillating state here, the frequency of which is determined primarily by the capacitance of capacitor C and the resistance in the load circuit of inverter INV. This resistance can be constructed in a controllable manner, such as the p- and n-MOS transistors shown in Figure 1, which are respectively connected between the positive supply voltage terminal and the p-MOS transistor of the specific inverter and the n-MOS transistor of the inverter. - Between the MOS transistor and the negative supply voltage terminal. The controllable inverter INV must be connected with two complementary control signal inputs 1 and 2 .
电压控制振荡器的基频通过电容C的电容量的大小确定。频率的变化借助于控制信号输入1、输入2通过反相器INV的负载的电阻的变化实现。The fundamental frequency of the voltage controlled oscillator is determined by the capacitance of the capacitor C. The variation of the frequency is effected by means of the variation of the resistance of the load of the control signal input 1 , input 2 through the inverter INV.
另外含有一个输出端，其提供具有大约锯齿波形的第一输出信号输出1，并且与电容C相连。In addition, there is an output terminal, which provides a first output signal output 1 with an approximately sawtooth waveform, and is connected to the capacitor C.
通过本发明的电路装置能够产生有效的随机位序列，其作为随机数能够应用在加密技术的数据处理过程中。The circuit arrangement according to the invention can generate an effective random bit sequence, which can be used as a random number in the data processing process of encryption technology.
Claims (7)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19618098.8 | 1996-05-06 | ||
| DE19618098A DE19618098C1 (en) | 1996-05-06 | 1996-05-06 | Random bit sequence generation circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1217834A true CN1217834A (en) | 1999-05-26 |
Family
ID=7793447
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN97194365A Pending CN1217834A (en) | 1996-05-06 | 1997-04-25 | Circuit arrangement for generating random bit sequences |
Country Status (7)
| Country | Link |
|---|---|
| EP (1) | EP0897613A1 (en) |
| JP (1) | JPH11509707A (en) |
| KR (1) | KR20000010804A (en) |
| CN (1) | CN1217834A (en) |
| BR (1) | BR9708977A (en) |
| DE (1) | DE19618098C1 (en) |
| WO (1) | WO1997042706A1 (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2325361B (en) * | 1997-05-16 | 2001-06-27 | Motorola Inc | Random number generator arrangement and method of generation thereof |
| DE19744586A1 (en) * | 1997-10-09 | 1999-04-15 | Guenther Dipl Phys Magens | Coding digital data for distant transmission |
| US6522210B1 (en) * | 2000-02-16 | 2003-02-18 | Honeywell International Inc. | Random pulse generator |
| US20070255777A1 (en) * | 2004-11-18 | 2007-11-01 | Niigata Tlo Corporation | Method for Generating Random Number and Random Number Generator |
| PL237196B1 (en) * | 2017-08-08 | 2021-03-22 | Politechnika Warszawska | Random generator |
| WO2019030667A1 (en) | 2017-08-08 | 2019-02-14 | Politechnika Warszawska | Random number generator |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3713142A (en) * | 1972-01-17 | 1973-01-23 | Signatron | Alarm system |
| DE3020481C2 (en) * | 1980-05-29 | 1988-10-20 | Siemens AG, 1000 Berlin und 8000 München | Settable pseudo-random generator |
| US4644299A (en) * | 1986-02-14 | 1987-02-17 | Hughes Aircraft Company | Multimode noise generator using digital FM |
| FR2621191B3 (en) * | 1987-09-29 | 1989-08-04 | Cit Alcatel | JIGS SIGNAL GENERATOR |
| US5153532A (en) * | 1989-05-24 | 1992-10-06 | Honeywell Inc. | Noise generator using combined outputs of two pseudo-random sequence generators |
| DE4002569C3 (en) * | 1990-01-30 | 1996-04-25 | Sensys Ag | mine |
-
1996
- 1996-05-06 DE DE19618098A patent/DE19618098C1/en not_active Expired - Fee Related
-
1997
- 1997-04-25 EP EP97924868A patent/EP0897613A1/en not_active Withdrawn
- 1997-04-25 KR KR1019980708938A patent/KR20000010804A/en not_active Withdrawn
- 1997-04-25 CN CN97194365A patent/CN1217834A/en active Pending
- 1997-04-25 WO PCT/DE1997/000831 patent/WO1997042706A1/en not_active Application Discontinuation
- 1997-04-25 JP JP9539414A patent/JPH11509707A/en active Pending
- 1997-04-25 BR BR9708977A patent/BR9708977A/en not_active Application Discontinuation
Also Published As
| Publication number | Publication date |
|---|---|
| BR9708977A (en) | 1999-08-03 |
| JPH11509707A (en) | 1999-08-24 |
| DE19618098C1 (en) | 1997-06-05 |
| KR20000010804A (en) | 2000-02-25 |
| EP0897613A1 (en) | 1999-02-24 |
| WO1997042706A1 (en) | 1997-11-13 |
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