KR960000639Y1 - Clock frequency changing apparatus - Google Patents

Abstract

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Description

Clock frequency switching circuit

Figure 1 (a) is a clock frequency generation circuit diagram using a conventional inverter, (b) is a clock frequency generation circuit diagram using a conventional NAND gike.

2 is a clock frequency switching circuit of the present invention.

FIG. 3 is a diagram of each sub waveform in FIG. 2; FIG.

* Explanation of symbols for main parts of the drawings

10: high frequency frequency oscillator 30: microcomputer

X21-X22: Crystal Oscillator C21-C24: Condenser

20: low frequency oscillator 24: NAND gate

R21-R22: Resistance

The present invention relates to a clock frequency switching circuit, and in particular, having a high frequency oscillator and a low frequency oscillator, the high speed frequency oscillator is selected and used during normal operation, and the low frequency oscillator is selected when the operation speed is slow The present invention relates to a clock frequency switching circuit capable of reducing power consumption.

FIG. 1A is a clock frequency issuing circuit diagram using a conventional inverter. As shown in FIG. 1A, an inverter NOT1, a resistor Rl, a capacitor C1, and a crystal oscillator X1 are used to oscillate a system clock frequency. A clock frequency oscillator 1 and a microcomputer 2 for controlling the system at a speed proportional to the output frequency of the clock frequency oscillator 1.

Referring to the operation of the conventional circuit configured as described above is as follows.

When power is applied in the initial state, a low signal is applied to the input terminal of the inverter (NOI, 1), and a high signal is output to the output terminal.

At this point, a voltage is charged to the capacitor C1 through the resistor Rl. When the charge voltage of the capacitor CI becomes higher than the threshold voltage of the inverter NOTl, a high signal is applied to the input terminal of the inverter NOTl. A low signal is output to the output terminal.

At this time, the layer charge voltage of the capacitor Cl is discharged to the ground through the resistor Rl. When the voltage of the capacitor C1 becomes less than the threshold voltage of the inverter NOTl, a low signal is applied to the input terminal of the inverter NOTl. Is applied, and a high signal is output to the output terminal.

The oscillation frequency generated by the crystal oscillator X1 is output through the above process.

However, such a conventional circuit outputs only a single frequency, and therefore, there is a problem in that the power usage is not efficient by always outputting the same frequency even in a work where the execution speed may be slow.

As another example, in a specific circuit, as shown in FIG. 1B, a NAND gate NANDl is used instead of an inverter to configure a clock frequency oscillator. Next, during standby, a low signal is applied to one input terminal of the NAND gate to prevent the oscillation frequency from being output.

In this case, however, the oscillation frequency is not applied to the microcomputer 2, so that the operation of the microcomputer 2 is completely stopped.

Therefore, the object of the present invention is to reduce the power consumption by selecting and using a high-speed frequency oscillator in normal operation to solve this conventional problem, and by using a low-frequency frequency oscillator in the case of a slow operation. The clock frequency switching circuit is conceived.

Means for achieving the object of the present invention include a high frequency oscillator for generating a high speed system clock frequency in accordance with a control signal, a low frequency oscillator for generating a low system clock frequency in accordance with a control signal, according to the control signal A NAND gate that receives the outputs of the alternating high speed oscillator and the low frequency oscillator and outputs a high speed or low speed system clock frequency, and a control signal to alternately oscillate the high frequency oscillator and the low frequency oscillator The present invention will be described in detail with reference to the accompanying drawings, wherein the microcomputer is configured to control the system at a speed proportional to the output frequency of the NAND gate.

FIG. 2 is a circuit diagram of the present invention, and the control signal of the microcomputer 30 includes NAND gates NAND21-NAND22, resistors R21, large capacitors C21-C22, and crystal oscillators X21 as shown in FIG. And a high frequency frequency oscillator 10 for generating a high frequency of 1 NlHz, a NAND gate NAND23, a resistor R22, a capacitor C23-C24, and a crystal oscillator X22. The output of the low frequency oscillator 20 and the low frequency oscillator 20, which oscillates alternately according to the control signal of the microcomputer 30, and the low frequency oscillator 20 for generating a low frequency of 32 KHz according to the signal. A NAND gate NAND24 that receives an input and outputs a clock frequency of a high speed or a low speed, and outputs a control signal to the high frequency oscillator 10 and the low frequency oscillator 20 to control the oscillation and the NAND gate NAND24. Output frequency The microcomputer 30 controls the system at a speed proportional to the number.

When described in detail with reference to Figure 3 with respect to the operation and effects of the present invention configured as described above.

The NAND gate is a condition in which a high signal must be input to one of the two input terminals to invert and output the signal input to the other. That is, the oscillated frequency can be output by the crystal oscillation only when the high signal is input to either input terminal.

Therefore, as shown in Fig. 3A, when the low signal is output from the terminal OUT of the microcomputer 30, the low signal is inputted to two input terminals of the NAND gate NAND21, and the NAND gate is output. NAND21 outputs a high signal, and this high signal is input to one input terminal of the NAND gate NAND22, and the NAND gate NAND22 is shown in FIG. 3 (b) oscillated by the crystal oscillator X21. As shown, outputs a frequency of AIHz.

On the other hand, the low signal output from the terminal (O =,) of the microcomputer 30 is input to one input terminal of the NAND gate NAND23, and the NAND gate NA＼D2 'is shown in FIG. As described above, the high signal is always output. Accordingly, the low frequency oscillator 20 cannot output the frequency of 32 KNlz oscillated by the crystal oscillator X.

At this time, the high signal output from the fraud NAND gate is input to one input terminal of the NAND gate and the NAND gate 24 is input to the other input terminal. A high frequency of 1NlHz is output as shown in FIG.

On the contrary, when a high signal is output from the single yarn OUT of the microcomputer 30 as shown in FIG. 3A, the following signal is inputted to two input terminals of the NAND gate NAND21, and the NAND gate NA＼. D21 outputs a low signal, which is input to one input terminal of the NAND gate NAND22 so that the NAND gate 드 A＼D2 (t) is always high as shown in (b) of FIG. As a result, the frequency of lNIHz oscillated by the crystal oscillator X21 cannot be output.

On the other hand, the hi signal output from the single yarn OU ^ 1 of the microcomputer 30 is input to one input terminal of the NAND gate AND23, and the NAND gate N4AND23 is oscillated by the crystal oscillator X22. A frequency of 32 KHz is output as shown in FIG.

At this time, the high signal output from the NAND gate NA＼D22 is input to one input terminal of the NAND gate NAND24, and the NAND gate NAND24 is input to the other input terminal, as shown in FIG. Outputs a low frequency of 32 NIHz as shown.

In this way, the control signal output from the terminal OUl of the microcomputer 30 may be generated by switching the high speed clock frequency and the low speed clock frequency.

As described in detail above, the present invention has an effect of reducing the current consumption by switching between the high speed oscillation unit and the low speed oscillation unit as necessary.

Claims (1)

A high speed frequency oscillator 10 generating a high speed system clock frequency in accordance with a control signal, a low frequency frequency oscillator 20 generating a low speed system clock frequency in accordance with a control signal, and the high speed alternately oscillating according to a control signal A NAND gate NAND24 that outputs a high frequency or low speed system clock frequency by inputting the output of the frequency oscillator 10 and the low frequency oscillator 20, and the high frequency oscillator 10 and the low frequency oscillator 20 And a microcomputer (30) for controlling the system at a speed proportional to the output frequency of the NAND gate and outputting a control signal to alternately oscillate.