CN1217398C - Control chip for daily monitoring for rapid theremal annealing process - Google Patents

Control chip for daily monitoring for rapid theremal annealing process Download PDF

Info

Publication number
CN1217398C
CN1217398C CN 02137394 CN02137394A CN1217398C CN 1217398 C CN1217398 C CN 1217398C CN 02137394 CN02137394 CN 02137394 CN 02137394 A CN02137394 A CN 02137394A CN 1217398 C CN1217398 C CN 1217398C
Authority
CN
China
Prior art keywords
layer
monitoring
day
rapid thermal
polycrystalline silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
CN 02137394
Other languages
Chinese (zh)
Other versions
CN1489194A (en
Inventor
吴金刚
刘靓一
罗学辉
李修远
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Original Assignee
Semiconductor Manufacturing International Shanghai Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Manufacturing International Shanghai Corp filed Critical Semiconductor Manufacturing International Shanghai Corp
Priority to CN 02137394 priority Critical patent/CN1217398C/en
Publication of CN1489194A publication Critical patent/CN1489194A/en
Application granted granted Critical
Publication of CN1217398C publication Critical patent/CN1217398C/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Landscapes

  • Semiconductor Memories (AREA)

Abstract

The present invention provides a control chip for daily monitoring for a rapid thermal annealing technique. The present invention comprises a silicon base, a silica white layer and a polycrystalline silicon layer without a fixed shape, wherein the silica white layer is formed on the surface of the silicon base, the polycrystalline silicon layer without the fixed shape is formed on the surface of the silica white layer, and the inside is adulterated with an arsenic ion.

Description

The control sheet of monitoring every day of rapid thermal anneal process
Technical field
The present invention is particularly to a kind of control sheet material of monitoring every day of rapid thermal anneal process relevant for a kind of method for supervising every day of rapid thermal anneal process, and it is recyclable to reduce control sheet cost.
Background technology
Be applied to rapid hot technics (the rapid thermal process of many semiconductor technologies, RTP), include rapid thermal oxidation (rapid thermal oxidation, RTO), rapid heat chemical vapour deposition (thermal CVD, RTCVD), rapid thermal annealing (rapid thermal annealing, several technologies such as RTA), wherein RTO is mainly used in the growth thin dielectric layer, and RTCVD is mainly used in the deposition of handling amorphous silicon, multi-crystal silicification tungsten and silicon dioxide.Be mainly used in hot-fluid and the hot-fluid again of reaction, the BPSG of the growth of tempering after ion is implanted, lock oxide layer and tempered metal silicide as for RTA, can make the lattice rearrangement and eliminate stress concentrated, because efficient and the quality of RTA are higher, have that annealing time is short, heat budget is less, oxide layer piles up advantages such as error is less, therefore implant in the cycle of annealing at present ion, RTA has replaced traditional boiler tube annealing way.
Generally speaking, in the disk sheet that silicon crystal bar cut out, concentrate on one section of the centre of silicon wafer rod, the better person of quality is called the production disk, more senior person is called disk of heap of stone, and as for the disk that is cut out by head, tail two ends, the ratio that flaw occurs is higher, be used as nonproductive purposes mostly, be called the test disk.Before the semiconductor wafer in-plant equipment is produced, all need to test the stable process conditions that disk comes measurement equipment, for example: furnace tube temperature, metal level, chemical concentration, deposit thickness, the test disk after the measurement can be scrapped usually.
For ion is implanted annealing device, before carrying out RTA technology every day, must measure temperature and thin layer resistance (sheet resistance, Rs) etc. parameter is with as the monitoring foundation, and every day, method for supervising was to adopt N type disk (for example: the silicon wafer that is doped with the boron ion) as a control sheet (monitor wafer), to the control sheet finish RTA technology with and after relevant monitoring parameter measures, then this control sector-meeting is to scrap processing.Because the use amount of control sheet is big and can't recycle, its spent cost of manufacture is quite big, needs a kind of returnable control sheet of exploitation at present badly.
Summary of the invention
Main purpose of the present invention is to propose a kind of control sheet of monitoring every day of rapid thermal anneal process, includes a silicon base; One silica layer is formed on the silicon base surface; And an amorphous polycrystalline silicon layer, be formed on this silicon oxide layer surface, and inside is doped with an arsenic ion.After the RTA monitoring measurement of finishing the control sheet, silicon oxide layer and amorphous polycrystalline silicon layer can be removed, with recycling control sheet.
Another main purpose of the present invention is to propose a kind of method of monitoring every day of rapid thermal anneal process, includes the following step: provide a silicon base; On the silicon base surface, form one silica layer; On the silicon oxide layer surface, form an amorphous polycrystalline silicon layer; Carry out implanting ions technology, with the arsenic ion that in the amorphous polycrystalline silicon layer, mixes; And carry out rapid thermal anneal process, with the temperature of measurement amorphous polycrystalline silicon layer and the relation of resistance value.After finishing the RTA monitoring measurement, silicon oxide layer and amorphous polycrystalline silicon layer can be removed, with the recycling silicon base.
Another feature of the present invention is, provides silicon oxide layer in amorphous polycrystalline silicon layer bottom, can keep out ions diffusion to silicon base.
Of the present inventionly one be characterised in that again, after finishing RTA monitoring measurement every day, amorphous polycrystalline silicon layer and silicon oxide layer can be removed, then can reclaim and use the control sheet, and then reach the purpose that reduces control sheet material cost.
Description of drawings
Figure 1A to 1D has shown that the present invention is used in the control sheet profile of RTA monitoring program every day.
Fig. 2 A shows the relation of the thickness of temperature (T), thin layer resistance (Rs) and the amorphous polycrystalline silicon layer of controlling sheet.
The relation of the thickness of the temperature (T) of Fig. 2 B demonstration control sheet, the uniformity of Rs and amorphous polycrystalline silicon layer.
Embodiment
For above-mentioned and other purposes of the present invention, feature and advantage can be become apparent, cited below particularlyly go out preferred embodiment, and conjunction with figs., be described in detail below:
See also Figure 1A to 1D, it shows that the present invention is used in the control sheet profile of RTA monitoring program every day.At first, shown in Figure 1A, provide one to be used in the control sheet 10 that RTA monitors every day, it includes a silicon base 12, an one silica layer 14 and an amorphous polysilicon (amorphous polysilicon) layer 16.Wherein, the making of silicon oxide layer 14 can be adopted thermal oxidation method or chemical vapor deposition (CVD) technology, and its THICKNESS CONTROL is 1000 ~ 2000 .The making of amorphous polycrystalline silicon layer 16 can be adopted low-pressure chemical vapor deposition (LPCVD) technology, by silicomethane (SiH 4) mode through adding thermal dissociation deposits, and can exist with the kenel of noncrystalline (amorphous) being lower than the siliceous deposits that (being about 530 ℃) obtained below 575 ℃ the heating-up temperature, its THICKNESS CONTROL is 1900 ~ 2100 .
Then, shown in Figure 1B, amorphous polycrystalline silicon layer 16 is carried out the doping process 18 of arsenic (As) ion, it is that 30KeV, ion doping concentration are 8E15 ion/cm that its ion is implanted energy 2Then, shown in Fig. 1 C, control sheet 10 is carried out RTA technology 20, so that carry out follow-up monitoring measurement.At last, shown in Fig. 1 D, the control sheet 10 of finishing monitoring measurement can carry out reclaimer, after the amorphous polycrystalline silicon layer 16 of the silicon oxide layer 14 on surface and dopant ion is removed, just recyclable re-using, to reduce the material cost of control sheet 10.
Fig. 2 A shows the temperature (T), thin layer resistance of control sheet, and (sheet resistance is Rs) with the relation of the thickness of amorphous polycrystalline silicon layer.The relation of the thickness of the temperature (T) of Fig. 2 B demonstration control sheet, the uniformity of Rs and amorphous polycrystalline silicon layer.By experimental data as can be known; along with temperature increases; the resistance that is measured can be certain proportion and descend; and no matter the thickness of amorphous polycrystalline silicon layer is 1900 , 2000 or 2100 ; when temperature rose to 950 ℃ process by 825 ℃ in, resistance was roughly the same by the decline ratio that 500ohms/sq reduces to 200ohms/sq.In addition, the uniformity of the Rs of control sheet inside is about 0.8 ~ 1.1%, and the uniformity of the Rs between control sheet and the control sheet is about 0.82%
Compared to known technology, the present invention provides the amorphous polycrystalline silicon layer 16 of arsenic doped ion to carry out RTA monitoring measurement every day on the surface of control sheet 10, and the silicon oxide layer 14 of amorphous polycrystalline silicon layer 16 bottoms is enough kept out ions diffusion to silicon base 12, therefore after finishing RTA monitoring measurement every day, amorphous polycrystalline silicon layer 16 and silicon oxide layer 14 can be removed, then can reclaim and use control sheet 10, and then reach the purpose that reduces control sheet material cost.
Though the present invention discloses as above with a preferred embodiment; right its is not in order to limit the present invention; anyly be familiar with present technique field person; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking the accompanying Claim book scope person of defining.

Claims (10)

1. the control sheet of the every day of rapid thermal anneal process monitoring includes:
One silicon base;
One silica layer is formed on this silicon base surface; And
One amorphous polycrystalline silicon layer be formed on this silicon oxide layer surface, and inside is doped with arsenic ion.
2. the control sheet of the monitoring every day of rapid thermal anneal process as claimed in claim 1 is characterized in that the thickness of this silicon oxide layer is 1000 ~ 2000 .
3. the control sheet of the monitoring every day of rapid thermal anneal process as claimed in claim 1 is characterized in that the thickness of this amorphous polycrystalline silicon layer is 1900 ~ 2100 .
4. the control sheet of the monitoring every day of rapid thermal anneal process as claimed in claim 1 is characterized in that, after the monitoring measurement of finishing this control sheet, this silicon oxide layer and this amorphous polycrystalline silicon layer can be removed, should the control sheet with recycling.
5. the method for the every day of rapid thermal anneal process monitoring includes the following step:
One silicon base is provided;
On this silicon base surface, form one silica layer;
On this silicon oxide layer surface, form an amorphous polycrystalline silicon layer;
Carry out implanting ions technology, with arsenic doped ion in this amorphous polycrystalline silicon layer; And
Carry out rapid thermal anneal process, with the temperature that measures this amorphous polycrystalline silicon layer and the relation of resistance value.
6. the method for the monitoring every day of rapid thermal anneal process as claimed in claim 5 is characterized in that the making of this silicon oxide layer can be adopted thermal oxidation method or chemical vapor deposition method.
7. the method for the monitoring every day of rapid thermal anneal process as claimed in claim 5 is characterized in that the thickness of this silicon oxide layer is 1000 ~ 2000 .
8. the method for the monitoring every day of rapid thermal anneal process as claimed in claim 5 is characterized in that the making of this amorphous polycrystalline silicon layer can be adopted low-pressure chemical vapor deposition process.
9. the method for the monitoring every day of rapid thermal anneal process as claimed in claim 5 is characterized in that the thickness of this amorphous polycrystalline silicon layer is 1900 ~ 2100 .
10. the method for the every day of rapid thermal anneal process as claimed in claim 5 monitoring, wherein after the relation of temperature that measures this amorphous polycrystalline silicon layer and resistance value, this silicon oxide layer and this amorphous polycrystalline silicon layer can be removed, with this silicon base of recycling.
CN 02137394 2002-10-11 2002-10-11 Control chip for daily monitoring for rapid theremal annealing process Expired - Lifetime CN1217398C (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN 02137394 CN1217398C (en) 2002-10-11 2002-10-11 Control chip for daily monitoring for rapid theremal annealing process

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN 02137394 CN1217398C (en) 2002-10-11 2002-10-11 Control chip for daily monitoring for rapid theremal annealing process

Publications (2)

Publication Number Publication Date
CN1489194A CN1489194A (en) 2004-04-14
CN1217398C true CN1217398C (en) 2005-08-31

Family

ID=34147001

Family Applications (1)

Application Number Title Priority Date Filing Date
CN 02137394 Expired - Lifetime CN1217398C (en) 2002-10-11 2002-10-11 Control chip for daily monitoring for rapid theremal annealing process

Country Status (1)

Country Link
CN (1) CN1217398C (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101312139B (en) * 2007-05-22 2011-04-20 中芯国际集成电路制造(上海)有限公司 Polycrystalline silicon film resistance value test method
CN102623366B (en) * 2011-01-27 2014-10-29 无锡华润上华半导体有限公司 Method for monitoring annealing process temperature
CN104078376A (en) * 2014-08-04 2014-10-01 上海华力微电子有限公司 Control wafer for furnace tube high-temperature annealing process, manufacturing method and monitoring method
CN104377147B (en) * 2014-11-27 2017-11-14 株洲南车时代电气股份有限公司 A kind of recycling method of ion implanting monitoring piece
CN106783545A (en) * 2016-12-26 2017-05-31 南京国盛电子有限公司 A kind of adjusting method of flat board epitaxial furnace thermal field
CN115692236A (en) * 2022-12-16 2023-02-03 广州粤芯半导体技术有限公司 Method for detecting RTA temperature in silicade process

Also Published As

Publication number Publication date
CN1489194A (en) 2004-04-14

Similar Documents

Publication Publication Date Title
CN1052115C (en) Semiconductor device and method for manufacturing the same
US6068928A (en) Method for producing a polycrystalline silicon structure and polycrystalline silicon layer to be produced by the method
CN1158696C (en) Ideal oxygen precipitating silicon wafers and oxygen out-diffusion-less process therefor
CN1217398C (en) Control chip for daily monitoring for rapid theremal annealing process
US5527718A (en) Process for removing impurities from polycide electrode and insulating film using heat
KR100297628B1 (en) Method for manufacturing semiconductor devices
US5081066A (en) Method for forming a silicide film used in a semiconductor chip
WO2001091177A2 (en) Method and apparatus for controlling deposition parameters based on polysilicon grain size feedback
TW465061B (en) Method for avoiding protrusion on the gate side wall of metal silicide layer
JP3445187B2 (en) Semiconductor device defect compensation method
CN1457086A (en) Base electrode producing method
CN101364538B (en) Gate layer forming method
CN102623366B (en) Method for monitoring annealing process temperature
CN101445958A (en) Silicon crystallization method
TWI286794B (en) Monitor wafer for monitoring daily monitoring of rapid thermal annealing process and method thereof
Byun et al. Characterization of the Dopant Effect on Dichlorosilane‐Based Tungsten Silicide Deposition
CN101685766B (en) Method for increasing use ratio of heat treatment reaction chamber
CN1964019A (en) A method to fabricate high resistance value polysilicon resistance in high voltage IC
CN1271695C (en) Manufacture of wafers monitored by thermo-probe
TW374801B (en) Method of interface flattening of polycide/polysilicon/Wsix
EP4174209A1 (en) Method of forming a doped polysilicon layer
CN1219316C (en) Manufacture of self aligned metal silicon compound with improved electric characteristics on contact surface
CN108987505A (en) A kind of solar battery and preparation method thereof
Moinpour et al. Composition and Structure of As-deposited and Oxidized DCS-Based CVD WSi x Films
KR19990027357A (en) Manufacturing method of semiconductor device

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
ASS Succession or assignment of patent right

Owner name: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING

Effective date: 20111129

C41 Transfer of patent application or patent right or utility model
TR01 Transfer of patent right

Effective date of registration: 20111129

Address after: 201203 No. 18 Zhangjiang Road, Shanghai

Co-patentee after: Semiconductor Manufacturing International (Beijing) Corp.

Patentee after: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) Corp.

Address before: 201203 No. 18 Zhangjiang Road, Shanghai

Patentee before: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) Corp.

CX01 Expiry of patent term

Granted publication date: 20050831

CX01 Expiry of patent term