CN1964019A - A method to fabricate high resistance value polysilicon resistance in high voltage IC - Google Patents
A method to fabricate high resistance value polysilicon resistance in high voltage IC Download PDFInfo
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- CN1964019A CN1964019A CN 200510110230 CN200510110230A CN1964019A CN 1964019 A CN1964019 A CN 1964019A CN 200510110230 CN200510110230 CN 200510110230 CN 200510110230 A CN200510110230 A CN 200510110230A CN 1964019 A CN1964019 A CN 1964019A
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- resistance
- polysilicon
- temperatures
- annealing
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- 238000000034 method Methods 0.000 title claims abstract description 22
- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims description 34
- 229920005591 polysilicon Polymers 0.000 title claims description 31
- 230000008569 process Effects 0.000 claims abstract description 11
- 239000000463 material Substances 0.000 claims abstract description 6
- 229910052785 arsenic Inorganic materials 0.000 claims abstract description 4
- 238000000137 annealing Methods 0.000 claims description 12
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 8
- 238000005259 measurement Methods 0.000 claims description 8
- 238000002347 injection Methods 0.000 claims description 6
- 239000007924 injection Substances 0.000 claims description 6
- UGACIEPFGXRWCH-UHFFFAOYSA-N [Si].[Ti] Chemical compound [Si].[Ti] UGACIEPFGXRWCH-UHFFFAOYSA-N 0.000 claims description 4
- 229910052757 nitrogen Inorganic materials 0.000 claims description 4
- 238000007669 thermal treatment Methods 0.000 claims description 4
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 238000002156 mixing Methods 0.000 claims description 3
- 238000002513 implantation Methods 0.000 claims description 2
- -1 LDD nitride Chemical class 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 238000011065 in-situ storage Methods 0.000 abstract description 2
- 238000005530 etching Methods 0.000 abstract 1
- 238000004062 sedimentation Methods 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 238000009826 distribution Methods 0.000 description 4
- 229910021332 silicide Inorganic materials 0.000 description 3
- 238000009966 trimming Methods 0.000 description 3
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910000073 phosphorus hydride Inorganic materials 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
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Abstract
The disclosed manufacture method for high-resistance multicrystal sensistor in high-voltage IC comprises: using the non-silicatized in-situ doped-arsenic multicrystal grid material as the resistance element; etching the high-resistance area and the grid; finally, taking the thermal process after material sedimentation. This invention can obtain 1000omega block resistance element.
Description
Technical field
The present invention relates to a kind of process for making of semiconductor integrated circuit, particularly relate to a kind of in the method for in high voltage integrated circuit, making the high value polysilicon resistance.
Background technology
Usually to use the high resistance measurement element in the high voltage integrated circuit product, and it directly is integrated in the inside of integrated circuit, to reduce the physical dimension of chip.Usually use doping or plain polysilicon as the high resistance element material, be called high resistance polysilicon (HR Poly).For obtaining target resistance values, generally all need the special injection mask plate of one deck, adopt photoresist to block other zone, inject and resistance region is carried out ion, and then adjust its resistance.So no doubt can obtain final resistance, but because need the special injection mask plate of this layer,, not only increase cost of manufacture but also lost time, influence efficient so can increase corresponding coating, development, series of process step such as inject, remove photoresist.
Summary of the invention
Technical problem to be solved by this invention provides the method for making the high value polysilicon resistance in a kind of high voltage integrated circuit, is saving the 1000 ohms/square resistance that the acquisition resistance is stable under the situation of injecting mask plate, inner evenness is good.
For solving the problems of the technologies described above, the method of making the high value polysilicon resistance in the high voltage integrated circuit of the present invention adopts following technical scheme, directly utilize the polysilicon gate material double as resistive element of mixing arsenic without the original position of silication, when the etch polysilicon grid, in the lump the high resistance measurement zone is carved, carry out the thermal process after the polysilicon deposit at last.
Because the present invention directly utilizes the polysilicon gate material double as resistive element (as shown in Figure 1) of mixing arsenic without the original position of silication, when the etch polysilicon grid, in the lump the high resistance measurement zone is carved, through follow-up a series of thermal processs, do not needing the injection of resistance trimming value, thereby can save one deck mask plate, under the situation of reduction expense, it is stable to obtain resistance, the high resistance measurement of 1000 ohms/square that inner evenness is good.
Requirement to high resistance polysilicon is, at first the resistance size whether in target range, secondly be in its silicon chip face, between silicon chip so LOT (batch) between variable quantity, also be its uniformity how.After adopting method of the present invention, obtained more satisfactory result, shown:
| Sample | Mean value (ohms/square) | Standard deviation | Maximum | Minimum value | Variable quantity | Uniformity (variable quantity/mean value) |
| First batch of the present invention | 1073.75 | 9.61 | 1091.70 | 1041.19 | 50.52 | 4 85％ |
| Second batch of the present invention | 1050.29 | 8.87 | 1076.81 | 1021.91 | 54.90 | 5.37％ |
| Sample for reference one | 1132.60 | 10 90 | N/A | N/A | 48.00 | 4.20％ |
| Sample for reference two | 962.50 | 10.40 | N/A | N/A | 43.50 | 4.50％ |
Table 1: the high resistance polysilicon performance that different schemes is made relatively
1, resistance is within standard
As shown in table 1, two batches the resistance mean value that adopts the present invention to make is respectively 1073 and 1050 ohms/square, and the requirement of regulation is 1000 ± 150 ohms/square, so the error of resistance is in standard.As reference, made two batches simultaneously and adopted ion to inject the high resistance polysilicon sample that obtains, during its result as above shows shown in the sample for reference one, two by special injection mask.Sample for reference shown in the table is 7 point measurement results in the face.
2, good uniformity
As shown in table 1, to compare with the resistance that injects acquisition by special resistance trimming value, the resistance that adopts the present invention to make is all suitable with the former aspect variable quantity and uniformity.Fig. 2 distributes with the silicon chip face internal resistance value that Figure 3 shows that two batches of resistance that adopt the present invention's making.As seen from the figure, in face, under the situation of full point measurement, still kept good homogeneous.
Description of drawings
Below in conjunction with accompanying drawing and embodiment the present invention is done explanation in further detail:
Fig. 1 is the high resistance polysilicon resistance schematic diagram that adopts the present invention to make;
Fig. 2 is first batch of silicon chip face internal resistance value distribution (full point) of adopting the present invention to make;
Fig. 3 is second batch of silicon chip face internal resistance value distribution (full point) of adopting the present invention to make.
Embodiment
The present invention makes the method for high value polysilicon resistance in high voltage integrated circuit main technical point is: the depositing technics of original position arsenic-doped polysilicon, and doping content and deposition process parameters influence the resistance of resistance itself; Thermal process after the polysilicon deposit, subsequent thermal process mainly influence the distribution of impurity in polysilicon.
Described doped polycrystalline silicon (DOPOS) deposit adopts low pressure plasma to strengthen chemical vapour deposition (CVD) (LPCVD).
Concrete technological parameter is as follows: S
iH
4The flow 1600cm of (silane)
3/ minute, PH
3The flow 12.8cm of (phosphine)
3/ minute, 34.5 minutes time, 530 ℃ of furnace temperature, pressure 0.0997Kpa.
Subsequent thermal process after the described DOPOS deposit influences the distribution of impurity in polysilicon as previously mentioned, and then influences resistance, and in the present invention, follow-up elevated temperature heat process is as follows:
1, carries out the polysilicon gate high annealing, 920 ℃ of annealing temperatures, 10 seconds time;
2, Poly Re-oxidation (grid reoxidize), 850 ℃ of temperature;
3, LDD (lightly doped drain) annealing, 950 ℃ of annealing temperatures, 20 seconds time;
4, LDD oxide side wall growth, 690 ℃ of growth temperatures, side wall thicknesses 100 ;
5, LDD nitride side wall growth, 760 ℃ of growth temperatures, side wall thicknesses 1500 ;
6, SD (source leakage) nitrogen injection is handled, 700 ℃ of treatment temperatures, 20 minutes time;
7, SD implantation annealing, 1050 ℃ of annealing temperatures, 30 seconds time;
8, Ti-silicide RTP1 (titanium silicon rapid thermal treatment 1), 710 ℃ of temperature, 30 seconds time;
9, Ti-silicide RTP2 (titanium silicon rapid thermal treatment 2), 850 ℃ of temperature, 30 seconds time;
10, PMD (deielectric-coating before the metal) nitrogen treatment, 690 ℃ of treatment temperatures, 30 seconds time.
The high value polysilicon resistance schematic diagram of Fig. 1 for adopting the present invention to make, promptly directly adopt without silication (being that resistance region has silicide barrier layer to cover) in-situ doped polysilicon (DOPOS) and under the situation that does not need special resistance trimming value to inject, obtained 1000 ohms/square high resistance measurements through a series of subsequent thermal processes.As circuit element, the resistance two ends need to connect interconnecting metal layer by contact hole and draw.
Claims (3)
1, makes the method for high value polysilicon resistance in a kind of high voltage integrated circuit, it is characterized in that: directly utilize the polysilicon gate material double as resistive element of mixing arsenic without the original position of silication, when the etch polysilicon grid, in the lump the high resistance measurement zone is carved, carry out the thermal process after the polysilicon deposit at last.
2, make the method for high value polysilicon resistance in the high voltage integrated circuit according to claim 1, it is characterized in that: the concrete technological parameter of described doped polycrystalline silicon deposit is as follows: S
iH
4Flow 1600cm
3/ minute, PH
3Flow 12.8cm
3/ minute, 34.5 minutes time, 530 ℃ of furnace temperature, pressure 0.0997Kpa.
3, make the method for high value polysilicon resistance in the high voltage integrated circuit according to claim 1 and 2, it is characterized in that: the subsequent thermal process behind the described doped polycrystalline silicon deposit is as follows:
(1) carries out the polysilicon gate high annealing, 920 ℃ of annealing temperatures, 10 seconds time;
(2) grid reoxidize, 850 ℃ of temperature;
(3) LDD annealing, 950 ℃ of annealing temperatures, 20 seconds time;
(4) LDD oxide side wall growth, 690 ℃ of growth temperatures, side wall thicknesses 100 ;
(5) LDD nitride side wall growth, 760 ℃ of growth temperatures, side wall thicknesses 1500 ;
(6) the SD nitrogen injection is handled, 700 ℃ of treatment temperatures, 20 minutes time;
(7) SD implantation annealing, 1050 ℃ of annealing temperatures, 30 seconds time;
(8) titanium silicon rapid thermal treatment 1,710 ℃ of temperature, 30 seconds time;
(9) titanium silicon rapid thermal treatment 2,850 ℃ of temperature, 30 seconds time;
(10) deielectric-coating nitrogen treatment before the metal, 690 ℃ of treatment temperatures, 30 seconds time.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101102304A CN100490121C (en) | 2005-11-10 | 2005-11-10 | A method to fabricate high resistance value polysilicon resistance in high voltage IC |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101102304A CN100490121C (en) | 2005-11-10 | 2005-11-10 | A method to fabricate high resistance value polysilicon resistance in high voltage IC |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1964019A true CN1964019A (en) | 2007-05-16 |
| CN100490121C CN100490121C (en) | 2009-05-20 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005101102304A Expired - Fee Related CN100490121C (en) | 2005-11-10 | 2005-11-10 | A method to fabricate high resistance value polysilicon resistance in high voltage IC |
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|---|---|
| CN (1) | CN100490121C (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102024539B (en) * | 2009-09-17 | 2012-04-18 | 上海宏力半导体制造有限公司 | Resistor structure |
| CN108122959A (en) * | 2017-12-25 | 2018-06-05 | 深圳市晶特智造科技有限公司 | The production method of polysilicon high-ohmic |
| CN109904117A (en) * | 2019-03-26 | 2019-06-18 | 武汉新芯集成电路制造有限公司 | A kind of interconnection structure and its manufacturing method |
-
2005
- 2005-11-10 CN CNB2005101102304A patent/CN100490121C/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102024539B (en) * | 2009-09-17 | 2012-04-18 | 上海宏力半导体制造有限公司 | Resistor structure |
| CN108122959A (en) * | 2017-12-25 | 2018-06-05 | 深圳市晶特智造科技有限公司 | The production method of polysilicon high-ohmic |
| CN108122959B (en) * | 2017-12-25 | 2020-08-21 | 李友洪 | Method for manufacturing polysilicon high resistance |
| CN109904117A (en) * | 2019-03-26 | 2019-06-18 | 武汉新芯集成电路制造有限公司 | A kind of interconnection structure and its manufacturing method |
| CN109904117B (en) * | 2019-03-26 | 2019-10-08 | 武汉新芯集成电路制造有限公司 | A kind of interconnection structure and its manufacturing method |
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| Publication number | Publication date |
|---|---|
| CN100490121C (en) | 2009-05-20 |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20140108 |
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Effective date of registration: 20140108 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corp. Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Patentee before: Shanghai Hua Hong NEC Electronics Co.,Ltd. |
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