CN103021865B - Metal silicide film and the manufacture method of ultra-shallow junctions - Google Patents
Metal silicide film and the manufacture method of ultra-shallow junctions Download PDFInfo
- Publication number
- CN103021865B CN103021865B CN201210536723.4A CN201210536723A CN103021865B CN 103021865 B CN103021865 B CN 103021865B CN 201210536723 A CN201210536723 A CN 201210536723A CN 103021865 B CN103021865 B CN 103021865B
- Authority
- CN
- China
- Prior art keywords
- ultra
- metal silicide
- shallow junctions
- silicide film
- manufacture method
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The present invention relates to technical field of semiconductors, disclose the manufacture method of a kind of metal silicide film and ultra-shallow junctions.In the present invention, by using the mixture of metal and semiconductor doping impurity to do target, physical vapour deposition (PVD) PVD method deposits mixture film on a semiconductor substrate, and wet method removes this mixture film, and carries out annealing formation metal silicide film and ultra-shallow junctions.Owing to using the mixture of metal and semiconductor doping impurity to do target deposit mixture film, and before carrying out heating anneal, wet method removes mixture film, make synchronize to be formed from limiting limit ultrathin homogeneous metal silicide film and ultra-shallow junctions in semiconductor field effect transistor manufacturing process, can apply in 14 nanometers, 11 nanometers and techniques below node field effect transistor.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly to metal silicide film and the manufacture method of ultra-shallow junctions.
Background technology
Along with the progress of semi-conductor industry, the characteristic size of semiconductor device is more and more less along with the innovation of Technology.While the lateral dimension of device constantly reduces, the longitudinal size of device is also correspondingly reducing.Especially into 65 nanometers and with lower node, require that source/drain region and source/drain extension area correspondingly shoal, junction depth is commonly called ultra-shallow junctions (UltraShallowJunction less than the doping knot of 100 nanometers, it is called for short " USJ "), ultra-shallow junctions can preferably improve the short-channel effect of device.Along with ultra-shallow junctions is more and more shallow, one of significant challenge that ultra-shallow junctions technology faces is how to solve to reduce the contradiction between series parasitic resistance and the junction depth reducing ultra-shallow junctions.
In prior art, generally use ion implantation technique to form ultra-shallow junctions, such as form highly doped source region and the drain region of metal-oxide semiconductor (MOS) MOS transistor.That is, with grid structure as mask, it is injected in Semiconductor substrate with N-type or p-type impurity, then carries out annealing activation, forms shallow PN junction, then metallic film is deposited, carry out heating anneal, form metal silicide, and carry out the wet etching remaining metal of removing, to form metal silicide.As transistor size shrinks, the length of its grid also can shorten therewith.Continuous shortening along with grid length, it is desirable to source/drain and source/drain extension area correspondingly shoal.Generally utilize ultra-low energy ion to inject at present and Millisecond laser annealing activation technique is to form ultra-shallow junctions.The ultra-shallow junctions junction depth of the semiconductor field effect transistor of future technology node will be less than 10 nanometers.Owing to huge challenge and the annealing of ultra-low energy ion injection technique itself the most all can cause certain impurity spread when activating, inject with conventional ultra-low energy ion and activation technique of annealing is formed and is applicable to the field-effect transistor of future technology node and is faced with huge challenge.
Summary of the invention
It is an object of the invention to provide the manufacture method of a kind of metal silicide film and ultra-shallow junctions, make synchronize to be formed from limiting limit ultrathin homogeneous metal silicide film and ultra-shallow junctions in semiconductor field effect transistor manufacturing process, can apply in 14 nanometers, 11 nanometers and techniques below node field effect transistor.
For solving above-mentioned technical problem, embodiments of the present invention provide the manufacture method of a kind of metal silicide film and ultra-shallow junctions, comprise the steps of
A., Semiconductor substrate is provided；
B. do target with the mixture of metal and semiconductor doping impurity, use physical vapour deposition (PVD) PVD method to deposit mixture film on the semiconductor substrate；
C. wet method removes described mixture film；
D. the described Semiconductor substrate having carried out mixture film deposit and removal is annealed, form metal silicide film and ultra-shallow junctions；Described an ultra shallow becomes PN junction or metal semiconductor junction.
Embodiment of the present invention is in terms of existing technologies, by using the mixture of metal and semiconductor doping impurity to do target, physical vapour deposition (PVD) PVD method deposits mixture film on a semiconductor substrate, and wet method removes this mixture film, and carries out annealing formation metal silicide film and ultra-shallow junctions.Owing to using the mixture of metal and semiconductor doping impurity to do target deposit mixture film, and before carrying out heating anneal, wet method removes mixture film, make synchronize to be formed from limiting limit ultrathin homogeneous metal silicide film and ultra-shallow junctions in semiconductor field effect transistor manufacturing process, can apply in 14 nanometers, 11 nanometers and techniques below node field effect transistor.
It addition, before described step D, at least perform step B and described step C described in twice；That is, before annealing, the deposit and the wet method that repeatedly carry out mixture film are removed, and can limit metal silicide film and the thickness of ultra-shallow junctions by the number of times repeatedly performed, it is possible to so that the metal silicide film ultimately formed and ultra-shallow junctions are evenly.
It addition, in the step at least performing step B described in twice and described step C, when performing described step B, use the mixture of different metals and semiconductor doping impurity to do target every time.It is to say, metal can be selected according to actual needs to prepare metal silicide, can expand the range of choice of spendable metal when forming metal silicide, the resistance making metal silicide is the least, applies more flexible.
It addition, in described step B, target ionization is become ionic condition so that it is produce metal ion and semiconductor doping foreign ion, and plus substrate bias on the semiconductor substrate.Described target ionization is become ionic condition by add on described target first bias realize.
By by target ionizing, and the deposit of mixture film is carried out by the bias of plus substrate on a semiconductor substrate, on the one hand metal ion and semiconductor doping foreign ion can be made to be deposited on semiconductor substrate surface with certain acceleration, the diffusion depth of ion can be controlled；On the other hand uniformity and the stability of thin-film deposition on three dimensional structure can be improved.
It addition, in described step D, microwave heating can be used to anneal.Using microwave heating to carry out in the step annealed, described in carry out the cavity of the microwave heating equipment that microwave heating annealing is used and contain multi-modal and multifrequency electromagnetic wave when heating.
By using microwave heating annealing technology, metal silicide and ultra-shallow junctions can be formed at relatively low temperature, make metal silicide energy stable existence.
Accompanying drawing explanation
Fig. 1 is the flow chart of the manufacture method of the metal silicide film according to first embodiment of the invention and ultra-shallow junctions；
Fig. 2 A to Fig. 2 E is the structural profile schematic diagram that the metal silicide film of first embodiment of the invention is corresponding with each step of the manufacture method of ultra-shallow junctions；
Fig. 3 be the ultra-shallow junctions semiconductor field effect transistor of first embodiment of the invention preparation method in the mixture of metal and semiconductor doping impurity is deposited structural representation on a semiconductor substrate.
Detailed description of the invention
For making the object, technical solutions and advantages of the present invention clearer, below in conjunction with accompanying drawing, the embodiments of the present invention are explained in detail.But, it will be understood by those skilled in the art that in each embodiment of the present invention, in order to make reader be more fully understood that, the application proposes many ins and outs.But, even if there is no these ins and outs and many variations based on following embodiment and amendment, it is also possible to realize the application each claim technical scheme required for protection.
First embodiment of the present invention relates to the manufacture method of a kind of metal silicide film and ultra-shallow junctions, and idiographic flow is as it is shown in figure 1, comprise the steps of
Step 101, it is provided that Semiconductor substrate 201, as shown in Figure 2 A；This Semiconductor substrate can be silicon (Si), germanium (Ge), SiGe (SiGe), III-V quasiconductor.It is formed with grid structure 202 on a semiconductor substrate, comprises the protective layer of gate dielectric layer, gate electrode and sidewall thereof.The method forming grid structure is consistent with prior art, does not repeats them here.
Step 102, does target with the mixture of metal and semiconductor doping impurity, uses physical vapour deposition (PVD) PVD method to deposit mixture film on a semiconductor substrate, and as shown in Figure 2 B, 203 is mixture film.
Physical vapour deposition (PVD) (PVD) is the known technology used in IC manufacturing.When carrying out PVD, required coating material, as injection target, is deposited on substrate.As it is shown on figure 3, be the schematic diagram of pvd chamber body.Target 301 and the Semiconductor substrate 201 defining grid structure 202 being placed in vacuum cavity 300, this cavity is evacuated and is maintained at low-down pressure (such as, less than 10 millitorrs).
Noble gas 303 it is full of, such as argon, and by gas pressure required in pumping system (not shown) holding chamber body in vacuum cavity 300.Use conventional method, low-pressure gas produces glow discharge plasma, at least part of gas ionization.If target is applied in suitable bias, the cation in plasma can accelerate towards target, causes target 305 to spray from target electrode.The injected target material deposition of part is in Semiconductor substrate 201, to form blend films 203.
In the present embodiment, target is enriched in the mixture of metal, presented in polycrystalline solids material.This mixture can be mixed by the powder of metal dust and semiconductor doping impurity, and is obtained by heat treatment or other process.Semiconductor doping impurity in target is evenly distributed in metal.Wherein, in the mixture of metal and semiconductor doping impurity the content of semiconductor doping impurity between 0.1% to 5%.Metal can be for nickel (Ni), platinum (Pt), platinum (Pt), titanium (Ti), cobalt (Co), any one in molybdenum (Mo) or the alloy of they combination in any formation.Great majority are applied, preferably nickel.The usual Pt of nickel, W or other above-mentioned metallic combinations are with beneficially stability and the adjustment of schottky barrier height.Semiconductor doping impurity can be p-type doped with boron (B), the sub-boron (BF of fluorination2), any one or the mixture of combination in any in indium (Indium)；Or any one in n-type doping phosphorus (P), arsenic (As) or the mixture of combination in any.
Although target is metal and the mixture of semiconductor doping impurity, but the technological process of PVD method is consistent with prior art, does not repeats them here.After deposit mixture film, metal ion and semiconductor doping foreign ion can penetrate in Semiconductor substrate, form the ion diffusion region of an ultra shallow in the semiconductor substrate, as shown in 204 in Fig. 2 C.Specifically, metal in mixture film 203 can form metal silicide with Semiconductor substrate reaction, semiconductor doping impurity in mixture film 203 spreads in the interface between the interface between metal silicide, metal silicide and Semiconductor substrate, ion diffusion region and Semiconductor substrate and Semiconductor substrate simultaneously, forms ion diffusion region 204.
Step 103, wet method removes mixture film, as shown in Figure 2 D.In this step, the wet etching technique of routine can be used to remove the remaining mixture film of semiconductor substrate surface, do not repeat them here.
Step 104, the Semiconductor substrate having carried out mixture film deposit and removal is annealed, forms metal silicide film and ultra-shallow junctions, as shown in Figure 2 E, 205 and 207 is the Metal-silicides Contact district of source electrode or drain electrode, and 206 and 208 is the impurity diffusion zone of source electrode or drain electrode.Under normal circumstances, form PN junction between impurity diffusion zone and the Semiconductor substrate of 206 and 208, and between metal silicide 205/207 and impurity diffusion zone 206/208, form Ohmic contact.But, when the impurity diffusion zone of 206 and 208 formed is sufficiently small (such as less than 1.5 nanometers), between metal silicide and Semiconductor substrate, form metal-semiconductor contact.
In this step, the rapid thermal annealing (RTP) that can use routine is annealed, it would however also be possible to employ microwave heating is annealed, and its technological process is similar with conventional annealing process, form metal silicide and ultra-shallow junctions at relatively low temperature, make metal silicide energy stable existence.Additionally, underlayer temperature when depositing mixture film on a semiconductor substrate can be between 0 to 300 DEG C.Formation temperature according to different metal silicide and the difference of the maximum temperature of stable existence, the temperature of annealing can be between 300 to 800 DEG C.In a step 102, metal and semiconductor doping impurity spread to Semiconductor substrate, form metal silicide；And the semiconductor doping impurity contained in metal silicide, when annealing, may proceed to spread to Semiconductor substrate, form ultra-shallow junctions.Owing to the formation temperature of metal silicide and the temperature of stable existence are relatively low, such as nickle silicide (NiSi), cobalt silicide (CoSi2), titanium silicide (TiSi2) stable existence temperature be less than 600,700,1000 DEG C respectively, therefore, form metal silicide at relatively low temperature and during ultra-shallow junctions, semiconductor doping impurity may be caused can not fully to activate in the semiconductor substrate, but, if can fully activate, then can form PN junction；And if can not fully activate, then can also form metal semiconductor junction；It is to say, during forming ultra-shallow junctions and super thin metal silicide, the ultra-shallow junctions of formation can be PN junction, or metal semiconductor junction.
The ultra-shallow junctions and the metal silicide film that use the formation of above-mentioned steps can apply in ultra-shallow junctions semiconductor field effect transistor, the thickness of metal silicide is about 3 to 12 nanometers, junction depth is about between 1 to 15 nanometer, and the peak doping concentration in the source/drain regions of ultra-shallow junctions is about every cubic centimetre 2 × 1019To 2 × 1020Individual ion, the length of grid structure is about 7 to 25 nanometers.
Additionally, it is noted that by using microwave heating annealing technology, metal silicide and ultra-shallow junctions can be formed at relatively low temperature, makes metal silicide energy stable existence.In addition, on substrate, different material absorbed microwave energy ability has difference, and, defect (defect) in microwave heating and substrate is the most relevant, and the damage of the semiconductor lattice that impurity or other factors cause can be regarded as defect, and defect is the most, microwave heating effects is the biggest, namely defect can strengthen the ability of microwave absorption, for this feature, uses microwave heating to carry out annealing and can improve the efficiency of heating surface.
In addition, it should be noted that, owing to mixture film containing metal and semiconductor doping impurity, so, when carrying out microwave heating annealing, the cavity of microwave heating equipment needs containing multi-modal and multifrequency electromagnetic wave when heating, and the mid frequency of microwave, between 1.5GHz to 15GHz, makes the material being intended to carry out heating fully be heated.In addition, what deserves to be explained is, when carrying out microwave heating, microwave heating equipment use microwave electromagnetic waves near 5.8GHz in Gauss distribution, multi-frequency heating can be carried out with the interval of 30Hz-50Hz, simultaneously inside cavity, the microwave of these different frequencies has the feature of multi-modal (multi-mode) simultaneously, so can ensure that uniformity and concordance that microwave energy is distributed in inside cavity, further results in uniformity during silicon and concordance.
Compared with prior art, present embodiment does target by using the mixture of metal and semiconductor doping impurity, physical vapour deposition (PVD) PVD method deposits mixture film on a semiconductor substrate, wet method removes this mixture film, and carries out annealing formation limit ultrathin homogeneous metal silicide film and ultra-shallow junctions.Owing to using the mixture of metal and semiconductor doping impurity to do target deposit mixture film, and before carrying out heating anneal, wet method removes mixture film, make synchronize to be formed from limiting limit ultrathin homogeneous metal silicide film and ultra-shallow junctions in semiconductor field effect transistor manufacturing process, can apply in 14 nanometers, 11 nanometers and techniques below node field effect transistor.
Second embodiment of the present invention relates to the manufacture method of a kind of metal silicide film and ultra-shallow junctions.Second embodiment has done further improvement on the basis of the first embodiment, mainly thes improvement is that: in second embodiment of the invention, before annealing, at least performs twice deposit and wet method removes mixture film；That is, before annealing, the deposit and the wet method that repeatedly carry out mixture film are removed, and can limit metal silicide film and the thickness of ultra-shallow junctions by the number of times repeatedly performed, it is possible to so that the metal silicide film ultimately formed and ultra-shallow junctions are evenly.
Additionally, during removing in the deposit and wet method repeating mixture film, when can carry out the deposit of mixture film, use the mixture of different metals and semiconductor doping impurity to do target the most every time.Such as, when carrying out the deposit of mixture film, it being adopted as the mixture of platinum and boron for the first time, second time uses nickel and the mixture of boron, or uses nickel and the mixture of indium；It is to say, metal can be selected according to actual needs to prepare metal silicide, can expand the range of choice of spendable metal when forming metal silicide, the resistance making metal silicide is the least, applies more flexible.
Third embodiment of the present invention relates to the manufacture method of a kind of metal silicide film and ultra-shallow junctions.3rd embodiment has done further improvement on the basis of the first embodiment or the second embodiment, mainly the improvement is that: in third embodiment of the invention, the high-power impulse magnetron sputtering technology (HiPIMS) improved is used to carry out PVD deposit, by by target ionizing, and the deposit of mixture film is carried out by the bias of plus substrate on a semiconductor substrate, on the one hand metal ion and semiconductor doping foreign ion can be made to be deposited on semiconductor substrate surface with certain acceleration, control the diffusion depth of ion；On the other hand uniformity and the stability of thin-film deposition on three dimensional structure can be improved.
Specifically, target is being done with the mixture of metal and semiconductor doping impurity, during using physical vapour deposition (PVD) PVD method to deposit mixture film on a semiconductor substrate, target ionization is become ionic condition, it is made to produce metal ion and semiconductor doping foreign ion, and plus substrate bias on a semiconductor substrate.Wherein, target ionization become ionic condition realize by adding the first bias on target.
Additionally, the first bias can be any one in Dc bias, AC bias or pulsed bias.The size of the first bias depends on that the PVD system used, i.e. PVD system are different, and the size of this first bias is the most correspondingly varied from；In general, the size of the first bias is 200V～1000V, and wherein for AC bias and pulsed bias, above-mentioned size refers to its virtual value.It addition, substrate bias is any one in Dc bias, AC bias or pulsed bias.The size of substrate bias is adjustable, by adjusting the size of substrate bias, can adjust the quantity of the metal ion diffusing to semiconductor substrate surface, so that the thickness of the metal-semiconductor compounds thin film ultimately formed is adjustable.In general, the size of substrate bias is 200V～1000V, and wherein for AC bias and pulsed bias, above-mentioned size refers to its virtual value.
Four embodiment of the invention relates to a kind of semiconductor device, as shown in Figure 2 E, comprise: metal silicide film and ultra-shallow junctions, this metal silicide film and ultra-shallow junctions do target with the mixture of metal and semiconductor doping impurity, physical vapour deposition (PVD) PVD method is used to deposit mixture film on a semiconductor substrate, wet method removes mixture film, and carries out annealing formation；Wherein, an ultra shallow becomes PN junction or metal semiconductor junction.
Owing to using the mixture of metal and semiconductor doping impurity to do target deposit mixture film, and before carrying out heating anneal, wet method removes mixture film, make synchronize to be formed from limiting limit ultrathin homogeneous metal silicide film and ultra-shallow junctions in semiconductor field effect transistor manufacturing process, can apply in 14 nanometers, 11 nanometers and techniques below node field effect transistor.Such as, the thickness of metal silicide is about 3 to 12 nanometers, and junction depth is about between 1 to 15 nanometer, and the peak doping concentration in the source/drain regions of ultra-shallow junctions is about every cubic centimetre 2 × 1019To 2 × 1020Individual ion, the length of grid structure is about 7 to 25 nanometers.
It should be noted that the content of semiconductor doping impurity is between 0.1% to 5% in the mixture of metal and semiconductor doping impurity.The alloy that metal can be formed for any one in nickel (Ni), platinum (Pt), platinum (Pt), titanium (Ti), cobalt (Co), molybdenum (Mo) or their combination in any.Great majority are applied, preferably nickel.The usual Pt of nickel, W or other above-mentioned metallic combinations are with beneficially stability and the adjustment of schottky barrier height.Semiconductor doping impurity can be p-type doped with boron (B), the sub-boron (BF of fluorination2), any one or the mixture of combination in any in indium (Indium)；Or any one in n-type doping phosphorus (P), arsenic (As) or the mixture of combination in any.
It is seen that, present embodiment is the system embodiment corresponding with the first embodiment, and present embodiment can be worked in coordination enforcement with the first embodiment.The relevant technical details mentioned in first embodiment is the most effective, in order to reduce repetition, repeats no more here.Correspondingly, the relevant technical details mentioned in present embodiment is also applicable in the first embodiment.
It will be understood by those skilled in the art that the respective embodiments described above are to realize the specific embodiment of the present invention, and in actual applications, can to it, various changes can be made in the form and details, without departing from the spirit and scope of the present invention.
Claims (16)
1. a metal silicide film and the manufacture method of ultra-shallow junctions, it is characterised in that comprise the steps of
A., Semiconductor substrate is provided；
B. do target with the mixture of metal and semiconductor doping impurity, use physical vaporous deposition to deposit mixture film on the semiconductor substrate；
C. wet method removes described mixture film；
D. the described Semiconductor substrate having carried out mixture film deposit and removal is annealed, form metal silicide film and ultra-shallow junctions；Described an ultra shallow becomes PN junction or metal semiconductor junction.
Metal silicide film the most according to claim 1 and the manufacture method of ultra-shallow junctions, it is characterised in that before described step D, at least perform step B and described step C described in twice.
Metal silicide film the most according to claim 2 and the manufacture method of ultra-shallow junctions, it is characterized in that, in the step at least performing step B described in twice and described step C, when performing described step B, use the mixture of different metals and semiconductor doping impurity to do target every time.
Metal silicide film the most according to claim 1 and the manufacture method of ultra-shallow junctions, it is characterized in that, in described step B, target ionization is become ionic condition, it is made to produce metal ion and semiconductor doping foreign ion, and plus substrate bias on the semiconductor substrate.
Metal silicide film the most according to claim 4 and the manufacture method of ultra-shallow junctions, it is characterised in that described target ionization is become ionic condition by add on described target first bias realize.
Metal silicide film the most according to claim 5 and the manufacture method of ultra-shallow junctions, it is characterised in that described first bias is any one in Dc bias, AC bias or pulsed bias.
Metal silicide film the most according to claim 4 and the manufacture method of ultra-shallow junctions, it is characterised in that described substrate bias is any one in Dc bias, AC bias or pulsed bias.
Metal silicide film the most according to claim 1 and the manufacture method of ultra-shallow junctions, it is characterised in that in described step D, use rapid thermal annealing to anneal；
Or use microwave heating to anneal.
Metal silicide film the most according to claim 8 and the manufacture method of ultra-shallow junctions, it is characterized in that, using microwave heating to carry out in the step annealed, described in carry out the cavity of the microwave heating equipment that microwave heating annealing is used and use multi-modal and multifrequency electromagnetic wave when heating.
Metal silicide film the most according to claim 9 and the manufacture method of ultra-shallow junctions, it is characterised in that using microwave heating to carry out in the step annealed, the frequency of described microwave is between 1.5GHZ to 15GHZ；During heating a length of 1 to 30 minute.
11. according to the metal silicide film described in any one of claim 1 to 10 and the manufacture method of ultra-shallow junctions, it is characterised in that described metal is any one in nickel, platinum, titanium, cobalt, molybdenum or the alloy of their combination in any formation.
12. according to the metal silicide film described in any one of claim 1 to 10 and the manufacture method of ultra-shallow junctions, it is characterised in that described semiconductor doping impurity is boron, the sub-boron F of fluorination2, any one or the mixture of combination in any in indium Indium；
Or any one in phosphorus, arsenic or the mixture of combination in any.
13. according to the metal silicide film described in any one of claim 1 to 10 and the manufacture method of ultra-shallow junctions, it is characterised in that in the mixture of described metal and semiconductor doping impurity, the content of semiconductor doping impurity is between 0.1% to 5%.
14. according to the metal silicide film described in any one of claim 1 to 10 and the manufacture method of ultra-shallow junctions, it is characterised in that described Semiconductor substrate is silicon, germanium, SiGe, III-V quasiconductor.
15. according to the metal silicide film described in any one of claim 1 to 10 and the manufacture method of ultra-shallow junctions, it is characterised in that in described step B, and underlayer temperature during deposit mixture film is 0 to 300 DEG C on the semiconductor substrate.
16. according to the metal silicide film described in any one of claim 1 to 10 and the manufacture method of ultra-shallow junctions, it is characterised in that in described step D, the temperature of described annealing is 300 to 800 DEG C.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210536723.4A CN103021865B (en) | 2012-12-12 | 2012-12-12 | Metal silicide film and the manufacture method of ultra-shallow junctions |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210536723.4A CN103021865B (en) | 2012-12-12 | 2012-12-12 | Metal silicide film and the manufacture method of ultra-shallow junctions |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103021865A CN103021865A (en) | 2013-04-03 |
| CN103021865B true CN103021865B (en) | 2016-08-03 |
Family
ID=47970328
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210536723.4A Expired - Fee Related CN103021865B (en) | 2012-12-12 | 2012-12-12 | Metal silicide film and the manufacture method of ultra-shallow junctions |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103021865B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9076730B2 (en) * | 2012-12-12 | 2015-07-07 | Fudan University | Metal silicide thin film, ultra-shallow junctions, semiconductor device and method of making |
| CN105977124A (en) * | 2016-07-29 | 2016-09-28 | 上海华力微电子有限公司 | Bearing platform of semiconductor substrate and ion implantation device and technology |
| CN107369622B (en) * | 2017-06-30 | 2020-02-14 | 上海集成电路研发中心有限公司 | Preparation method of ultra-shallow junction |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6281126B1 (en) * | 1998-03-16 | 2001-08-28 | Oki Electronic Industry Co., Ltd. | Process for manufacturing semiconductor device |
| US6426291B1 (en) * | 2000-08-31 | 2002-07-30 | Micron Technology, Inc. | Method of co-deposition to form ultra-shallow junctions in MOS devices using electroless or electrodeposition |
| CN1799125A (en) * | 2003-06-03 | 2006-07-05 | 皇家飞利浦电子股份有限公司 | Formation of junctions and silicides with reduced thermal budget |
| CN102169830A (en) * | 2011-03-17 | 2011-08-31 | 复旦大学 | Manufacturing method of metal semiconductor compound film |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6660621B1 (en) * | 2002-06-07 | 2003-12-09 | Advanced Micro Devices, Inc. | Method of forming ultra-shallow junctions in a semiconductor wafer with silicon layer deposited from a gas precursor to reduce silicon consumption during salicidation |
| US6835656B1 (en) * | 2002-06-07 | 2004-12-28 | Advanced Micro Devices, Inc. | Method of forming ultra-shallow junctions in a semiconductor wafer with a deposited silicon layer and in-situ anneal to reduce silicon consumption during salicidation |
| US7119024B2 (en) * | 2003-07-10 | 2006-10-10 | Micron Technology, Inc. | Method and structure for a self-aligned silicided word line and polysilicon plug during the formation of a semiconductor device |
| TWI547999B (en) * | 2007-09-17 | 2016-09-01 | Ｄｓｇｉ公司 | System for and method of microwave annealing semiconductor material |
-
2012
- 2012-12-12 CN CN201210536723.4A patent/CN103021865B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6281126B1 (en) * | 1998-03-16 | 2001-08-28 | Oki Electronic Industry Co., Ltd. | Process for manufacturing semiconductor device |
| US6426291B1 (en) * | 2000-08-31 | 2002-07-30 | Micron Technology, Inc. | Method of co-deposition to form ultra-shallow junctions in MOS devices using electroless or electrodeposition |
| CN1799125A (en) * | 2003-06-03 | 2006-07-05 | 皇家飞利浦电子股份有限公司 | Formation of junctions and silicides with reduced thermal budget |
| CN102169830A (en) * | 2011-03-17 | 2011-08-31 | 复旦大学 | Manufacturing method of metal semiconductor compound film |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103021865A (en) | 2013-04-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9252015B2 (en) | Ultra-shallow junction semiconductor field-effect transistor and method of making | |
| US7553763B2 (en) | Salicide process utilizing a cluster ion implantation process | |
| US20170178908A1 (en) | Damage free enhancement of dopant diffusion into a substrate | |
| CN103021865B (en) | Metal silicide film and the manufacture method of ultra-shallow junctions | |
| CN102184961B (en) | Asymmetrical gate metal oxide semiconductor (MOS) device and manufacturing method thereof | |
| TWI531004B (en) | Method for fabricating a semiconuctor chip | |
| CN103035533B (en) | The preparation method of for ultra-shallow junctions semiconductor field effect transistor | |
| CN105789320A (en) | Metal oxide film transistor and manufacturing method thereof as well as array substrate | |
| Cojocaru-Mirédin et al. | Boron redistribution during reactive diffusion in Ni–Si contacts | |
| US9076730B2 (en) | Metal silicide thin film, ultra-shallow junctions, semiconductor device and method of making | |
| CN105702575A (en) | Semiconductor device manufacturing method | |
| CN112885716B (en) | Method for forming semiconductor structure | |
| Current | Perspectives on low-energy ion (and neutral) implantation | |
| Chen et al. | Nickel silicide formation using pulsed laser annealing for nMOSFET performance Improvement | |
| US20210119022A1 (en) | Methods for forming ultra-shallow junctions having improved activation | |
| TWI492285B (en) | Forming method of metal semiconductor compound | |
| Deng et al. | A modified scheme to tune the Schottky Barrier Height of NiSi by means of dopant segregation technique | |
| CN102456556A (en) | Formation method of metal silicide | |
| Papasouliotis et al. | Formation of Ultra‐Shallow Junctions by Advanced Plasma Doping Techniques | |
| CN106328531B (en) | The forming method of fin formula field effect transistor | |
| Jin | Boron activation and diffusion in polycrystalline silicon with flash-assist rapid thermal annealing | |
| CN103839797B (en) | Preparation method of IGBT short-circuit collector structure | |
| CN102810468B (en) | High-k gate dielectric interface optimization method | |
| CN102569087A (en) | Mos transistor and manufacturing method thereof | |
| Kim et al. | Ultra-thin and High-quality Pt-Silicidation using CW Laser Annealing Process |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20160803 Termination date: 20211212 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |