CN106328531B - The forming method of fin formula field effect transistor - Google Patents
The forming method of fin formula field effect transistor Download PDFInfo
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- CN106328531B CN106328531B CN201510377770.2A CN201510377770A CN106328531B CN 106328531 B CN106328531 B CN 106328531B CN 201510377770 A CN201510377770 A CN 201510377770A CN 106328531 B CN106328531 B CN 106328531B
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
A kind of forming method of fin formula field effect transistor, it include: the semiconductor substrate for being provided with p type island region domain and n-type region, p type island region domain semiconductor substrate surface has the first fin and the first grid structure across the first fin, and n-type region semiconductor substrate surface has the second fin and the second grid structure across the second fin；First is carried out to the first fin of first grid structure two sides, injection is lightly doped, forms the first lightly doped district；After first is lightly doped injection, the first side wall is formed in first grid structure two sides；The first source-drain area is formed in the first fin portion surface；In the second side wall of second grid structure two sides formation, second the second fin of side wall covering part, the second side wall is thinner than the first side wall；The second source-drain area is formed in the second fin portion surface, has the second ion in the second source-drain area, and diffuse into the second ion in the second fin of the second side wall covering, forms the second lightly doped district.The forming method of fin formula field effect transistor improves the performance of fin formula field effect transistor.
Description
Technical field
The present invention relates to field of semiconductor manufacture more particularly to a kind of forming methods of fin formula field effect transistor.
Background technique
MOS transistor is one of most important element in modern integrated circuits.The basic structure of MOS transistor includes: half
Conductor substrate；Source-drain area positioned at the gate structure of substrate surface, in gate structure semiconductor substrates on two sides.MOS crystal
Pipe adjusts by applying voltage in grid and generates switching signal by the electric current of gate structure bottom channel.
With the development of semiconductor technology, the MOS transistor of traditional plane formula dies down to the control ability of channel current,
Cause serious leakage current.Fin formula field effect transistor (Fin FET) is a kind of emerging multi-gate device, it generally comprises protrusion
In the fin of semiconductor substrate surface, the top surface of fin and the gate structure of side wall described in covering part are located at grid knot
Source-drain area in the fin of structure two sides.
The method for forming fin formula field effect transistor includes: offer semiconductor substrate, and the semiconductor substrate surface has
The fin and gate structure across the fin of protrusion, the top of fin described in the gate structure covering part and side wall；
Side wall is formed in gate structure two sides side wall；Ion is carried out using side wall and gate structure as fin of the exposure mask to gate structure two sides
Injection forms the source-drain area of heavy doping.
As characteristic size further reduces, the prior art formed fin formula field effect transistor Performance And Reliability compared with
Difference.
Summary of the invention
Problems solved by the invention is to provide a kind of forming method of fin formula field effect transistor, to improve fin field effect
The Performance And Reliability of transistor.
To solve the above problems, the present invention provides a kind of forming method of fin formula field effect transistor, comprising: offer is partly led
Body substrate, semiconductor substrate have p type island region domain and n-type region, and the semiconductor substrate surface in p type island region domain has the first fin and cross
First grid structure across the first fin, the top surface and side wall of first grid structure the first fin of covering part, n-type region
Semiconductor substrate surface have the second fin and the second grid structure across the second fin, second grid structure covering part
The top surface and side wall of second fin；First is carried out to the first fin of first grid structure two sides, injection is lightly doped, formed
First lightly doped district；First is lightly doped after injection, forms the first side wall, the first side in first grid structure two sides sidewall surfaces
The first lightly doped district of wall covering part；The first fin portion surface in first grid structure two sides forms the first source-drain area, the first source
Side wall of the drain region close to the first side wall；The second side wall, the thickness of the second side wall are formed in second grid structure two sides sidewall surfaces
Less than the thickness of the first side wall, second the second fin of side wall covering part；The second fin portion surface in second grid structure two sides
Form the second source-drain area, the second source-drain area doped with the second ion in the second source-drain area, and makes close to the side wall of the second side wall
Second ion diffuses into the second fin of the second side wall covering, forms the second lightly doped district.
Optionally, third ion is injected in the second fin of the second source-drain area lower part using third ion implanting, is formed
Third source-drain area, and third ion is made to diffuse into the second lightly doped district；The third ion and the second ion are identical.
Optionally, for the ion that the third ion implanting uses for P ion, Implantation Energy range is 1KeV~8KeV, note
Entering dosage range is 2E14atom/cm2~2E15atom/cm2, implant angle is 0 degree~10 degree.
Optionally, for the ion that third ion implanting uses for As ion, Implantation Energy range is 2KeV~10KeV, injection
Dosage range is 2E14atom/cm2~2E15atom/cm2, implant angle is 0 degree~10 degree.
Optionally, depth of the third source-drain area in the second fin is 30nm~60nm.
Optionally, the method for first side wall is formed are as follows: form the first side wall material in covering p type island region domain and n-type region
The bed of material；The first barrier layer of covering n-type region is formed, first barrier layer is located at the first spacer material layer table of n-type region
Face；Using the first barrier layer as the first spacer material layer in mask etching p type island region domain, in the first grid structure two sides in p type island region domain
Form the first side wall.
Optionally, the method for forming the first source-drain area includes: to remove first grid knot by mask etching of the first barrier layer
The first fin of part of structure two sides, so that the height of the first fin reduces；Remove the first barrier layer；The first fin after etching
Surface epitaxial growth the first source-drain area material layer；First ion is adulterated to the first source-drain area material layer.
Optionally, the first ion is adulterated in situ while the first source-drain area material layer described in epitaxial growth.
Optionally, the method for second side wall is formed are as follows: remove the first spacer material layer of n-type region；Form covering P
Second side walling bed of material in type region and n-type region；The third barrier layer in covering p type island region domain is formed, third barrier layer is located at p-type
The surface of second side walling bed of material in region；Using third barrier layer as second side walling bed of material of mask etching n-type region, in N
The second grid structure two sides in type region form the second side wall.
Optionally, the method for forming the second source-drain area includes: to remove second grid knot by mask etching of third barrier layer
The second fin of part of structure two sides, so that the height of the second fin reduces；Remove third barrier layer；The second fin after etching
Surface epitaxial growth the second source-drain area material layer；Second ion is adulterated to the second source-drain area material layer.
Optionally, the second ion is adulterated in situ while the second source-drain area material layer described in epitaxial growth.
Optionally, second ion is N-type ion.
Optionally, the N-type ion is P or As.
Optionally, first side wall with a thickness of 25nm~40nm.
Optionally, second side wall with a thickness of 10nm~20nm.
Optionally, the material of first side wall is silicon nitride.
Optionally, the material of second side wall is silicon nitride.
Optionally, described first the ion for injecting and using being lightly doped as B ion, Implantation Energy range is 1KeV~5KeV,
Implantation dosage range is 1E14atom/cm2~2E15atom/cm2, implant angle is 0 degree~20 degree.
Optionally, doped with P-type ion in first source-drain area.
Optionally, the first grid structure includes across the first gate dielectric layer of the first fin and positioned at the first gate medium
The first gate electrode layer of layer surface；The second grid structure includes across the second gate dielectric layer of the second fin and positioned at second
Second gate electrode layer on gate dielectric layer surface.
Compared with prior art, technical solution of the present invention has the advantage that
The forming method of fin formula field effect transistor provided by the invention, in the fin field with p type island region domain and n-type region
In effect transistor, after carrying out the first lightly doped district injection, injection is lightly doped without and then carrying out second, but first
Gate structure two sides sidewall surfaces form the first side wall；The first fin portion surface in first grid structure two sides forms the first source and drain
Area, side wall of first source-drain area close to the first side wall；The second side wall, second side are formed in second grid structure two sides sidewall surfaces
Thickness of the thickness of wall less than the first side wall, second the second fin of side wall covering part；The second of second grid structure two sides
Fin portion surface forms the second source-drain area, the second source-drain area close to the second side wall side wall, in the second source-drain area doped with second from
Son, and the second ion is diffused into the second fin of the second side wall covering, form the second lightly doped district.Due to described
The thickness of two side walls is smaller, and the distance between the second source-drain area and second grid structure are smaller, so the second of the second source-drain area
Ion can diffuse into the secondth fin of the second side wall covering, form the second lightly doped district.So as to avoid using from
The mode of son injection forms the second lightly doped district, and avoiding the second lightly doped district, there are implant damages, improve fin field effect
The performance of transistor.
Further, third ion is injected in the second fin of the second source-drain area lower part, forms third source-drain area, it is described
Third ion and the second ion are identical, and the third ion in third source-drain area can diffuse into the second lightly doped district, especially
Third ion can diffuse into the second lightly doped district in the second fin bottom section, so that being distributed in the second lightly doped district
The second ion concentration gradient reduce, the second ion is distributed more uniform in the second lightly doped district.
Detailed description of the invention
Fig. 1 to Fig. 3 is the structural schematic diagram of fin formula field effect transistor in one embodiment of the invention.
Fig. 4 to Figure 30 is the structural schematic diagram of the forming process of fin formula field effect transistor in another embodiment of the present invention.
Specific embodiment
The Performance And Reliability for the fin formula field effect transistor that the prior art is formed is poor.
Fig. 1 to Fig. 3 is the structural schematic diagram of fin formula field effect transistor in one embodiment of the invention.
The forming method of fin formula field effect transistor provides semiconductor lining the following steps are included: in conjunction with referring to figs. 1 to Fig. 3
Bottom 100, semiconductor substrate 100 have p type island region domain (region I) and n-type region (region II), the semiconductor substrate 100 in p type island region domain
Surface has the first fin 120 and the first grid structure 130 across the first fin 120,130 covering part of first grid structure
The top surface and side wall of first fin 120；100 surface of semiconductor substrate of n-type region has the second fin 121 and across the
The second grid structure 133 of two fins 121, the top surface of 133 second fin of covering part 121 of second grid structure and
Side wall；First is carried out to the first fin 120 of 130 two sides of first grid structure, injection is lightly doped, formed in the first fin 120
First lightly doped district 150；Second is carried out to the second fin 121 of 133 two sides of second grid structure, injection is lightly doped, in the second fin
The second lightly doped district 151 is formed in portion 121；First is formed on 140 surface of the first offset side wall of 130 two sides of first grid structure
Side wall 142；First grid structure 130 120 surface of the first fin formed the first source-drain area 160, the first source-drain area 160 close to
The side wall of first side wall 142；Second side is formed in the sidewall surfaces of the second offset side wall 141 of 133 two sides of second grid structure
Wall 143；The second source-drain area 161 is formed on 121 surface of the second fin of 133 two sides of second grid structure, the second source-drain area 161 is tight
The side wall of adjacent second side wall 143.
Fig. 1 is cross-sectional view of the fin formula field effect transistor along the region I the first fin extending direction；Fig. 2 is fin field effect
Answer transistor along the cross-sectional view of the region II the second fin extending direction；Fig. 3 is fin formula field effect transistor along the region I and II
Region is parallel to first grid structure and second grid structure extending direction and passes through the cross-sectional view of the first fin and the second fin.
First grid structure 130 includes the first gate dielectric layer of the first gate dielectric layer 131 and covering across the first fin 120
131 first gate electrode layer 132, second grid structure 133 include across the second fin 121 the second gate dielectric layer 134 and cover
Second gate electrode layer 135 of the second gate dielectric layer of lid 134.
First grid structure 130 and the mutual electric isolation of second grid structure 133.
Also there is isolation structure 110, the surface of isolation structure 110 is lower than the first fin 120 and the in semiconductor substrate 100
The top surface of two fins 121, isolation structure 110 are used for the first fin of electric isolation 120, and the second fin of electric isolation 121.
First is lightly doped the ion for injecting and using as B, and second is lightly doped the ion for injecting and using as As or P.
The thickness of first side wall 142 is equal to the thickness of the second side wall 143.
The study found that the reason that the fin formula field effect transistor that the above method is formed still remains Performance And Reliability difference exists
In:
In the fin field effect pipe transistor with p type island region domain and n-type region, the is carried out to fin formula field effect transistor
Two injection is lightly doped during the ion that uses for P or As, the B ion that injection use is lightly doped relative to first, P or As's
Relative atomic mass is larger, so second is lightly doped injection and will cause biggish implant damage to the second fin, that is, the formed
There are biggish implant damages in two lightly doped districts, and the implant damage is also difficult to during subsequent made annealing treatment
It is repaired.
In order to reduce the implant damage in the second lightly doped district, can inject to form described second and be lightly doped using thermion
Area, but inject to form second lightly doped district and will increase the complexity of technique, reason using thermion are as follows: thermion injection
Higher temperature is needed, typical temperature range is 400 degrees Celsius to 500 degrees Celsius, needs to increase heat source；Photoresist is in the temperature
Can occur in range it is severely deformed, cannot function as thermion injection exposure mask, so needing to form hard mask layer as thermion
The exposure mask of injection, and the pattern that the hard mask layer also needs to define the hard mask layer using photoresist is formed, increase work
Skill number and complexity；It is easy that fin is caused to damage during removing hard mask layer.
The present invention provides the forming methods of the fin formula field effect transistor of another embodiment, comprising: provides semiconductor lining
Bottom, semiconductor substrate have p type island region domain and a n-type region, and the semiconductor substrate surface in p type island region domain has the first fin and across the
The first grid structure of one fin, the top surface and side wall of first grid structure the first fin of covering part, the half of n-type region
Conductor substrate surface has the second fin and the second grid structure across the second fin, second grid structure covering part second
The top surface and side wall of fin；First is carried out to the first fin of first grid structure two sides, injection is lightly doped, forms first
Lightly doped district；First is lightly doped after injection, forms the first side wall in first grid structure two sides sidewall surfaces, the first side wall covers
The first lightly doped district of cover；The first fin portion surface in first grid structure two sides forms the first source-drain area, the first source-drain area
Close to the side wall of the first side wall；The second side wall is formed in second grid structure two sides sidewall surfaces, the thickness of the second side wall is less than
The thickness of first side wall, second the second fin of side wall covering part；The second fin portion surface in second grid structure two sides is formed
Second source-drain area, the second source-drain area doped with the second ion in the second source-drain area, and make second close to the side wall of the second side wall
Ion diffuses into the second fin of the second side wall covering, forms the second lightly doped district.
In the fin formula field effect transistor with p type island region domain and n-type region, after carrying out the first lightly doped district injection,
Injection is lightly doped without and then carrying out second, but forms the first side wall in first grid structure two sides sidewall surfaces；?
First fin portion surface of one gate structure two sides forms the first source-drain area, side wall of first source-drain area close to the first side wall；?
Two gate structure two sides sidewall surfaces form the second side wall, thickness of the thickness less than the first side wall of the second side wall, the second side wall
The second fin of covering part；The second fin portion surface in second grid structure two sides forms the second source-drain area, and the second source-drain area is tight
The side wall of adjacent second side wall doped with the second ion in the second source-drain area, and makes the second ion diffuse into the second side wall and covers
In second fin of lid, the second lightly doped district is formed.Since the thickness of second side wall is smaller, the second source-drain area and second gate
The distance between pole structure is smaller, so the second ion of the second source-drain area can diffuse into the second fin of the second side wall covering
In portion, the second lightly doped district is formed.So as to avoid the second lightly doped district is formed by the way of ion implanting, second is avoided
There are implant damages for lightly doped district, improve the performance of fin formula field effect transistor.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
In conjunction with reference Fig. 4 to Fig. 7, semiconductor substrate 200 is provided, semiconductor substrate 200 has p type island region domain (region I) and N
Type region (region II), 200 surface of semiconductor substrate in p type island region domain have the first fin 220 and across the of the first fins 220
One gate structure 230, the top surface and side wall of 230 the first fin of covering part 220 of first grid structure, the half of n-type region
Conductor substrate surface 200 has the second fin 221 and the second grid structure 233 across the second fin 221, second grid structure
The top surface and side wall of 233 the second fins of covering part 221.
Fig. 5 is section view of the fin formula field effect transistor along the first fin of the region I extending direction (A-A1 axis) in Fig. 4
Figure；Fig. 6 is cross-sectional view of the fin formula field effect transistor along the second fin of the region II extending direction (A2-A3 axis) in Fig. 4；Figure
7 are parallel to first grid structure and the extension of second grid structure along the region I in Fig. 4 and the region II for fin formula field effect transistor
Direction and the cross-sectional view obtained by the first fin and the second fin (B-B1 axis).
The semiconductor substrate 200 can be monocrystalline silicon, polysilicon or amorphous silicon；Semiconductor substrate 200 be also possible to silicon,
The semiconductor materials such as germanium, SiGe, GaAs；The semiconductor substrate 200 can be body material, be also possible to composite construction,
Such as silicon-on-insulator；The semiconductor substrate 200 can also be other semiconductor materials, no longer illustrate one by one here.This implementation
In example, the material of the semiconductor substrate 200 is silicon.
In the present embodiment, the forming method of the first fin 220 and the second fin 221 are as follows: heavy on 200 surface of semiconductor substrate
Then product fin material layer is that etching stop layer etches fin material layer with semiconductor substrate 200, forms 220 He of the first fin
Second fin 221.
In another embodiment, the first fin 220 and the second fin 221 are integrated, formation with semiconductor substrate 200
The method of first fin 220 and the second fin 221 are as follows: being formed on 200 surface of semiconductor substrate has patterned mask layer, institute
The position that patterned mask layer defines the first fin 220 and the second fin 221 is stated, using the patterned mask layer as exposure mask
Etch semiconductor substrates 200 form the first fin 220 and the second fin 221.
In the present embodiment, with p type island region domain with first fin 220 as an example, there is one second with n-type region
Fin 221 is used as example.It can according to need in actual process and form multiple first fins 220 in p type island region domain, in n-type region
Form multiple second fins 221.
First grid structure 230 includes the first gate dielectric layer of the first gate dielectric layer 231 and covering across the first fin 220
231 first gate electrode layer 232.Second grid structure 233 include across the second fin 221 the second gate dielectric layer 234 and cover
Second gate electrode layer 235 of the second gate dielectric layer of lid 234.
First gate dielectric layer 231 be located at 210 surface of isolation structure, 220 top surface of the first fin of covering part and
Side wall, the first gate electrode layer 232 are located at the surface of the first gate dielectric layer 231.Second gate dielectric layer 234 is located at isolation
210 surface of structure, 221 top surface of the second fin of covering part and side wall, second gate electrode layer 235 are located at second gate Jie
The surface of matter layer 234.
In the present embodiment, the material of the first gate dielectric layer 231 and the second gate dielectric layer 234 is silica, first gate electrode
The material of layer 232 and the second gate electrode layer 235 is polysilicon.In other embodiments, the first gate dielectric layer 231 and second gate are situated between
The material of matter layer 234 is high K dielectric material (K is greater than 3.9), such as HfO2、HfSiON、HfAlO2、ZrO2Or Al2O3, first grid electricity
Pole layer 232 and second gate electrode layer 235 material be metal material, as Al, Cu, Ag, Au, Pt, Ni, Ti, TiN, Ta, TaN, W,
WN or WSi.
The method for forming first grid structure 230 and second grid structure 233 are as follows: the formation covering isolation structure 210,
The gate dielectric material layer of first fin 220 and the second fin 221；Gate material is formed in the gate dielectric material layer surface
Layer；It is formed patterned mask layer (not shown) in the gate material layer surface, the patterned mask layer defines shape
At first grid structure 230 and second grid structure 233 position；Using the patterned mask layer as exposure mask, use
Etching technics etches the gate dielectric material layer and layer of gate electrode material, forms first grid structure 230 and second grid structure
233.230 exposed at both sides of first grid structure goes out the first fin of part 220,233 exposed at both sides of second grid structure
The second fin of part 221 out.
It should be noted that can not be gone during forming first grid structure 230 and second grid structure 233
The mask layer for falling to define 233 position of first grid structure 230 and second grid structure, in first grid structure 230 and second gate
Structure 233 top surface in pole retains the mask layer (not shown), in the mistake for being subsequently formed the first source-drain area and the second source-drain area
It can protect first grid structure 230 and second grid structure 233 in journey.
200 surface of semiconductor substrate also has isolation structure 210, and the surface of isolation structure 210 is lower than 220 He of the first fin
The top surface of second fin 221, isolation structure 210 are used for the first fin of electric isolation 220, and the second fin of electric isolation
221。
First fin 220 and the second fin 221 can also adulterate different foreign ions, for adjusting fin field effect
Answer the threshold voltage of transistor.The doped N-type ion in first fin 220 in p type island region domain (region I), in the n-type region (area II
Domain) the second fin 221 in doped p-type ion.
In conjunction with reference Fig. 8 and Fig. 9, the first offset side wall 240 is formed in 230 two sides sidewall surfaces of first grid structure,
233 two sides sidewall surfaces of second grid structure form the second offset side wall 241.
The method for forming the first offset side wall 240 and the second offset side wall 241 are as follows: in p type island region domain (region I) and N-type region
Domain (region II) deposits offset side wall material layer, using anisotropic dry etch process etch bias spacer material layer, the
One gate structure, 230 two sides sidewall surfaces form the first offset side wall 240, while in 233 two sides side wall table of second grid structure
Face forms the second offset side wall 241.
First offset side wall 240 protects first grid structure 230, and second offset side wall 241 protects second gate
Pole structure 233.
The material of first offset side wall 240 and the second offset side wall 241 includes silicon nitride, silica or silicon oxynitride etc.
Insulating materials.The material of the first offset side wall 240 and the second offset side wall 241 is silicon nitride in the present embodiment.
The second offset side wall 233 is formed while it should be noted that forming the first offset side wall 240, work can be simplified
Skill.In other embodiments, 233 two sides sidewall surfaces of second grid structure can not form the second offset side wall 241, only the
One gate structure, 230 two sides sidewall surfaces form the first offset side wall 240.
In conjunction with reference Fig. 8 to Figure 10, first is carried out to the first fin 220 of 230 two sides of first grid structure, note is lightly doped
Enter, forms the first lightly doped district 250.
First lightly doped district 250 is located in the first fin 220 of 230 two sides of first grid structure, the first lightly doped district 250
Positioned at the side and top of the first fin 220.
The top of first fin 220 refers to the region in the first fin 220 close to 220 top surface of the first fin,
In the top o'clock to 220 top surface of the first fin distance be less than or equal to half the first fin 220 thickness；
The side of first fin 220 refers to the region in the first fin 220 close to 220 sidewall surfaces of the first fin, the side
In o'clock to 220 sidewall surfaces of the first fin distance be less than or equal to half 220 thickness of the first fin.First fin
220 with a thickness of the size for being parallel to 230 extending direction of first grid structure.
The first mask layer (not shown) for forming covering n-type region (region II), is covered with the first of n-type region (region II)
Film layer, first grid structure 230, the first offset side wall 240 are first fin 220 of the exposure mask to 230 two sides of first grid structure
It carries out first injection being lightly doped, forms the first lightly doped district 250 in p type island region domain (region I), the first lightly doped district 250 is positioned at the
The top and side of one fin 220.
First mask layer selects photoresist.
In the present embodiment, first the ion for injecting and using is lightly doped as B, Implantation Energy range is 1KeV~5KeV, note
Entering dosage range is 1E14atom/cm2~2E15atom/cm2, implant angle is 0 degree~20 degree.
First lightly doped district 250 reduces heat for reducing the transverse electric field intensity for the first source-drain area being subsequently formed
Carrier effect.
After described first is lightly doped injection, the ion of injection can be made annealing treatment, activation Doped ions and
Eliminate implantation defect.It can also be made annealing treatment together after being subsequently formed the first source-drain area and the second source-drain area.
Fin formula field effect transistor progress first is lightly doped the ion used during injecting as B ion, and it is subsequent
The ion adulterated in the second lightly doped district formed is that the relative atomic mass of P or As, P or As are larger, if infused using ion
The mode entered forms the second lightly doped district in the fin, can generate biggish implant damage, that is, second formed to the second fin
There are biggish implant damages in lightly doped district, and the implant damage is also difficult to be repaired during subsequent anneal.For
It avoids forming the second lightly doped district in the second fin by the way of ion implanting, so that the second lightly doped district formed is not
There are implant damages, will not immediately form the second lightly doped district after injection is lightly doped first, but subsequent in second gate
Pole structure two sides form lesser second side wall of thickness, so that between the second source-drain area being subsequently formed and second grid structure
Distance reduces, and since the thickness of the second side wall is smaller, the second ion adulterated in the second source-drain area for being subsequently formed can pass through
It is diffused in the second fin of second grid structure two sides and forms the second lightly doped district.
In conjunction with reference to figures 11 to Figure 13, first side wall in covering p type island region domain (region I) and n-type region (region II) is formed
Material layer 242；The first barrier layer 243 of covering n-type region (region II) is formed, the first barrier layer 243 is located at n-type region (II
Region) 242 surface of the first spacer material layer.
The material on first barrier layer 243 is photoresist.
The material of the first spacer material layer 242 includes silicon nitride, the insulating materials such as silica or silicon oxynitride.This
In embodiment, the material of the first spacer material layer 242 is silicon nitride.
First spacer material is deposited such as plasma enhanced chemical vapor deposition or atomic layer deposition using depositing operation
Layer 242, the first spacer material layer 242 covers entire p type island region domain (region I) and n-type region (region II).
It is formed after the first spacer material layer 242, in the 242 surface shape of the first spacer material layer of n-type region (region II)
At the first barrier layer 243.
Mask layer of first barrier layer 243 as the first spacer material layer 242 in subsequent etching p type island region domain (region I), makes
The first spacer material layer 242 of n-type region (region II) during being subsequently formed the first side wall is obtained to be not etched.
In conjunction with reference Figure 14 and Figure 15, the first spacer material layer 242 for etching p type island region domain (region I) (refers to Figure 11 and figure
13), 240 sidewall surfaces of the first offset side wall in 230 two sides of p type island region domain (region I) first grid structure form the first side wall
244。
With the first barrier layer 243 (referring to Figure 12 and Figure 13) for exposure mask, p-type is etched using anisotropic dry etch process
The first spacer material layer 242 in region (region I), first in 230 two sides of first grid structure in p type island region domain (region I) are inclined
It moves 240 sidewall surfaces of side wall and forms the first side wall 244.
First side wall 244 with a thickness of 25nm~40nm.
It should be noted that the technological parameter of adjustable etching, so that in p type island region domain (region I), in addition to first grid
Part the first spacer material layer 242 of 230 two sides of structure retains to form the first side wall 244, the first side wall at remaining position
Material layer 242 is etched removal.The first fin 220 in 230 two sides of p type island region domain (region I) first grid structure is complete
It is exposed (with reference to Figure 15), subsequent 220 surface of the first fin in p type island region domain (region I) exposure forms the first source-drain area, the
Material in one source-drain area has stress, and the stress in the material of the first source-drain area can preferably be applied to first grid structure
In the channel of 230 bottoms.
First side wall 244 protects first grid structure 230 and defines the first source-drain area being subsequently formed and the first grid
The distance between pole structure 230, and define the width of the first lightly doped district 250 of the first side wall 244 covering.The width refers to
Be size along 220 extending direction of the first fin.
In conjunction with reference Figure 16 and Figure 17, the first source and drain is formed on 220 surface of the first fin of 230 two sides of first grid structure
Area 260, side wall of first source-drain area 260 close to the first side wall 244.
The method for forming the first source-drain area 260 are as follows: first grid structure is removed for mask etching with the first barrier layer 243
The first fin of part 220 of 230 two sides, so that the height of the first fin 220 reduces；Removal covering n-type region (region II)
First barrier layer 243；220 surface epitaxial growth the first source-drain area material layer of the first fin after etching；To the first source-drain area
Material layer adulterates the first ion.
In one embodiment, the first ion is adulterated in situ while the first source-drain area material layer described in epitaxial growth.
In another embodiment, the first ion implanting is carried out after one source-drain area material layer of extension growth regulation,
The first ion is adulterated in one source-drain area material layer.
The material of the first source-drain area material layer is SiGe.
First ion is P-type ion, such as B or In.
The side wall of first source-drain area 260 close to the first side wall 244 refers to the sidewall surfaces and first of the first source-drain area 260
Minimum range between the sidewall surfaces of side wall 244 is zero.
In conjunction with referring to figs. 18 to Figure 20, covering p type island region domain (region I) second barrier layer 245 is formed, with the second barrier layer
245 be exposure mask, and the first spacer material layer 242 (referring to Figure 12 and Figure 17) of etching removal n-type region (region II) and first is partially
Move side wall 241 (referring to Figure 12).
The material on second barrier layer 245 is photoresist.
Second barrier layer 245 is as the first spacer material layer 242 of etching removal n-type region (region II) and the first offset
The mask layer of side wall 241 protects p type island region domain (region I) not by the influence etched.
The first spacer material layer 242 and the first offset side wall 241 in n-type region (region II) are removed using dry etching,
Specific technological parameter are as follows: the gas of use includes CH3F and O2, CH3The flow of F is 50sccm~350sccm, O2Flow be
10sccm~40sccm, RF source power are 100 watts~500 watts, bias voltage 100V~500V, and etching cavity pressure is
40mtorr~250mtorr.
After the first spacer material layer 242 and the first offset side wall 241 that remove n-type region (region II), the second resistance
Barrier 245 is removed by cineration technics, and subsequent 233 two sides of second grid structure in n-type region (region II) form relatively thin
Second side wall.
It should be noted that in the present embodiment, in order to simplify technique, by first spacer material in n-type region (region II)
Layer 242 and the first offset side wall 241 remove together.It in other embodiments, can also be only by n-type region (region II) the first side
The walling bed of material 242 removes.
With reference to figures 21 to Figure 23, second spacer material in covering p type island region domain (region I) and n-type region (region II) is formed
Layer 246；The third barrier layer 247 of covering p type island region domain (region I) is formed, third barrier layer 247 is located at p type island region domain (region I)
The surface of second side walling bed of material 246.
The material of second side walling bed of material 246 includes silicon nitride, the insulating materials such as silica or silicon oxynitride.This implementation
In example, the material of second side walling bed of material 246 is silicon nitride.
Second spacer material is formed such as plasma enhanced chemical vapor deposition or atomic layer deposition using depositing operation
Layer 246, second side walling bed of material 246 covers entire p type island region domain (region I) and n-type region (region II).
It is formed after second side walling bed of material 246, the 246 surface shape of second side walling bed of material in p type island region domain (region II)
At third barrier layer 247.
The material on the third barrier layer 247 is photoresist.
Mask layer of the third barrier layer 247 as second side walling bed of material 246 of subsequent etching n-type region (region II),
So that second side walling bed of material 246 in p type island region domain (region I) is not etched during being subsequently formed the second side wall.
In conjunction with reference Figure 24 and Figure 25, second side walling bed of material 246 in n-type region (region II) is etched, in n-type region
The 233 two sides sidewall surfaces of second grid structure in (region II) form the second side wall 248,248 covering part of the second side wall
Second fin 221, the thickness of the thickness of second side wall 248 less than the first side wall 244.
It is exposure mask with third barrier layer 247, using the of anisotropic dry etch process etching n-type region (region II)
Two spacer material layers 246 form the second side wall in the 233 two sides sidewall surfaces of second grid structure of n-type region (region II)
248, specific technological parameter are as follows: the gas of use includes CH3F and O2, CH3The flow of F is 50sccm~350sccm, O2Stream
Amount is 10sccm~40sccm, and RF source power is 100 watts~500 watts, bias voltage 100V~500V, and etching cavity pressure is
40mtorr~250mtorr.
It should be noted that the technological parameter of adjustable etching, so that in n-type region (region II), second grid knot
233 two sides of structure retain part second side walling bed of material 246 to form the second side wall 248, meanwhile, in 221 two sides side of the second fin
Wall retains part second side walling bed of material 246 to form the second fin side wall 249, the second fin in 221 two sides side wall of the second fin
Portion's side wall 249 is lower than the top surface of the second fin 221.It in other embodiments, can also be by n-type region (region II) second
Second side walling bed of material 246 on 221 surface of fin all removals, by 233 two sides of n-type region (region II) second grid structure
Second fin 221 is fully exposed.
Second side wall 248 protects second grid structure 233 and defines the second source-drain area and second gate being subsequently formed
The distance between pole structure 233, and define the width of the second fin 221 of the second side wall 248 covering.The width refers to
Along the size of 221 extending direction of the second fin.
The thickness of second side wall 248 less than the first side wall 244 thickness so that the of the covering of the second side wall 248
The region of two fins 221 reduces, so that second grid structure 233 and the distance between the second source-drain area being subsequently formed subtract
It is small.
In the present embodiment, second side wall 248 with a thickness of 10nm~20nm.
Due to eliminating the first spacer material layer 242 of n-type region before forming the second side wall 248, then second
233 two sides sidewall surfaces of gate structure form lesser second side wall 248 of thickness, so that the thickness of the second side wall 248 is less than the
The thickness of one side wall 244, so that the distance between second grid structure 233 and the second source-drain area being subsequently formed reduce, due to
The thickness of second side wall 248 is smaller, and the second ion adulterated in the second source-drain area being subsequently formed can diffuse into second side
In the second fin 221 that wall 248 covers, second is formed in the second fin 221 of 233 two sides of second grid structure and is lightly doped
Area.It avoids forming the second lightly doped district by the way of ion implanting, so as to avoid existing in the second lightly doped district of formation
Implant damage, to improve the performance of fin formula field effect transistor to be formed.
It should be noted that lesser second side wall 248 of formation thickness, which uses, is initially formed covering p type island region in the present embodiment
The second barrier layer 245 of domain (region I), is exposure mask with the second barrier layer 245, the first side of etching removal n-type region (region II)
The walling bed of material 242 and the second offset side wall 241；Then the of covering p type island region domain (region I) and n-type region (region II) is formed
Two spacer material layers 246 form the third barrier layer 247 on covering 246 surface of p type island region domain (region I) second side walling bed of material；With
Third barrier layer 247 is that exposure mask uses anisotropic etch process to etch second side walling bed of material 246, in the n-type region (area II
Domain) second grid structure 233 two sides formed the second side wall 248, the thickness of second side wall 248 is less than the first side wall 244
Thickness.Lesser second side wall 248 of thickness can be formed using the above method, in addition, forming lesser second side wall of thickness
When 248, the damage etched to the second fin 221 is reduced, and the second side wall 248 formed will not expose second grid structure
233 partial sidewall.
In another embodiment, it is initially formed second side wall in covering p type island region domain (region I) and n-type region (region II)
Material layer；Form the second barrier layer of covering p type island region domain (region I)；Then anisotropy is used by exposure mask of the second barrier layer
Etching technics etches the first spacer material layer and second side walling bed of material in n-type region (region II), due to the first spacer material
The overall thickness of layer and second side walling bed of material is thicker, it is difficult to form the second relatively thin side wall, reason is: if to be formed the
Two side wall thicknesses are relatively thin, need to increase the etching degree to the first spacer material layer and second side walling bed of material, cause to second
The etching injury of fin, and expose the partial sidewall of second grid structure.
In conjunction with reference Figure 26 to Figure 28, the second source and drain is formed on 221 surface of the second fin of 233 two sides of second grid structure
Area 261, second source-drain area 261 close to the second side wall 248 side wall, doped with the second ion in the second source-drain area 261, and
So that the second ion diffuses into the second fin 221 of the second side wall 248 covering, the second lightly doped district 251 is formed.
Second lightly doped district 251 is located in the second fin 221 of 233 two sides of second grid structure, and second is lightly doped
Area 251 is located at the side and top of the second fin 221, and second side wall 248 covers the second lightly doped district 251.
The top of second fin 221 refers to the region in the second fin 221 close to 221 top surface of the second fin,
In the top o'clock to 221 top surface of the second fin distance be less than etc. halfs 221 thickness of the second fin area
Domain；The side of second fin 221 refers to the region in the second fin 221 close to 221 sidewall surfaces of the second fin, the side
In portion o'clock to 221 sidewall surfaces of the second fin distance be less than or equal to half 221 thickness of the second fin region.
Second fin 221 with a thickness of the size for being parallel to 233 extending direction of second grid structure.
The method for forming the second source-drain area 261 are as follows: with third barrier layer 247 (referring to Figure 25) for mask etching second grid
The second fin of part 221 of 233 two sides of structure, so that 221 height of the second fin and the second fin side wall 249 after etching are neat
It is flat；The third barrier layer 247 of removal covering p type island region domain (region I)；221 surface epitaxial growth of the second fin after etching
Two source-drain area material layers；Second ion is adulterated to the second source-drain area material layer.
In one embodiment, the second ion is adulterated in situ while the second source-drain area material layer described in epitaxial growth.
In another embodiment, the second ion implanting is carried out after two source-drain area material layer of extension growth regulation,
The second ion is adulterated in two source-drain area material layers.
The material of the second source-drain area material layer is silicon carbide.
Second ion is N-type ion, such as P or As.
The side wall of second source-drain area 261 close to the second side wall 248 refers to the sidewall surfaces and second of the second source-drain area 261
Minimum range between the sidewall surfaces of side wall 248 is zero.
Due to the second side wall 248 thickness less than the first side wall 244 thickness so that the second source-drain area 261 and second gate
The distance between pole structure 233 reduces, and the second ion adulterated in the second source-drain area 261 can diffuse into the second side wall 248
In second fin 221 of covering, 221 form the second lightly doped district 251 in the second fin of 233 two sides of second grid structure,
Second lightly doped district 251 is located at the top and side of the second fin 221 of 233 two sides of second grid structure, and described second
Side wall 248 covers the second lightly doped district 251.It avoids forming the second lightly doped district 251 by the way of ion implanting, to avoid
There are implant damages in second lightly doped district 251, so that the performance of fin formula field effect transistor improves.
After forming the second source-drain area 261, made annealing treatment.
It should be noted that being also distributed in the second fin 221 of 261 bottom of the second source-drain area after the diffusion of the second ion
Second ion, it is not shown.
It should be noted that when without forming the second fin side wall 249, the second fin of 233 two sides of second grid structure
The side wall of 221 bottoms can be exposed, and form the method for the second source-drain area 261 at this time are as follows: with third barrier layer 247 (with reference to figure
It 25) is the second fin of part 221 of 233 two sides of mask etching second grid structure, so that the height of the second fin 221 reduces；
The third barrier layer 247 of removal covering p type island region domain (region I)；221 the second source of surface epitaxial growth of the second fin after etching
Drain region material layer；Second ion is adulterated to the second source-drain area material layer.
The second ion is adulterated while the second source-drain area material layer described in epitaxial growth in situ, or in extension growth regulation
The second ion implanting is carried out after two source-drain area material layers, adulterates the second ion in the second source-drain area material layer.
Due to not forming the second fin side wall 249, so that 221 bottom of the second fin of 233 two sides of second grid structure
Side wall be exposed, then the second fin 221 surface formed the second source-drain area 261 so that in the second source-drain area 261
Second ion can adequately be diffused into the bottom section of the second fin 221, form the second lightly doped district 251, second is lightly doped
Area 251 is located at the top and side of the second fin 221 of 233 two sides of second grid structure, the covering of the second side wall 248 second
Lightly doped district 251, the second ion distribution in the second lightly doped district 251 are more uniform.
After forming the second source-drain area 261, made annealing treatment.
In order to reduce concentration gradient of second ion in the second lightly doped district 251, so that the second ion is gently mixed second
It is evenly distributed in miscellaneous area 251, needs to increase the second ion in the second lightly doped district 251 of 221 bottom section of the second fin
Doping concentration, the forming method of the fin formula field effect transistor further include: using third ion implanting under the second source-drain area
Third ion is injected in second fin in portion, forms third source-drain area, and third ion is made to diffuse into the second lightly doped district；
Second ion and the second ion are identical.
The lower part of second source-drain area 261 refers to being located at other than the second source-drain area 261 close to 261 bottom of the second source-drain area
The region on portion surface o'clock is less than or equal to the of half to the distance of 261 bottom surface of the second source-drain area in the lower part
The region of two source-drain areas, 261 height.The height is referred to along the size perpendicular to 200 direction of semiconductor substrate.
With reference to Figure 29 and Figure 30, injected in the second fin 221 of 261 lower part of the second source-drain area using third ion implanting
Third ion forms third source-drain area 271, and third ion is made to diffuse into the second lightly doped district 251, the third ion
It is identical with the second ion.
In one embodiment, the ion that the third ion implanting uses for P ion, Implantation Energy range be 1KeV~
8KeV, implantation dosage range are 2E14atom/cm2~2E15atom/cm2, implant angle is 0 degree~10 degree.
In another embodiment, for As ion, Implantation Energy range is the ion that the third ion implanting uses
2KeV~10KeV, implantation dosage range are 2E14atom/cm2~2E15atom/cm2, implant angle is 0 degree~10 degree.
Depth of the third source-drain area 271 in the second fin 221 is 30nm~60nm.
Due to the injection third ion in the second fin 221 of 261 lower part of the second source-drain area, third source-drain area 271 is formed,
The third ion and the second ion are identical, and the third ion in third source-drain area 271 can diffuse into the second lightly doped district
251, especially third ion can diffuse into the second lightly doped district 251 in 221 bottom section of the second fin, and third from
Son is identical with the second ion, so that the concentration gradient for the second ion being distributed in the second lightly doped district 251 reduces, the second ion exists
Distribution in second lightly doped district 251 is more uniform.
The invention has the following advantages that
The forming method of fin formula field effect transistor provided by the invention, in the fin field with p type island region domain and n-type region
In effect transistor, after carrying out the first lightly doped district injection, injection is lightly doped without and then carrying out second, but first
Gate structure two sides sidewall surfaces form the first side wall；The first fin portion surface in first grid structure two sides forms the first source and drain
Area, side wall of first source-drain area close to the first side wall；The second side wall, second side are formed in second grid structure two sides sidewall surfaces
Thickness of the thickness of wall less than the first side wall, second the second fin of side wall covering part；The second of second grid structure two sides
Fin portion surface forms the second source-drain area, the second source-drain area close to the second side wall side wall, in the second source-drain area doped with second from
Son, and the second ion is diffused into the second fin of the second side wall covering, form the second lightly doped district.Due to described
The thickness of two side walls is smaller, and the distance between the second source-drain area and second grid structure are smaller, so the second of the second source-drain area
Ion can form the second lightly doped district in the second fin by being diffused in second grid structure two sides.So as to avoid use
The mode of ion implanting forms the second lightly doped district, and avoiding the second lightly doped district, there are implant damages, improves fin field effect
Answer the performance of transistor.
Further, third ion is injected in the second fin of the second source-drain area lower part, forms third source-drain area, it is described
Third ion and the second ion are identical, and the third ion in third source-drain area can diffuse into the second lightly doped district, especially
Third ion can diffuse into the second lightly doped district in the second fin bottom section, so that being distributed in the second lightly doped district
The second ion concentration gradient reduce, the second ion is distributed more uniform in the second lightly doped district.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (19)
1. a kind of forming method of fin formula field effect transistor characterized by comprising
Semiconductor substrate is provided, semiconductor substrate has p type island region domain and n-type region, and the semiconductor substrate surface in p type island region domain has
First fin and first grid structure across the first fin, the top surface of first grid structure the first fin of covering part and
The semiconductor substrate surface of side wall, n-type region has the second fin and the second grid structure across the second fin, second grid
The top surface and side wall of the second fin of structure covering part；
First is carried out to the first fin of first grid structure two sides, injection is lightly doped, forms the first lightly doped district；
First is lightly doped after injection, forms the first side wall, the first side wall covering part in first grid structure two sides sidewall surfaces
Divide the first lightly doped district；
The first fin portion surface in first grid structure two sides forms the first source-drain area, and the first source-drain area is close to the side of the first side wall
Wall；
Form the second side wall in second grid structure two sides sidewall surfaces, the thickness of the second side wall less than the first side wall thickness,
Second the second fin of side wall covering part；
The second fin portion surface in second grid structure two sides forms the second source-drain area, and the second source-drain area is close to the side of the second side wall
Wall doped with the second ion in the second source-drain area, and diffuses into the second ion in the second fin of the second side wall covering,
Form the second lightly doped district；
Second side wall with a thickness of 10nm~20nm.
2. the forming method of fin formula field effect transistor according to claim 1, which is characterized in that infused using third ion
Enter the injection third ion in the second fin of the second source-drain area lower part, form third source-drain area, and third ion is spread
Into the second lightly doped district；The third ion and the second ion are identical.
3. the forming method of fin formula field effect transistor according to claim 2, which is characterized in that the third ion note
Enter the ion used for P ion, Implantation Energy range is 1KeV~8KeV, and implantation dosage range is 2E14atom/cm2~
2E15atom/cm2, implant angle is 0 degree~10 degree.
4. the forming method of fin formula field effect transistor according to claim 2, which is characterized in that third ion implanting is adopted
Ion is As ion, and Implantation Energy range is 2KeV~10KeV, and implantation dosage range is 2E14atom/cm2~
2E15atom/cm2, implant angle is 0 degree~10 degree.
5. the forming method of fin formula field effect transistor according to claim 2, which is characterized in that the third source-drain area
Depth in the second fin is 30nm~60nm.
6. the forming method of fin formula field effect transistor according to claim 1, which is characterized in that form first side
The method of wall are as follows: form the first spacer material layer in covering p type island region domain and n-type region；Form covering n-type region first stops
Layer, first barrier layer is located at the first spacer material layer surface of n-type region；Using the first barrier layer as mask etching p type island region
The first spacer material layer in domain forms the first side wall in the first grid structure two sides in p type island region domain.
7. the forming method of fin formula field effect transistor according to claim 6, which is characterized in that form the first source-drain area
Method include: using the first barrier layer as mask etching remove first grid structure two sides the first fin of part so that first
The height of fin reduces；Remove the first barrier layer；First fin portion surface epitaxial growth the first source-drain area material layer after etching；
First ion is adulterated to the first source-drain area material layer.
8. the forming method of fin formula field effect transistor according to claim 7, which is characterized in that described in epitaxial growth
The first ion is adulterated while first source-drain area material layer in situ.
9. the forming method of fin formula field effect transistor according to claim 7, which is characterized in that form described second side
The method of wall are as follows: remove the first spacer material layer of n-type region；Form second spacer material in covering p type island region domain and n-type region
Layer；The third barrier layer in covering p type island region domain is formed, third barrier layer is located at the surface of second side walling bed of material in p type island region domain；With
Third barrier layer is second side walling bed of material of mask etching n-type region, forms the in the second grid structure two sides of n-type region
Two side walls.
10. the forming method of fin formula field effect transistor according to claim 9, which is characterized in that form the second source and drain
The method in area includes: the second fin of part that second grid structure two sides are removed using third barrier layer as mask etching, so that the
The height of two fins reduces；Remove third barrier layer；Second fin portion surface epitaxial growth the second source-drain area material after etching
Layer；Second ion is adulterated to the second source-drain area material layer.
11. the forming method of fin formula field effect transistor according to claim 10, which is characterized in that in epitaxial growth institute
The second ion is adulterated while stating the second source-drain area material layer in situ.
12. according to claim 1 or the forming method of fin formula field effect transistor described in 10, which is characterized in that described second
Ion is N-type ion.
13. the forming method of fin formula field effect transistor according to claim 12, which is characterized in that the N-type ion
For P or As.
14. the forming method of fin formula field effect transistor according to claim 1, which is characterized in that first side wall
With a thickness of 25nm~40nm.
15. the forming method of fin formula field effect transistor according to claim 1, which is characterized in that first side wall
Material be silicon nitride.
16. the forming method of fin formula field effect transistor according to claim 1, which is characterized in that second side wall
Material be silicon nitride.
17. the forming method of fin formula field effect transistor according to claim 1, which is characterized in that described first gently mixes
Pragma enters the ion used for B ion, and Implantation Energy range is 1KeV~5KeV, and implantation dosage range is 1E14atom/cm2~
2E15atom/cm2, implant angle is 0 degree~20 degree.
18. the forming method of fin formula field effect transistor according to claim 1, which is characterized in that first source and drain
Doped with P-type ion in area.
19. the forming method of fin formula field effect transistor according to claim 1, which is characterized in that the first grid
Structure includes the first gate dielectric layer across the first fin and the first gate electrode layer positioned at first grid dielectric layer surface；Described
Two gate structures include the second gate dielectric layer across the second fin and the second gate electrode layer positioned at second gate dielectric layer surface.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5756383A (en) * | 1996-12-23 | 1998-05-26 | Advanced Micro Devices | Method of manufacturing an active region of a semiconductor by diffusing a counterdopant out of a sidewall spacer |
| US5776806A (en) * | 1995-07-17 | 1998-07-07 | Micron Technology, Inc. | Method of forming CMOS integrated circuitry having halo regions |
| CN1385895A (en) * | 2002-06-20 | 2002-12-18 | 上海华虹（集团）有限公司 | Deep submicrometer CMOS channel and source drain making technology integrating method |
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2015
- 2015-07-01 CN CN201510377770.2A patent/CN106328531B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5776806A (en) * | 1995-07-17 | 1998-07-07 | Micron Technology, Inc. | Method of forming CMOS integrated circuitry having halo regions |
| US5756383A (en) * | 1996-12-23 | 1998-05-26 | Advanced Micro Devices | Method of manufacturing an active region of a semiconductor by diffusing a counterdopant out of a sidewall spacer |
| CN1385895A (en) * | 2002-06-20 | 2002-12-18 | 上海华虹（集团）有限公司 | Deep submicrometer CMOS channel and source drain making technology integrating method |
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