CN106783545A - A kind of adjusting method of flat board epitaxial furnace thermal field - Google Patents
A kind of adjusting method of flat board epitaxial furnace thermal field Download PDFInfo
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- CN106783545A CN106783545A CN201611216992.7A CN201611216992A CN106783545A CN 106783545 A CN106783545 A CN 106783545A CN 201611216992 A CN201611216992 A CN 201611216992A CN 106783545 A CN106783545 A CN 106783545A
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- temperature
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- square resistance
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
Abstract
The invention discloses a kind of adjusting method of improved 8 cun of flat boards epitaxial furnace thermal field, inject N-type impurity ion with ion implantation and be prepared into injection piece, the N-type impurity ion in the injection piece is activated at high temperature, so that surface forms P N knots.The timing of time one, the amount that N-type impurity ion is activated is directly proportional to temperature, the square resistance of the injection piece after being toasted under testing different temperatures, obtain the linear relationship of temperature and square resistance, based on this, the square resistance for injecting multiple spot in piece piece after measuring baking, obtains thermal field distribution situation, instruct thermal field to adjust, the thermal field distribution situation in extension furnace cavity can be quickly obtained.
Description
Technical field
Manufacture field the present invention relates to belong to semiconductor epitaxial wafer, the especially adjusting method of flat board epitaxial furnace thermal field.
Background technology
With the continuous increase of extension chip size, the influence of more easy thermally stressed effect causes defect in piece to increase,
And 8 cun of extension products propose requirement higher to uniformity in piece, these are directly limited by the heterogeneity phantom of reaction chamber, because
This, the heterogeneity phantom to epitaxial furnace reaction chamber proposes more harsh requirement.
The heterogeneity phantom of 8 cun of flat board epitaxial furnaces is by extension stokehold portion (Front), sidepiece (Side), rear portion
(Rear) regulation of trizonal temperature-compensating is realized, so as to obtain the more uniform thermal field of epitaxial growth, such as Fig. 1 institutes
Show.During thermal field regulation, the compensation to reaction chamber (tri- regions of Front, Side, Rear and separate) temperature is divided into
Positive compensation or negative compensation, and in specific operation process, to different zones using which kind of compensation, specific offset be it is how many,
Method differs.
Prior art often instructs thermal field to adjust with skid wire observation method, i.e., to tri- region difference of Front, Side, Rear
Using a certain setting value, in middle resistance one layer of epitaxial layer of Grown, by observing the distribution situation of skid wire, determine using just
Compensation or the value of negative compensation and specific compensation, by continuously attempting to, make heterogeneity phantom tend to uniform.Skid wire observation method
The disadvantage is that, need repeatedly to attempt, not only time-consuming consumed the raw material such as substrate, and debugging cost is higher again.
Accordingly, it would be desirable to a kind of new technical scheme is solving the above problems.
The content of the invention
For problems of the prior art, the present invention proposes a kind of adjusting method of flat board epitaxial furnace thermal field, can
The thermal field distribution situation in extension furnace cavity is quickly obtained, compared to prior art, wafer (injection piece raw material) has been saved
Usage amount, and thermal field regulating time can be shortened.
To reach above-mentioned purpose, the present invention can be adopted the following technical scheme that：
A kind of adjusting method of flat board epitaxial furnace thermal field, comprises the following steps：
(1), the injection piece processed by ion implantation is toasted in furnace chamber, now there is initial temperature in furnace chamber
Degree offset；
(2) baked injection piece, is removed into surface oxide layer with wet method；
(3) square resistance on piece surface, is injected with four probe tests, using temperature as abscissa, square resistance is used as vertical
Coordinate, the square resistance of the injection piece central point toasted under test different temperatures, carries out linear fit, linear fit index R2For
0.9933, so as to obtain the corresponding relation between square resistance and temperature；
(4), four probe tests obtain the square resistance distribution situation of multiple spot in piece；
(5), according to the square resistance distribution situation that multiple spot in piece is injected in step (4), each region is obtained compared to center
The square resistance difference of point, according to temperature and the conversion relation of square resistance, obtains temperature deviation of each region compared to central point
Relation, so as to the actual temperature for obtaining each region is distributed；
(6), according to the actual temperature distribution obtained in step (5), it is modified on the basis of initial temperature compensation value,
Obtain one group of ideal temperature offset.
Beneficial effect：Relative to prior art, the adjusting method of flat board epitaxial furnace thermal field of the present invention is by testing not equality of temperature
The square resistance of the injection piece after the lower baking of degree, obtains the linear relationship of temperature and square resistance, based on this, by measuring
The square resistance of multiple spot, obtains thermal field distribution situation in injection piece piece after baking, instructs thermal field to adjust, and can be quickly obtained
Thermal field distribution situation in extension furnace cavity, compared to prior art, has saved wafer usage amount, and substantially reduce thermal field tune
The section time.
Preferably, the baking method for injecting piece is comprised the following steps in the step (1)：
(1.1) furnace chamber, is warmed up to 1180 DEG C；
(1.2) HCL treatment furnace chambers, are passed through；
(1.3) furnace chamber, is cooled to 850 DEG C；
(1.4) graphite base that piece loads in furnace chamber will, be injected；
(1.5), rising to cavity temperature has above-mentioned initial temperature offset in temperature needed for extension product, furnace chamber；
(1.6) doped source and silicon source, are not passed through in furnace chamber, and are kept for a set time；
(1.7), furnace chamber cooling；
(1.8), the injection piece in furnace chamber is taken out and completes extension.
Also, in above step (1.1) to step (1.8), graphite base does not rotate.
Preferably, in step (1.6), the set time is 60s.
Preferably, the initial temperature offset is specifically, the anterior temperature compensation value of epitaxial furnace is -15, sidepiece temperature
Offset is that -25, rear part temperature offset is -40.
Preferably, in step (5), the conversion relation of temperature and square resistance is 1 Ω/mouth=1.52 DEG C.
Preferably, in step (4), the square resistance test of multiple spot is 41 points in piece.
Preferably, the temperature deviation is：The anterior temperature deviation of epitaxial furnace is that the sidepiece temperature deviation of 7, epitaxial furnace is
0th, the rear part temperature deviation of epitaxial furnace is -8, and temperature deviation is subtracted with initial temperature offset, obtains one group of preferable temperature and mends
Repay value：The rear portion of the sidepiece ideal temperature offset -25, epitaxial furnace of the anterior ideal temperature offset -22, epitaxial furnace of epitaxial furnace
Ideal temperature offset -32.
Preferably, this method is applied to 8 inches of manufactures of epitaxial wafer.
Brief description of the drawings
Fig. 1 for model be ASM E2000 epitaxial furnace front portion (Front), epitaxial furnace sidepiece (Side), epitaxial furnace rear portion
(Rear) region heating tube distribution.
Fig. 2 is the linear relationship of square resistance and temperature.
Fig. 3 is the square resistance distribution map for injecting multiple spot in piece.
Specific embodiment
A kind of adjusting method of improved 8 cun of flat boards epitaxial furnace thermal field is present embodiments provided, that is, uses resistance lining in 8 cun of P
Bottom (the Ω .cm of resistivity 8~12).
Refer to shown in Fig. 1 to Fig. 3, embodiments of the invention are described in detail below.
The adjusting method that the present embodiment is provided includes：
(1), injection piece is toasted in furnace chamber, now there is initial temperature offset in furnace chamber；The initial temperature
Degree offset is specifically, it is -25, rear part temperature offset that the anterior temperature compensation value of epitaxial furnace is -15, sidepiece temperature compensation value
For -40.
Baking method to injecting piece is comprised the following steps：
(1.1) furnace chamber, is warmed up to 1180 DEG C；
(1.2) HCL treatment furnace chambers, are passed through；
(1.3) furnace chamber, is cooled to 850 DEG C；
(1.4) graphite base that piece loads in furnace chamber will, be injected；
(1.5), rising to cavity temperature has above-mentioned initial temperature offset in temperature needed for extension product, furnace chamber；
(1.6) doped source and silicon source, are not passed through in furnace chamber, and are kept for a set time；
(1.7), furnace chamber cooling；
(1.8), the injection piece in furnace chamber is taken out and completes extension.
Also, in above step (1.1) to step (1.8), graphite base does not rotate.
(2) baked injection piece, is removed into surface oxide layer with wet method；
(3) square resistance on piece surface, is injected with four probe tests, using temperature as abscissa, square resistance is used as vertical
Coordinate, the square resistance of the injection piece central point toasted under test different temperatures, carries out linear fit, linear fit index R2For
0.9933, so as to obtain the corresponding relation between square resistance and temperature；1 Ω/mouth=1.52 DEG C.
(4), four probe tests obtain injecting the square resistance distribution situation of multiple spot in piece, obtain injecting 41 points in piece of side
Block distribution of resistance figure；
(5), according to the square resistance distribution situation that multiple spot in piece is injected in step (4), i.e., according to 41 points in injection piece
Square resistance distribution situation, learns front portion 10 square resistances lower than central point of epitaxial furnace, and central point is compared at the rear portion of epitaxial furnace
12 square resistances high, epitaxial furnace sidepiece and central point are considered as indifference, obtain square resistance of each region compared to central point
Difference, according to temperature and the conversion relation of square resistance, obtains temperature deviation relation of each region compared to central point：Epitaxial furnace
Anterior temperature deviation be 7, epitaxial furnace sidepiece temperature deviation be the rear part temperature deviation of 0, epitaxial furnace for -8, mended with initial temperature
Repay value and subtract temperature deviation, obtain one group of preferable temperature compensation value：The anterior ideal temperature offset -22, extension of epitaxial furnace
The rear portion ideal temperature offset -32 of the sidepiece ideal temperature offset -25, epitaxial furnace of stove.
(6), according to the actual temperature distribution obtained in step (5), it is modified on the basis of initial temperature compensation value,
Obtain one group of ideal temperature offset.
In the method, inject N-type impurity ion with ion implantation and be prepared into injection piece, the N-type in the injection piece is miscellaneous
Matter ion is activated at high temperature, so that surface forms P-N junction.Time one, regularly the amount that N-type impurity ion is activated was and temperature
Degree is directly proportional, therefore the square resistance of piece surface different zones is injected with 4 probe measurements.
The method and approach that the present invention implements the technical scheme are a lot, and the above is only of the invention being preferable to carry out
Mode.It should be pointed out that for those skilled in the art, under the premise without departing from the principles of the invention, also
Some improvements and modifications can be made, these improvements and modifications also should be regarded as protection scope of the present invention.It is unknown in the present embodiment
True each component part can use prior art to be realized.
Claims (8)
1. a kind of adjusting method of flat board epitaxial furnace thermal field, it is characterised in that comprise the following steps：
(1), injection piece is toasted in furnace chamber, now there is initial temperature offset in furnace chamber；
(2) baked injection piece, is removed into surface oxide layer with wet method；
(3) square resistance on piece surface, is injected with four probe tests, using temperature as abscissa, square resistance as ordinate,
The square resistance of the injection piece central point toasted under test different temperatures, carries out linear fit, linear fit index R2For
0.9933, so as to obtain the corresponding relation between square resistance and temperature；
(4), four probe tests obtain the square resistance distribution situation of multiple spot in piece；
(5), according to the square resistance distribution situation that multiple spot in piece is injected in step (4), each region is obtained compared to central point
Square resistance difference, according to temperature and the conversion relation of square resistance, obtains temperature deviation relation of each region compared to central point,
So as to the actual temperature for obtaining each region is distributed；
(6), according to the actual temperature distribution obtained in step (5), it is modified on the basis of initial temperature compensation value, is obtained
One group of ideal temperature offset.
2. the adjusting method of flat board epitaxial furnace thermal field according to claim 1, it is characterised in that right in the step (1)
The baking method for injecting piece is comprised the following steps：
(1.1) furnace chamber, is warmed up to 1180 DEG C；
(1.2) HCL treatment furnace chambers, are passed through；
(1.3) furnace chamber, is cooled to 850 DEG C；
(1.4) graphite base that piece loads in furnace chamber will, be injected；
(1.5), rising to cavity temperature has above-mentioned initial temperature offset in temperature needed for extension product, furnace chamber；
(1.6) doped source and silicon source, are not passed through in furnace chamber, and are kept for a set time；
(1.7), furnace chamber cooling；
(1.8), the injection piece in furnace chamber is taken out and completes extension.
Also, in above step (1.1) to step (1.8), graphite base does not rotate.
3. the adjusting method of flat board epitaxial furnace thermal field according to claim 2, it is characterised in that：It is described in step (1.6)
Set time is 60s.
4. the adjusting method of flat board epitaxial furnace thermal field according to claim 1 and 2, it is characterised in that：The initial temperature
Offset is specifically, it is -25, rear part temperature offset that the anterior temperature compensation value of epitaxial furnace is -15, sidepiece temperature compensation value
For -40.
5. the adjusting method of flat board epitaxial furnace thermal field according to claim 1 and 2, it is characterised in that：In step (5), temperature
The conversion relation of degree and square resistance is 1 Ω/mouth=1.52 DEG C.
6. the adjusting method of flat board epitaxial furnace thermal field according to claim 1, it is characterised in that：It is many in piece in step (4)
The square resistance test of point is 41 points.
7. the adjusting method of flat board epitaxial furnace thermal field according to claim 4, it is characterised in that the temperature deviation is：
The anterior temperature deviation of epitaxial furnace be 7, epitaxial furnace sidepiece temperature deviation be the rear part temperature deviation of 0, epitaxial furnace for -8, with first
Beginning temperature compensation value subtracts temperature deviation, obtains one group of preferable temperature compensation value：The anterior ideal temperature offset of epitaxial furnace-
22nd, the rear portion ideal temperature offset -32 of the sidepiece ideal temperature offset -25, epitaxial furnace of epitaxial furnace.
8. the adjusting method of flat board epitaxial furnace thermal field according to claim 1, it is characterised in that suitable for 8 inches of extensions
The manufacture of piece.
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| CN201611216992.7A CN106783545A (en) | 2016-12-26 | 2016-12-26 | A kind of adjusting method of flat board epitaxial furnace thermal field |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110957246A (en) * | 2019-12-10 | 2020-04-03 | 河北普兴电子科技股份有限公司 | Method for measuring temperature of reaction chamber of epitaxial equipment |
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| CN1489194A (en) * | 2002-10-11 | 2004-04-14 | 中芯国际集成电路制造（上海）有限公 | Control chip for daily monitoring for rapid theremal annealing process |
| CN101399163A (en) * | 2007-09-28 | 2009-04-01 | 上海华虹Nec电子有限公司 | Method for calibrating epitaxial reaction chamber temperature |
| CN102087953A (en) * | 2009-12-03 | 2011-06-08 | 无锡华润上华半导体有限公司 | Method for measuring temperature of cavity of epitaxial equipment |
| CN103605388A (en) * | 2013-10-25 | 2014-02-26 | 上海晶盟硅材料有限公司 | Method for detecting temperature of temperature field of epitaxial furnace platform through ion-implanted chip and method for correcting temperature field of epitaxial furnace platform through ion-implanted chip |
| CN104022054A (en) * | 2014-06-09 | 2014-09-03 | 上海先进半导体制造股份有限公司 | Method for monitoring temperature of epitaxial cavity |
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2016
- 2016-12-26 CN CN201611216992.7A patent/CN106783545A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1489194A (en) * | 2002-10-11 | 2004-04-14 | 中芯国际集成电路制造（上海）有限公 | Control chip for daily monitoring for rapid theremal annealing process |
| CN101399163A (en) * | 2007-09-28 | 2009-04-01 | 上海华虹Nec电子有限公司 | Method for calibrating epitaxial reaction chamber temperature |
| CN102087953A (en) * | 2009-12-03 | 2011-06-08 | 无锡华润上华半导体有限公司 | Method for measuring temperature of cavity of epitaxial equipment |
| CN103605388A (en) * | 2013-10-25 | 2014-02-26 | 上海晶盟硅材料有限公司 | Method for detecting temperature of temperature field of epitaxial furnace platform through ion-implanted chip and method for correcting temperature field of epitaxial furnace platform through ion-implanted chip |
| CN104022054A (en) * | 2014-06-09 | 2014-09-03 | 上海先进半导体制造股份有限公司 | Method for monitoring temperature of epitaxial cavity |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110957246A (en) * | 2019-12-10 | 2020-04-03 | 河北普兴电子科技股份有限公司 | Method for measuring temperature of reaction chamber of epitaxial equipment |
| CN110957246B (en) * | 2019-12-10 | 2023-07-04 | 河北普兴电子科技股份有限公司 | Method for calibrating temperature of reaction cavity of epitaxial equipment |
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