CN102479690B - Method for improving uniformity of working current on wafer during source drain annealing - Google Patents
Method for improving uniformity of working current on wafer during source drain annealing Download PDFInfo
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- CN102479690B CN102479690B CN2010105559911A CN201010555991A CN102479690B CN 102479690 B CN102479690 B CN 102479690B CN 2010105559911 A CN2010105559911 A CN 2010105559911A CN 201010555991 A CN201010555991 A CN 201010555991A CN 102479690 B CN102479690 B CN 102479690B
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Abstract
The invention provides a method for improving uniformity of working current on a wafer during source drain annealing. The method is used for measuring the working current of areas on the wafer and obtaining the working current with difference between an edge area and a central area of the wafer, so that uniform working current on the surface of the wafer is obtained by means of compensation for the temperature of the edge of the wafer. By the aid of the method, the uniformity of the working current on the wafer during source drain annealing is greatly improved.
Description
Technical field
The present invention relates to semiconductor device processing technology, a kind of inhomogeneity method of operating current when particularly on raising wafer, source-drain electrode is annealed.
Background technology
In the FEOL of manufacturing at semiconductor device, comprise the operation to the source-drain electrode annealing of semiconductor device.Particularly, after exactly Semiconductor substrate being carried out to the Implantation of source-drain electrode, the temperature of source-drain electrode is elevated to rapidly to a high temperature, then maintains source-drain electrode and fix time at this High Temperature Pre, finally source-drain electrode is lowered rapidly from this high temperature process.Can control the operating current of semiconductor device by annealing process, operating current requires that certain specification is arranged, the operating current fallen short of specifications, and its semiconductor device lost efficacy.Whether described semiconductor device lost efficacy, and whether operating current is up to specification, was to permit the testing electrical property of Acceptance Tests (WAT) to obtain through wafer.
Improve on wafer the inhomogeneity method of operating current when source-drain electrode is annealed in prior art, comprise the following steps:
Step 11, according to the dosage of source-drain electrode Implantation, the first wafer control slice is carried out to Implantation, and the described wafer control slice that carries out Implantation is annealed.Wafer control slice is the smooth wafer silicon chip that does not pass through processes.
Step 12, measure the square resistance (Rs) of the first annealed wafer control slice regional.
Usually, wafer be take its circular central and is that the center of circle draws the concentric circles of different radii, and crystal column surface is divided into a plurality of zones.The measurement of Rs is carried out repeatedly in each zone, obtains the different Rs mean values that each zone has.Theoretically, the Rs value of wafer control slice regional should be consistent, but, due to the restriction of the board that injects board and annealed itself, causes the Rs value difference of regional.
Wherein, the Rs value of regional is all to measure by measurement platform, and this is prior art, does not repeat them here.
Step 13, still according to the dosage of source-drain electrode Implantation, the second wafer control slice is carried out to Implantation, square resistance according to described the first wafer control slice regional, for obtaining the uniform square resistance of the second wafer control slice regional, adjust the annealing temperature of corresponding the second wafer control slice regional.
Wherein, adjust the annealing temperature of corresponding the second wafer control slice regional, a kind of method is to have in the annealing machine bench of different temperatures heating bulb above the second wafer control slice is placed on, rapid thermal annealing (RTP) is carried out according to different temperature in each zone, concrete annealing process is prior art, repeats no more.
In prior art, operating current uniformity when improving on wafer source-drain electrode annealing, this step is a crucial step, according to U=IR, in the situation that voltage is certain, resistance R is identical, electric current I is identical, so after obtaining the uniform square resistance of the second wafer control slice regional, just think that now the operating current uniformity is adjusted by step 13, after the second wafer control slice regional obtains uniform square resistance, when the second wafer control slice regional annealing temperature transfer on the product wafer, also can reach same effect, therefore perform step 14, carry out annealing in process according to the annealing temperature of regional on the second wafer control slice on the product wafer.The product wafer is the wafer of the device that distributed on it, finally can become finished product through multiple working procedure, so carry out annealing in process on the product wafer, means to start to carry out batch process, and processed finished products, therefore the product wafer is generally multi-disc here.
Step 13, by adjusting the method for annealing temperature, changes the Rs in regional on the second wafer control slice, makes the Rs in regional on the second wafer control slice reach unanimity.Rule of thumb show, Rs value and temperature T have the relation be inversely proportional to, and temperature is higher, and the Rs value obtained is lower.Institute thinks and makes each locational Rs on the second wafer control slice reach unanimity, according to the average Rs value on the second wafer control slice, Rs on it is raise higher than the regional temperature of mean value, perhaps the sub-average regional temperature of Rs on it is reduced, thereby obtain the uniform square resistance of the second wafer control slice regional.
Through above-mentioned steps, after carrying out annealing in process according to the annealing temperature of regional on the second wafer control slice on the product wafer, the product wafer is carried out to the WAT testing electrical property can be found, the operating current of product crystal round fringes can exceed predetermined dimension, may be greater than the electric current of crystal circle center position, also may be less than the electric current of crystal circle center position.According to common practise, can know, electric current and resistance have the relation be inversely proportional to, this is less than the Rs of center with regard to the Rs that means crystal round fringes, perhaps the Rs of crystal round fringes is greater than the Rs of center, that is to say the temperature adjustment of step 13, although on wafer control slice, Rs is regulated evenly, is not sufficient to make the Rs on the product wafer also to there is uniformity.Because the product wafer is only the wafer that really carries out finished product production, so crucial, meaningfully make the Rs on the product wafer there is uniformity, even the operating current on the product wafer has uniformity.
Summary of the invention
In view of this, the technical problem that the present invention solves is: how further to improve on the product wafer operating current uniformity when source-drain electrode is annealed.
For solving above-mentioned embodied technique problem, technical scheme of the present invention specifically is achieved in that
The invention provides on a kind of raising wafer the inhomogeneity method of operating current when source-drain electrode is annealed, the method comprises:
The first wafer control slice is carried out to Implantation annealing;
Measure the square resistance of the first annealed wafer control slice regional;
After the second wafer control slice is carried out to described Implantation, according to the square resistance of described the first wafer control slice regional, for obtaining the uniform square resistance of the second wafer control slice regional, adjust the annealing temperature of corresponding the second wafer control slice regional;
After carrying out annealing in process according to the annealing temperature of regional on the second wafer control slice on the first product wafer, measure the operating current of the first product wafer regional, obtain the first product crystal round fringes zone poor with the operating current of central area;
After the 3rd wafer control slice is carried out to described Implantation, poor with the operating current of central area according to described the first product crystal round fringes zone, the annealing temperature of corresponding the 3rd wafer control slice upper edge region of adjustment;
Carry out annealing in process according to the annealing temperature of regional on the 3rd wafer control slice on the second product wafer.
Described the first product crystal round fringes zone is the scope of circumferential interior 10 millimeters of wafer.
The described annealing temperature of adjusting corresponding the 3rd wafer control slice upper edge region is:
When the first product crystal round fringes zone is lower than the operating current of central area, the annealing temperature of the 3rd wafer control slice upper edge region is raise 3～10 degrees centigrade;
When higher than the operating current of central area, the annealing temperature of the 3rd wafer control slice upper edge region is reduced to 3～10 degrees centigrade when the first product crystal round fringes zone.
As seen from the above technical solutions, the present invention is measured the operating current of regional on the first product wafer, obtain the first product crystal round fringes zone poor with the operating current of central area, by the operating current to the 3rd wafer control slice fringe region, adjusted like this, adjust the annealing temperature of the 3rd wafer control slice fringe region, reach the operating current consistent with central area, finally the annealing temperature of regional on the 3rd wafer control slice is transferred on the second product wafer, just can be obtained the consistent operating current of the second product crystal column surface.With in prior art, only the operating current of regional on wafer control slice is measured, carry out the temperature adjustment and compare, operating current uniformity while greatly having improved on the product wafer source-drain electrode annealing.
The accompanying drawing explanation
Fig. 1 is the schematic flow sheet that the present invention improves on wafer the inhomogeneity method of operating current when source-drain electrode is annealed.
Fig. 2 is for to carry out to the product wafer device operating frequency distribution map that the WAT testing electrical property obtains according to the method for prior art, and according to method of the present invention, the product wafer carried out to the device operating frequency distribution map that the WAT testing electrical property obtains.
Embodiment
For make purpose of the present invention, technical scheme, and advantage clearer, referring to the accompanying drawing embodiment that develops simultaneously, the present invention is described in more detail.
The present invention utilizes schematic diagram have been described in detail, when the embodiment of the present invention is described in detail in detail, for convenience of explanation, the schematic diagram that means structure can be disobeyed local amplification of general ratio work, should not using this as limitation of the invention, in addition, in actual making, should comprise the three-dimensional space of length, width and the degree of depth.
When the present invention improves the annealing of source-drain electrode on wafer, as shown in Figure 1, it comprises the following steps the schematic flow sheet of the inhomogeneity method of operating current:
Same as the prior art, the first wafer control slice is carried out to the dosage of Implantation, be exactly the ion implantation dosage according to the actual source drain electrode.
Usually, wafer be take its circular central and is that the center of circle draws the concentric circles of different radii, and crystal column surface is divided into a plurality of zones.The measurement of Rs is carried out repeatedly in each zone, obtains the different Rs mean values that each zone has.Theoretically, the Rs value of wafer control slice regional should be consistent, but, due to the restriction of the board that injects board and annealed itself, causes the Rs value difference of regional.
Rule of thumb show, Rs value and temperature T have the relation be inversely proportional to, and temperature is higher, and the Rs value obtained is lower.Institute thinks and makes each locational Rs on the second wafer control slice reach unanimity, according to the average Rs value on the second wafer control slice, Rs on it is raise higher than the regional temperature of mean value, perhaps the sub-average regional temperature of Rs on it is reduced, thereby obtain the uniform square resistance of the second wafer control slice regional.
Particularly, the scope of crystal round fringes refers to the scope of circumferential interior 10 millimeters of wafer.The wafer that is for example 150 millimeters for radius, the scope of its crystal round fringes is exactly in the zone of 140～150 millimeters.
It should be noted that, in the WAT testing electrical property, the operating current of each position of product wafer is that frequency measurement by the resolution chart on the wafer Cutting Road obtains, frequency and described electric current have certain corresponding relation, and frequency is directly proportional to electric current, can correctly reflect the size of electric current.
Particularly, the present invention is 3～10 degrees centigrade of the variations in temperature in crystal round fringes zone, that is to say when the first product crystal round fringes zone lower than the operating current of central area the time, just by 3～10 degrees centigrade of the temperature in crystal round fringes zone risings; Higher than the operating current of central area the time, just the temperature in crystal round fringes zone is reduced to 3～10 degrees centigrade when the first product crystal round fringes zone.The actual temp that raises or reduce can be based on experience value, or test of many times obtains.
Rule of thumb, be preferably 3～5 degrees centigrade of the variations in temperature in crystal round fringes zone, just can overcome the defect of prior art.
Above-mentioned the first wafer control slice, the second wafer control slice, the 3rd wafer control slice and the first product wafer and the second product wafer all refer to the same product, and just wafer control slice can abandon after corresponding steps is finished, and the product wafer can finally be made finished product.
Fig. 2 is for to carry out to the product wafer device operating frequency distribution map that the WAT testing electrical property obtains according to the method for prior art, and according to method of the present invention, the product wafer carried out to the device operating frequency distribution map that the WAT testing electrical property obtains.
Wherein, the device operating frequency curve that art methods obtains means with A, the inventive method, when the first product crystal round fringes zone is lower than the operating current of central area, means the temperature in the crystal round fringes zone device operating frequency curve obtained that raises respectively after 3 degrees centigrade and 5 degrees centigrade respectively with B and C.Abscissa is frequency, the probable value that ordinate occurs for each position records from wafer frequency.As can be seen from the figure, through method of the present invention, curve B and C be relatively convergence, substantially there do not is the point be distributed in the low scope of frequency, and the probability be distributed in curve A in low-frequency range is larger, the operating current that a plurality of positions on the prior art wafer are described is on the low side, exceeds predetermined dimension, and the operating current uniformity is very poor.And the present invention has overcome this defect just, the operating current obtained from each position measurement of product wafer is roughly the same, do not exist the operating current of product crystal round fringes to exceed the defect of predetermined dimension yet, that is to say, method of the present invention has improved on the product wafer operating current uniformity when source-drain electrode is annealed greatly.
The foregoing is only preferred embodiment of the present invention, in order to limit the present invention, within the spirit and principles in the present invention not all, any modification of making, be equal to replacement, improvement etc., within all should being included in the scope of protection of the invention.
Claims (3)
1. one kind is improved on wafer the inhomogeneity method of operating current when source-drain electrode is annealed, and the method comprises:
The first wafer control slice is carried out to Implantation annealing;
Measure the square resistance of the first annealed wafer control slice regional;
After the second wafer control slice is carried out to described Implantation, according to the square resistance of described the first wafer control slice regional, for obtaining the uniform square resistance of the second wafer control slice regional, adjust the annealing temperature of corresponding the second wafer control slice regional;
After carrying out annealing in process according to the annealing temperature of regional on the second wafer control slice on the first product wafer, measure the operating current of the first product wafer regional, obtain the first product crystal round fringes zone poor with the operating current of central area;
After the 3rd wafer control slice is carried out to described Implantation, poor with the operating current of central area according to described the first product crystal round fringes zone, the annealing temperature of corresponding the 3rd wafer control slice upper edge region of adjustment;
Carry out annealing in process according to the annealing temperature of regional on the 3rd wafer control slice on the second product wafer.
2. the method for claim 1, is characterized in that, described the first product crystal round fringes zone is the scope of circumferential interior 10 millimeters of wafer.
3. method as claimed in claim 2, is characterized in that, the described annealing temperature of adjusting corresponding the 3rd wafer control slice upper edge region is:
When the first product crystal round fringes zone is lower than the operating current of central area, the annealing temperature of the 3rd wafer control slice upper edge region is raise 3～10 degrees centigrade;
When higher than the operating current of central area, the annealing temperature of the 3rd wafer control slice upper edge region is reduced to 3～10 degrees centigrade when the first product crystal round fringes zone.
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| CN109637949B (en) * | 2018-11-13 | 2023-09-26 | 南昌凯迅光电股份有限公司 | Temperature correction method for RTA annealing furnace |
| CN112420541A (en) * | 2020-11-18 | 2021-02-26 | 上海华力集成电路制造有限公司 | Monitoring method for source-drain annealing process of wafer product |
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