CN108878274B - Method for monitoring capability of rapid thermal annealing process - Google Patents
Method for monitoring capability of rapid thermal annealing process Download PDFInfo
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- CN108878274B CN108878274B CN201810672950.7A CN201810672950A CN108878274B CN 108878274 B CN108878274 B CN 108878274B CN 201810672950 A CN201810672950 A CN 201810672950A CN 108878274 B CN108878274 B CN 108878274B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67242—Apparatus for monitoring, sorting or marking
- H01L21/67253—Process monitoring, e.g. flow or thickness monitoring
Abstract
The invention provides a monitoring method for the capability of a rapid thermal annealing process, which comprises the steps of arranging a plurality of test areas in an area between the edge of a wafer and the center of the wafer, then the surface of the wafer is amorphized, normal source and drain ion implantation and a rapid thermal annealing process are carried out on the active region, the rapid thermal annealing process repairs and activates impurities implanted in the active region, and repairing the lattice defect on the surface of the wafer, which is generated due to amorphization, obtaining the actual corresponding relation between the crystallization parameter and the position of the surface of the wafer by obtaining the crystallization parameter of the test area, and comparing the actual corresponding relation with an ideal corresponding relation to judge whether the capacity of the rapid thermal annealing process meets the control requirement, thereby realizing the online monitoring of the rapid thermal annealing process and avoiding the performance difference of devices caused by the difference of the wafers in different batches.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a monitoring method for the capability of a rapid thermal annealing process.
Background
Rapid Thermal Annealing (RTA) has important applications in the modern semiconductor industry, where Rapid Thermal Annealing (RTA) processes can be carried out at extremely Rapid temperature increases and for short durations at target temperatures to thermally anneal wafers, and the Rapid temperature increase process and short duration can be optimized between the repair of lattice defects, the activation of impurities, and the minimization of impurity diffusion.
The CMOS device is the main constituent unit of the integrated circuit, and according to the manufacturing process and the technology, the RTA technology has strong correlation on the distribution of the electrical parameters in the wafer, so in order to improve the uniformity of the CMOS device of the chip in different areas in the wafer and improve the technological window of the product, the uniformity of the heat distribution of the RTA technology in different areas of the wafer can be improved, and the yield of the chip is improved. In the RTA process, the temperature setting for each region of the wafer is constant, and when the RTA process is performed, the following two effects are caused due to the process dispersion: the influence of the previous process causes different responses of the wafer to the temperatures of different regions of the RTA, and causes the distribution of CMO device parameters in different regions of the wafer, thereby causing larger dispersion of wafer electrical parameters and reducing the process window; due to the characteristics of the wafer manufacturing process, the process window at the edge of the wafer is narrow, and when the RTA process sets a uniform temperature in the edge region of the wafer, the batch-to-batch difference and the fluctuation caused by the RTA process cannot be effectively compensated.
Disclosure of Invention
The invention aims to provide a method for monitoring the capability of a rapid thermal annealing process, which realizes the online monitoring of the capability of the rapid thermal annealing process.
In order to achieve the above object, the present invention provides a method for monitoring the capability of a rapid thermal annealing process, comprising:
providing a wafer, wherein the wafer comprises an active area and a plurality of test areas, the plurality of test areas are distributed in an area from the edge of the wafer to the center of the wafer,
amorphizing the surface of the wafer;
performing source-drain ion implantation on the active region;
carrying out a rapid thermal annealing process on the wafer;
obtaining crystallization parameters of the plurality of test areas to obtain an actual corresponding relation between the crystallization parameters and positions of the surface of the wafer;
and comparing the actual corresponding relation with an ideal corresponding relation to obtain whether the rapid thermal annealing process capability meets the control requirement.
Optionally, the method for obtaining the ideal correspondence includes:
providing a plurality of test wafers, and amorphizing the surfaces of the test wafers;
subjecting a plurality of the test wafers to a standard rapid thermal annealing process;
and obtaining crystallization parameters at a plurality of positions on the surface of the test wafer to obtain an ideal corresponding relation between the crystallization parameters and the positions on the surface of the test wafer.
Optionally, the deviation between the actual corresponding relationship and the ideal corresponding relationship is within a set range, and the capacity of the rapid thermal annealing process meets the control requirement; and the deviation of the actual corresponding relation and the ideal corresponding relation exceeds the set range, and the capacity of the rapid thermal annealing process does not meet the control requirement.
Optionally, the actual corresponding relationship is compared with the ideal corresponding relationship, and the temperatures of different positions of the wafer during the rapid thermal annealing are regulated and controlled, so that the rapid thermal annealing process meets the control requirement.
Optionally, when the actual corresponding relationship and the ideal corresponding relationship generate overall deviation, the temperature of the rapid thermal annealing process is integrally increased or decreased; and when the actual corresponding relation and the ideal corresponding relation generate local deviation, increasing or reducing the temperature of the rapid thermal annealing process at the local position generating the deviation.
Optionally, before performing the rapid thermal annealing process on the wafer, the method for monitoring the capability of the rapid thermal annealing process further includes:
and forming a first dielectric layer, wherein the first dielectric layer covers the wafer.
Optionally, after the rapid thermal annealing process is performed on the wafer, the method for monitoring the capability of the rapid thermal annealing process further includes:
forming a second dielectric layer, wherein the second dielectric layer covers the first dielectric layer;
and etching the second dielectric layer and the first dielectric layer to form an opening, wherein the active region and the plurality of test regions are exposed out of the opening.
Optionally, the wafer includes a silicon-containing substrate, and the wafer surface is amorphized by performing ion implantation on the wafer, where the implanted ions include one or more of germanium ions, silicon ions, and xenon ions.
Optionally, the size of the wafer is 28nm-55 nm.
Optionally, an elliptical polarization spectrometer or a raman spectrometer is used to obtain the crystallization parameters of the wafer surface.
In the monitoring method for the rapid thermal annealing process capability provided by the invention, a plurality of test areas are arranged in the area between the edge of the wafer and the center of the wafer, then the surface of the wafer is amorphized, normal source and drain ion implantation and a rapid thermal annealing process are carried out on the active region, the rapid thermal annealing process repairs and activates impurities implanted in the active region, and repairing the lattice defect on the surface of the wafer, which is generated due to amorphization, obtaining the actual corresponding relation between the crystallization parameter and the position of the surface of the wafer by obtaining the crystallization parameter of the test area, and comparing the actual corresponding relation with an ideal corresponding relation to judge whether the capacity of the rapid thermal annealing process meets the control requirement, thereby realizing the online monitoring of the rapid thermal annealing process and avoiding the performance difference of devices caused by the difference of the wafers in different batches.
Drawings
Fig. 1 is a flowchart of a method for monitoring the capability of a rapid thermal annealing process according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of an ideal correspondence relationship provided by an embodiment of the present invention;
FIG. 3 is a diagram illustrating an actual mapping relationship according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of an actual mapping relationship provided in the embodiment of the present invention;
wherein, a-line a, b-line b, b '-line b', b "-line b", X1-X1 position, X2-X2 position.
Detailed Description
The following describes in more detail embodiments of the present invention with reference to the schematic drawings. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Referring to fig. 1, a flowchart of a method for monitoring the capability of a rapid thermal annealing process according to the present embodiment is shown, where the method for monitoring the capability of a rapid thermal annealing process includes:
s1: providing a wafer, wherein the wafer comprises an active area and a plurality of test areas, the plurality of test areas are distributed in an area from the edge of the wafer to the center of the wafer,
s2: amorphizing the surface of the wafer;
s3: performing source-drain ion implantation on the active region;
s4: carrying out a rapid thermal annealing process on the wafer;
s5: obtaining crystallization parameters of the plurality of test areas to obtain an actual corresponding relation between the crystallization parameters and positions of the surface of the wafer;
s6: and comparing the actual corresponding relation with an ideal corresponding relation to obtain whether the rapid thermal annealing process capability meets the control requirement.
Firstly, before performing a rapid thermal annealing process on a large number of wafers after ion implantation, an engineer usually calibrates a rapid thermal annealing machine, wherein the temperature of different regions on the wafers is compensated during calibration so as to ensure that the wafers can perform a standard rapid thermal annealing process. A plurality of test wafers are then provided, the test wafers having a size of 28nm-55 nm. The test wafer is usually a bare wafer including only a substrate, and optionally, the substrate of the test wafer includes silicon, such as a silicon substrate, a silicon germanium substrate, a silicon on insulator substrate, and the like. Injecting one or more of germanium ions, silicon ions and xenon ions into the substrate of the test wafer to amorphize the surface of the test wafer, and then carrying out a standard rapid thermal annealing process on the test wafers in the rapid thermal annealing process, wherein the standard rapid thermal annealing process can repair lattice defects on the surface of the test wafer to crystallize the amorphous structure on the surface of the test wafer. Since the same rapid thermal annealing equipment is adopted by a plurality of test wafers, and the same rapid thermal annealing process is performed (the parameters such as annealing time, annealing temperature and the like are the same), ideally, the crystallization parameters at each position on the surface of the test wafers should be equal. Next, obtaining crystallization parameters at a plurality of positions on the surface of each test wafer, and fitting the corresponding data of all the crystallization parameters and the positions into an ideal corresponding relationship between the crystallization parameters and the positions on the surface of the test wafer, specifically as shown in fig. 2, a line a may be approximately regarded as a straight line.
Optionally, in order to improve the accuracy of the ideal corresponding relationship, the number of the test wafers may be adaptively increased, and the crystallization parameters at different positions on the test wafers may be tested as much as possible, so that the more data is obtained, the closer the ideal corresponding relationship is to the real situation. Since the rapid thermal annealing equipment is heated by the annular heater arranged at the bottom of the test wafer, wafer parameters on the annular zones with the same radius on the test wafer are theoretically equal, the test wafer can be divided into the annular zones as many as possible, and each annular zone only needs to detect the crystallization parameter at one position.
Referring to fig. 3, step S1 is executed to provide a wafer, wherein the wafer has the same dimensions and specifications as the test wafer. The wafer is provided with scribing channels which are transversely and longitudinally arranged, the wafer comprises an active area and a plurality of testing areas, the testing areas are arranged on the scribing channels, and the testing areas are distributed at positions from the edge to the center of the wafer, so that the subsequent detection of the crystallization parameters on the surface of the wafer is facilitated. The number of the test areas can be increased by a proper amount so as to improve the precision of the actual corresponding relation obtained subsequently. Next, step S2 is performed to amorphize the wafer surface. Further, the process of amorphizing the wafer surface is the same as the process of amorphizing the test wafer surface, for example: the process for amorphizing the surface of the test wafer is to implant germanium ions into the test wafer, and then the process for amorphizing the surface of the test wafer is to implant germanium ions into the test wafer, and the energy, the dose and other process parameters of the implanted germanium ions are the same.
And then, executing step S3, performing source-drain ion implantation on the active region to form a source-drain region, wherein when the source-drain ion implantation is performed on the active region, the test region is covered by a mask, so that the source-drain ion implantation process of the active region does not affect the test region. Optionally, the ion implanted into the source and drain regions and the implantation depth may be adjusted to suit the device to be formed, which is not limited in the present invention. And then forming a first dielectric layer on the wafer, wherein the first dielectric layer covers the wafer to prevent ions injected into the source and drain regions from escaping when a rapid thermal annealing process is subsequently carried out, and the first dielectric layer can also adjust the stress of a subsequent film deposited on the wafer.
Next, step S4 is performed to perform a rapid thermal annealing process on the wafer. Specifically, the wafer is subjected to a rapid thermal annealing process in the rapid thermal annealing equipment, and the rapid thermal annealing process can activate ions injected into the active region and repair a lattice structure damaged by amorphization on the surface of the wafer. Further, the rapid thermal annealing process performed on the wafer is the same as the rapid thermal annealing process performed on the test wafer, for example: the temperature for performing the rapid thermal annealing process on the test wafer is 1000 ℃, so the temperature for performing the rapid thermal annealing process on the wafer is also 1000 ℃, and the annealing time, the annealing humidity and other process parameters are the same.
Furthermore, because the first dielectric layer is formed on the wafer, in order to measure the crystallization parameters of the surface of the wafer, a second dielectric layer is formed on the first dielectric layer, and then the second dielectric layer and the first dielectric layer are etched to expose the test area and the active area. Preferably, the first dielectric layer is made of silicon oxide, and the second dielectric layer is made of silicon nitride.
Next, step S5 is executed to test the crystallization parameters of the multiple test areas at each position on the wafer, and then fit the multiple crystallization parameters into the actual corresponding relationship between the crystallization parameters and the positions on the wafer surface, optionally, an elliptical polarization spectrometer or a raman spectrometer may be used to obtain the crystallization parameters on the wafer surface. Because the wafer and the test wafer are both made of the same wafer, and the same amorphization process and rapid thermal annealing process are adopted for the wafer and the test wafer, theoretically, the actual corresponding relationship between the crystallization parameters and the positions of the surface of the wafer and the ideal corresponding relationship between the crystallization parameters and the positions of the surface of the test wafer should be kept consistent. However, since the wafers are subjected to other previous processes (e.g., ion implantation on the active region) between the rapid thermal annealing processes, some deviations may occur in the previous processes of different wafers, and the rapid thermal annealing processing equipment may generate process fluctuations, which may cause differences between different wafers or between different batches of wafers, thereby causing differences in process parameters of devices.
And finally, executing a step S6, and comparing the actual corresponding relation with the ideal corresponding relation to obtain whether the capacity of the rapid thermal annealing process meets the control requirement. Specifically, if the deviation between the actual corresponding relationship and the ideal corresponding relationship is within a set range, the capacity of the rapid thermal annealing process meets the control requirement; and the deviation of the actual corresponding relation and the ideal corresponding relation exceeds the set range, and the capacity of the rapid thermal annealing process does not meet the control requirement. The setting range can be set and adjusted according to the precision of the device which needs to be formed actually, and the invention is not limited.
Further, please refer to fig. 3, wherein when the actual corresponding relationship and the ideal corresponding relationship are shifted integrally (the line b is biased downward as a whole, and the line b' is biased upward as a whole), the actual corresponding relationship can approach the ideal corresponding relationship by raising or lowering the temperature of the rapid thermal annealing process integrally, so that the capability of the rapid thermal annealing process meets the control requirement; as shown in fig. 4, when the actual corresponding relationship and the ideal corresponding relationship are locally offset (line b "is offset upward at the position X1 and is offset downward at the position X2), the actual corresponding relationship approaches the ideal corresponding relationship by increasing or decreasing the temperature of the rapid thermal annealing process at the offset-generating local position, so that the capability of the rapid thermal annealing process meets the control requirement.
In summary, in the monitoring method for rapid thermal annealing capability according to the embodiment of the present invention, by disposing a plurality of test regions in a region between the edge of the wafer and the center of the wafer, then the surface of the wafer is amorphized, normal source and drain ion implantation and a rapid thermal annealing process are carried out on the active region, the rapid thermal annealing process repairs and activates impurities implanted in the active region, and repairing the lattice defect on the surface of the wafer, which is generated due to amorphization, obtaining the actual corresponding relation between the crystallization parameter and the position of the surface of the wafer by obtaining the crystallization parameter of the test area, and comparing the actual corresponding relation with an ideal corresponding relation to judge whether the capacity of the rapid thermal annealing process meets the control requirement, thereby realizing the online monitoring of the rapid thermal annealing process and avoiding the performance difference of devices caused by the difference of the wafers in different batches.
The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any way. It will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A method for monitoring the capability of a rapid thermal annealing process is characterized by comprising the following steps:
providing a wafer, wherein the wafer comprises an active area and a plurality of test areas, and the test areas are distributed in an area from the edge of the wafer to the center of the wafer;
amorphizing the surface of the wafer;
performing source-drain ion implantation on the active region;
carrying out a rapid thermal annealing process on the wafer;
obtaining crystallization parameters of the plurality of test areas to obtain an actual corresponding relation between the crystallization parameters and positions of the surface of the wafer;
and comparing the actual corresponding relation with an ideal corresponding relation to obtain whether the rapid thermal annealing process capability meets the control requirement.
2. The method for monitoring the capability of rapid thermal annealing process according to claim 1, wherein the method for obtaining the ideal corresponding relationship comprises:
providing a plurality of test wafers, and amorphizing the surfaces of the test wafers;
subjecting a plurality of the test wafers to a standard rapid thermal annealing process;
and obtaining crystallization parameters at a plurality of positions on the surface of the test wafer to obtain an ideal corresponding relation between the crystallization parameters and the positions on the surface of the test wafer.
3. The method for monitoring rapid thermal annealing process capability of claim 2, wherein the deviation of the actual correspondence from the ideal correspondence is within a set range, and the rapid thermal annealing process capability satisfies the control requirement; and the deviation of the actual corresponding relation and the ideal corresponding relation exceeds the set range, and the capacity of the rapid thermal annealing process does not meet the control requirement.
4. The method for monitoring the capability of the rapid thermal annealing process according to claim 3, wherein the actual corresponding relationship is compared with the ideal corresponding relationship to adjust the temperatures of different positions of the wafer during the rapid thermal annealing process, so that the rapid thermal annealing process satisfies the control requirement.
5. The method for monitoring the capability of rapid thermal annealing process according to claim 4, wherein when the actual correspondence is shifted from the ideal correspondence as a whole, the temperature of rapid thermal annealing process is raised or lowered as a whole; and when the actual corresponding relation and the ideal corresponding relation generate local deviation, increasing or reducing the temperature of the rapid thermal annealing process at the local position generating the deviation.
6. The method for monitoring the rapid thermal annealing process capability of claim 1, wherein before the rapid thermal annealing process is performed on the wafer, the method for monitoring the rapid thermal annealing process capability further comprises:
and forming a first dielectric layer, wherein the first dielectric layer covers the wafer.
7. The method for monitoring the capability of rapid thermal annealing process according to claim 6, wherein after the rapid thermal annealing process is performed on the wafer, the method for monitoring the capability of rapid thermal annealing process further comprises:
forming a second dielectric layer, wherein the second dielectric layer covers the first dielectric layer;
and etching the second dielectric layer and the first dielectric layer to form an opening, wherein the active region and the plurality of test regions are exposed out of the opening.
8. The method for monitoring the capability of the rapid thermal annealing process according to claim 1, wherein the wafer comprises a silicon-containing substrate, the wafer surface is amorphized by ion implantation into the wafer, and the implanted ions comprise one or more of germanium ions, silicon ions and xenon ions.
9. The method for monitoring the capability of rapid thermal annealing process according to claim 8, wherein the wafer has a size of 28nm-55 nm.
10. The method for monitoring rapid thermal annealing process capability of claim 1, wherein the crystallization parameters of the wafer surface are obtained by using an ellipsometer or a raman spectrometer.
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