CN1191001C - Circuit base board having high quality rate - Google Patents
Circuit base board having high quality rate Download PDFInfo
- Publication number
- CN1191001C CN1191001C CNB011368187A CN01136818A CN1191001C CN 1191001 C CN1191001 C CN 1191001C CN B011368187 A CNB011368187 A CN B011368187A CN 01136818 A CN01136818 A CN 01136818A CN 1191001 C CN1191001 C CN 1191001C
- Authority
- CN
- China
- Prior art keywords
- weld pad
- wafer
- bonding wire
- power supply
- welding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48237—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a die pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
The present invention relates to a circuit base plate with high quality rate, which comprises a wafer, a base plate, a plurality of first welding lines and a plurality of second welding lines, wherein a plurality of earthing welding pads and power source welding pads are arranged on the wafer; an earthing ring and a power source ring are arranged on the base plate; the earthing welding pads and the power source welding pads are respectively connected to the earthing ring and the power source ring through the first welding lines and the second welding lines, wherein the earthing welding pads and the power source welding pads are arranged on the wafer continuously in groups to isolate the first welding lines and the second welding lines. The electric property of products and the short circuit probability of welding lines can be changed through the specific arrangement of the welding pads on the wafer and the copper foil on the base plate.
Description
Technical field
The present invention relates to the circuit device, particularly a kind of circuit substrate.
Background technology
Fig. 1 has shown an one of a traditional circuit substrate, comprising a substrate 11, the ground loop (ground ring) 111 that on substrate, forms with Copper Foil, power ring (power ring) 112, signal pin 113 and anti-welding material layer 114, be set in the wafer (die) 12 on the substrate, ground connection weld pad on the wafer 12 (ground pad) 121, power supply weld pad (power pad) 122 and signal weld pad 123, connect ground connection weld pad 121 respectively to ground loop 111, the bonding wire (Bonding wire) 131 of power supply weld pad 122 to power ring 112 and signal weld pad 123 to signal pin 113,132,133.Wherein, the ground connection weld pad 121 on the wafer 12, power supply weld pad 122 and signal weld pad 123 are respectively in order to receiving wafer 12 required ground connection and supply voltage, and the input of signal and output.
Design on traditional circuit substrate and chip bonding pads, as shown in Figure 1, ground connection weld pad 121, power supply weld pad 122 and signal weld pad 123 become staggered state on wafer 12, this kind arrangement mode make to connect ground connection weld pad 121 to ground loop 111, power supply weld pad 122 to power ring 112 and signal weld pad 123 to the bonding wire 131,132,133 of signal pin 113 interlocking.
Yet, when forming the back at bonding wire and irritate mould (molding), the phenomenon that is short-circuited because of bonding wire is crooked, two adjacent bonding wires must have different camber to be set, also must be with the spacing increasing of 112 of ground loop 111 and power rings.So, pull the length of having grown bonding wire and increased its inductance value, reduced the electrical characteristic of product.
Summary of the invention
In order to address the above problem, the invention provides a kind of circuit substrate, can avoid under the situation about being short-circuited, can there be identical bonding wire camber to set, can also shorten the length of bonding wire, improve the electrical characteristic of bonding wire.
The object of the present invention is to provide a kind of circuit substrate, comprise a wafer, a substrate, many first and second bonding wires.Have a plurality of ground connection weld pads and power supply weld pad on the wafer.Have a ground loop and power ring on the substrate.Described first and second bonding wire is connected to described ground loop and power ring with described ground connection weld pad and power supply weld pad respectively.Wherein, described ground connection weld pad and power supply weld pad are arranged on described wafer separately in groups continuously, and separate described first and second bonding wire.
Thus, the present invention will connect the ground connection weld pad to ground loop, power supply weld pad to power ring and the arrangement of hiving off of signal weld pad to the bonding wire of signal pin, even since connect the bonding wire of power supply weld pad to power ring, ground connection weld pad to ground loop respectively short circuit also can not cause the operating mistake of circuit in the wafer, therefore can have identical camber sets, the spacing of ground loop and power ring can also shorten, and wire length is reduced and improves its electrical characteristic.
The present invention more includes many articles the 3rd bonding wires, described wafer and described substrate have more a plurality of signal weld pads and a plurality of signal pin respectively, described the 3rd bonding wire is connected to described signal pin with described signal weld pad, and described signal weld pad and signal pin are arranged in groups continuously, and separate described the 3rd bonding wire and described first, second bonding wire; And
Described power ring has a protuberance, and described power supply weld pad nationality is wired in described protuberance by described second and is connected with described power ring, makes the camber of described first and second bonding wire identical;
Described ground loop have one with the relative recess of described power ring protuberance;
More comprise an anti-welding material layer, between described wafer and the described substrate and between described power ring and the described ground loop;
Comprise that more one is positioned at the epoxy layer in order to fixing described wafer between described anti-welding material layer and described wafer.
In sum, the present invention utilize power supply weld pad on the wafer, ground connection weld pad and signal weld pad in groups arrangement and have the power ring of protuberance, make the present invention have the bonding wire camber and set probability identical, that wire length shortens and reduce power supply and ground loop short circuit, good far beyond traditional circuit substrate performance.
Description of drawings
One one of Fig. 1 one traditional circuit substrate;
In Fig. 2 one embodiment of the invention one of circuit substrate one;
Among Fig. 3 Fig. 2 along the profile of XX ' tangent line.
The piece number explanation:
11,21 circuit substrates;
12,22 wafers:
131,132,133,231,232,233 bonding wires:
111,211 ground loops;
112,212 power rings;
113,213 signal pins;
114,214 anti-welding material layers;
121,221 ground connection weld pads;
122,222 power supply weld pads;
123,223 signal weld pads.
Embodiment
Fig. 2,3 has shown an one of circuit substrate of one embodiment of the invention, comprising a substrate 21, the ground loop 211, power ring 212 and the signal pin 213 that form with Copper Foil on the substrate, be set in wafer 22 on the substrate, on the wafer 22 ground connection weld pad 221, power supply weld pad 222, signal weld pad 223 and anti-welding material layer 214, respectively connect ground connection weld pad 221 to ground loop 211, power supply weld pad 222 to power ring 212 and signal weld pad 223 to the bonding wire 231,232,233 of signal pin 213.Wherein, the ground connection weld pad 221 on the wafer 22, power supply weld pad 222 and signal weld pad 223 are respectively in order to receiving wafer 22 required ground connection and supply voltage, and the input of signal and output.
In addition, power ring 212 also has a protuberance 2121, and ground loop 211 also has a relative recess (its label omits), the distance of power supply weld pad 222 on can further power ring 212 and the wafer 22, the wire length that connects power ring 212 and power supply weld pad 22 is shortened, improve its electrical characteristic.
Fig. 3 has shown among Fig. 2 the profile along XX ' tangent line.Wherein components identical is to use identical symbolic representation.Have ground loop 211, power ring 212 on the substrate 21 and placing on the ground loop 211 and the anti-welding material layer 214 between the Copper Foil spacing, the epoxy layer (Epoxy) 24 between anti-welding material layer 214 and wafer 22.Epoxy layer 24 is in order to wafer 22 is fixed on the anti-welding material layer 214.
Circuit substrate in the present embodiment and the design on the chip bonding pads, as shown in Figure 2, ground connection weld pad 221, power supply weld pad 222 and signal weld pad 223 are arranged in continuous in groups mode on wafer 22, this kind arrangement mode makes and connects the bonding wire groups that ground connection weld pad 221 to ground loop 211, power supply weld pad 222 to power ring 212 and signal weld pad 223 to the bonding wire 231,232,233 of signal pin 213 is divided into three groups of separations that two adjacent bonding wires systems belong to the bonding wire of same connection purpose.
At this moment, be in contact with one another short circuit because of the filling mould is crooked even connect three bonding wires 231 of ground loop 211 and ground connection weld pad 221, because it is connected to same ground loop 211, so can't be influential to the operation of circuit in the wafer 22, the bonding wire that connects power ring 212 and power supply weld pad 22 also has same situation, so bonding wire 231,232 and 233 can have identical camber setting and needn't worry the problem that it may be short-circuited; Simultaneously, because power ring 212 has protuberance 2121, reduced the length of bonding wire 232, it is good making its electrical characteristic bonding wire that tradition is long.
Claims (6)
1, a kind of circuit substrate comprises at least:
One wafer has a plurality of ground connection weld pads and power supply weld pad;
One substrate has a ground loop and power ring; And
Many first and second bonding wires are connected to described ground loop and power ring with described ground connection weld pad and power supply weld pad respectively;
Wherein, described ground connection weld pad and power supply weld pad are arranged on described wafer separately in groups continuously, thereby separate described first and second bonding wire.
2, circuit substrate as claimed in claim 1, it is characterized in that, more include many articles the 3rd bonding wires, described wafer and described substrate have more a plurality of signal weld pads and a plurality of signal pin respectively, described the 3rd bonding wire is connected to described signal pin with described signal weld pad, and described signal weld pad and signal pin are arranged separately in groups continuously, thereby separate described the 3rd bonding wire and described first, second bonding wire.
3, circuit substrate as claimed in claim 1 is characterized in that, described power ring has a protuberance, and described power supply weld pad nationality is wired in described protuberance by described second and is connected with described power ring, makes the camber of described first and second bonding wire identical.
4, circuit substrate as claimed in claim 3 is characterized in that, described ground loop have one with the relative recess of described power ring protuberance.
5, circuit substrate as claimed in claim 1 is characterized in that, more comprises an anti-welding material layer, between described wafer and the described substrate and between described power ring and the described ground loop.
6, circuit substrate as claimed in claim 5 is characterized in that, comprises that more one is positioned at the epoxy layer in order to fixing described wafer between described anti-welding material layer and described wafer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB011368187A CN1191001C (en) | 2001-10-24 | 2001-10-24 | Circuit base board having high quality rate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB011368187A CN1191001C (en) | 2001-10-24 | 2001-10-24 | Circuit base board having high quality rate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1414821A CN1414821A (en) | 2003-04-30 |
| CN1191001C true CN1191001C (en) | 2005-02-23 |
Family
ID=4673939
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB011368187A Expired - Fee Related CN1191001C (en) | 2001-10-24 | 2001-10-24 | Circuit base board having high quality rate |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1191001C (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI341576B (en) | 2007-01-24 | 2011-05-01 | Chipmos Technologies Inc | Chip package reducing wiring layers on substrate and its carrier |
| KR101941795B1 (en) * | 2014-09-23 | 2019-01-23 | 후아웨이 테크놀러지 컴퍼니 리미티드 | Radio frequency power assembly and transceiver device |
-
2001
- 2001-10-24 CN CNB011368187A patent/CN1191001C/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CN1414821A (en) | 2003-04-30 |
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|---|---|---|---|
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20050223 Termination date: 20091124 |