CN1170313C - Multi-layer substrate of IC and arrangement method of holes on dielectric layers - Google Patents
Multi-layer substrate of IC and arrangement method of holes on dielectric layers Download PDFInfo
- Publication number
- CN1170313C CN1170313C CNB011293640A CN01129364A CN1170313C CN 1170313 C CN1170313 C CN 1170313C CN B011293640 A CNB011293640 A CN B011293640A CN 01129364 A CN01129364 A CN 01129364A CN 1170313 C CN1170313 C CN 1170313C
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- CN
- China
- Prior art keywords
- laminate
- interlayer
- conductive plate
- holes
- interlayer hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Abstract
The present invention discloses a multi-layer substrate of an integrated circuit and an arrangement method of interlayer holes, which is suitable for a wafer with a connecting shim. The multi-layer substrate comprises a first veneer and a second veneer, wherein conducting wires electrically coming into contact with the connecting shim are laid on the surface of the first veneer, so the wafer can generate currents in the conducting wires during operation; an electric conduction thin plate and interlayer holes penetrating the second veneer and the electric conduction thin plate are laid on the surface of the second veneer. When the wafer acts, the electric conduction thin plate is electrically connected with a ground point, and the currents in the conducting wires on the first veneer are induced in the electric conduction thin plate to generate opposite mirror currents. The interlayer holes are arranged in a radial shape in the multi-layer substrate, and the path of each mirror current is communicated with the ground point, so that noise can be avoided.
Description
Technical field
The present invention relates to the field of integrated circuit, especially a kind of multilager base plate of integrated circuit and interlayer hole aligning method thereof.
Background technology
The structure of traditional B GA (Ball Grid Array) multilager base plate as shown in Figure 1, multilager base plate 1 comprises first, second, third and fourth laminate 11,12,13,14.Its bottom surface has a plurality of connection balls 17 (solderball), and wafer 15 is connected with an external device (ED) (figure does not show).The first and the 4th laminate 11,14 surfaces of multilager base plate 1 are equipped with many lead (conductingtrace, the lead 114 that only shows first laminate 11 among Fig. 1) be the usefulness of wiring (fan out), second and third laminate 12,13 surfaces then are equipped with the conductive plate (not showing among Fig. 1) of full wafer and are the usefulness that connects power supply and ground connection.In addition, first, second, third and fourth laminate all has not exclusively relative interlayer hole (the interlayer hole 111a and the 111b that only show first laminate among Fig. 1) of position.Therefore, the electric connection between each laminate is reached via those interlayer holes, and the electric connection on the same laminate is then reached by lead (the first, the 4th laminate 11,14) and conductive plate (second, third laminate 12,13).
Wafer 15 is embedded on first laminate 11.Wafer 15 has the thin pad of a plurality of connections (Die Pad) 151, carries out output, goes into signal, connects the link of power supply or ground connection as wafer 15, and connect with the thin pad 115 that is connected on first laminate 11 by welded wire 16 (as gold thread).Be equipped with the many elongated and leads 114 that extend laterally on the surface of first laminate 11, will connect and thinly fill up 115 and be connected to medial and lateral interlayer hole 111a and 111b.For illustrative simplicity, do not show the lead 114 of all medial and lateral interlayer hole 111a and 111b among Fig. 1.At wafer 15 an other ground loop 112 (ground ring) and the power rings (power ring) 113 of still being equipped with, the conductive plate with second, third laminate 12,13 electrically connects respectively.The earth terminal of wafer 15 approaches 151 on pad with being connected of power end and is connected to ground loop 112 and power ring 113 via metal wire 16 respectively.
See also Fig. 2, shown interlayer hole 121a, the 121b on second laminate 12, the arrangement mode of 121c in the tradition among the figure.As above-mentioned, the surface of second laminate 12 is equipped with a conductive plate 122, makes that any point-to-point transmission is electric connection when not having the obstruction of interlayer hole 121a, 121b, 121c on full wafer second laminate 12.This interlayer hole 121a, 121b, 121c are divided into three layers of arrangement haply from outside to inside.The interlayer hole 121b major part in the interlayer hole 121a that mediates and the close outside connects thin pad as the signal end with wafer 15 (Fig. 1) and is connected to the usefulness that connects ball 17 (Fig. 1), also has few part to be connected to the usefulness that connects ball 17 as the thin pad of power end connection with wafer 15.In addition, interlayer hole 121a, 121b all insulate with conductive plate 122.Wherein, interlayer hole 121a, 121b pass through conductive plate 122 and with conductive plate, the 4th laminate 14 of three ply board 13 or be connected ball 17 and connect.The interlayer hole 121c of close inboard then is the usefulness that connects ball 17 as conductive plate 122 is connected to.Interlayer hole 121c and conductive plate 122 electrically connect.
There is the excessive problem of noise in above-mentioned traditional multilager base plate.Please consult Fig. 2 again, one of this problem occurrence cause is that the arrangement mode of the interlayer hole 121a in second laminate 12 is not good.Wafer 15 is when operation, since can carry out signal output, go into action, make first laminate, 11 upper conductors 114 can produce electric current, because the distance that the conductive plate 122 of second laminate 12 and the lead of first laminate 11 are 114 is very near, make the electric current in the lead 114 of first laminate 11 to induce the image electric current that a direction is opposite, the position is relative in the conductive plate 122 of second laminate 12, the arrow among Fig. 2 shows the possible path of this image electric current.When image electric current fails to follow a discharge path that is connected to earth point when flowing out, just can be, go into the very big noise of generation in the signal in the output of wafer 15.And in traditional multilager base plate, conductive plate 122 earthy on second laminate 12 originally can provide so discharge path, but because interlayer hole 121a is enclosed in interlayer hole 121c wherein, cut off being communicated with between image electric current and earth point, though cause conductive plate 122 to be connected with earth point through interlayer hole 121c, image electric current wherein can't discharge through earth point.
Summary of the invention
For solving above-mentioned problems of the prior art, the invention provides a kind of multilager base plate and interlayer hole aligning method thereof of integrated circuit, the present invention is applicable to a wafer, reach the purpose that image electric current (image current) discharge path is provided by the arrangement mode that changes interlayer hole (through hole or via hole), and then avoid the generation of noise.
The multilager base plate of a kind of integrated circuit of the present invention comprises: first and second laminate.The first laminate surface is equipped with many leads, and those leads are connected the electrically contact of thin pad with those, makes this wafer produce power plural current in those leads when operation.The second laminate surface is equipped with a conductive plate and a plurality of interlayer hole that passes through this second laminate and this conductive plate, this wafer is being done the time spent, this conductive plate and an earth point electrically connect, electric current on this first laminate in those leads is responded to the relative image electric current of generation in this conductive plate, wherein, these a plurality of interlayer holes are with radial arrangement, and this arrangement mode all is communicated with the path of each image electric current with this earth point.
The interlayer hole aligning method of a kind of integrated circuit multilayer substrate of the present invention, be applicable to a wafer, this wafer has the thin pad of a plurality of connections, this method may further comprise the steps: first and second laminate is provided, this first laminate surface is equipped with many leads and those leads are connected the electrically contact of thin pad with those, and this second laminate surface is equipped with a conductive plate and a plurality of interlayer hole that passes through this second laminate and this conductive plate.When this wafer operation, in those leads, produce power plural current and, make the relative image electric current of induction generation in this conductive plate this conductive plate ground connection.Arrange those interlayer holes, the path of those image electric currents all is communicated with this earth point.
Adopt the multilager base plate and the interlayer hole aligning method thereof of integrated circuit of the present invention, because the interlayer hole on the earthy conductive plate is arranged (as radial) with a particular form, make the path of image electric current can not be cut off and can discharge, thereby reduced wafer output, go into the noise in the signal via earth point.
Description of drawings
Fig. 1 is the structural representation of a BGA multilager base plate;
Fig. 2 is the top view of earthy conductive plate in the traditional B GA multilager base plate;
Fig. 3 is the top view of an embodiment in the BGA multilager base plate of the present invention;
Fig. 4 is the flow chart of the interlayer hole aligning method of BGA multilager base plate of the present invention.
Component parameters explanation among the figure:
1 multilager base plate, 11 first laminates
111a, 111b, 121a, 121b, 121c, 321a, 321b, 321c interlayer hole
112 ground loops, 113 power rings, 114 leads
115 connect thin pad 12,32 second laminates 122,322 conductive plates
13 three ply boards 14 the 4th laminate, 15 wafers
16 metal wires 17 connect ball
Embodiment
Below in conjunction with accompanying drawing the present invention is further described:
The integrated circuit multilayer board structure of present embodiment is identical with Fig. 1, and so the interlayer hole of its second laminate 12 is arranged differently with the shown arrangement mode of Fig. 2, below will cooperate Fig. 3 to describe.
See also Fig. 3, the surface of second laminate 32 is equipped with a conductive plate 322, makes that any point-to-point transmission is electric connection when not having the obstruction of interlayer hole 321a, 321b, 321c on full wafer second laminate 32.Those interlayer holes 321a, 321b, 321c are divided into three layers of arrangement haply from outside to inside.The interlayer hole 321b major part in the interlayer hole 321a that mediates and the close outside connects thin pad as the signal end with wafer 15 (Fig. 1) and is connected to the usefulness that connects ball 17 (Fig. 1), also has few part to be connected to the usefulness that connects ball 17 as the thin pad of power end connection with wafer 15.In addition, interlayer hole 321a, 321b all insulate with conductive plate 322.Wherein, interlayer hole 321a, 321b pass through conductive plate 322 and with conductive plate, the 4th laminate 14 of three ply board 13 or be connected ball 17 and connect.The interlayer hole 321c of close inboard then is the usefulness that connects ball 17 as conductive plate 322 is connected to.Interlayer hole 321c and conductive plate 322 electrically connect.
What pay special attention to is that interlayer hole 321a is with radial arrangement.Wafer 15 is when operation, lead 114 on first laminate 11 can produce electric current, because the distance that the conductive plate 322 of second laminate 32 and the lead of first laminate 11 are 114 is very near, make the electric current in the lead 114 of first laminate 11 to induce the image electric current that a direction is opposite, the position is relative in the conductive plate 322 of second laminate 32, the possible path of this image electric current is shown in the arrow among Fig. 3.Because interlayer hole 321a is with radial arrangement, the path of this image electric current can not cut off by interlayer hole 321a and can be communicated with interlayer hole 321c, and then is connected to earth point.Therefore, image electric current just can follow a discharge path that is connected to earth point and flow out, just can be in the output of wafer 15, go into the excessive noise of generation in the signal.
Fig. 4 shows the flow chart according to the interlayer hole aligning method of the present invention's one BGA multilager base plate.
At first, in step 41, provide a wafer, first and second laminate.Wherein, wafer has the thin pad of a plurality of connections.The surface of first laminate is equipped with many leads, and each lead all is connected the electrically contact of thin pad with one of them.The second laminate surface then is equipped with a conductive plate and a plurality of interlayer hole that passes through second laminate and conductive plate simultaneously.
Then, in step 42, when wafer is operated, in lead, produce electric current and with conductive plate ground connection, make conductive plate because of with the approaching sensed relative image electric current that goes out of first laminate.
At last, in step 43, interlayer hole is divided into first and second interlayer hole, first interlayer hole contacts and electrically connects with conductive plate, and second interlayer hole does not then contact with conductive plate and forms insulation.Make first interlayer hole be positioned at the inboard simultaneously and surrounded by second interlayer hole, second interlayer hole is then arranged in the radial mode as Fig. 3.
The above only is preferred embodiment of the present invention, and all other do not break away from the equivalence of being finished under the disclosed spirit and change or modification, all should be included in the claim scope of the present invention.
Claims (4)
1. the multilager base plate of an integrated circuit, this multilager base plate comprises at least,
One can inlay first laminate of a wafer;
One second laminate is connected with first laminate, and the surface is equipped with a conductive plate and a plurality of interlayer hole that passes through this second laminate and this conductive plate; This conductive plate electrically contacts with a ground loop; These a plurality of interlayer holes are divided into three layers from inside to outside at least, be a plurality of first interlayer holes, a plurality of second interlayer hole and a plurality of the 3rd interlayer hole, these a plurality of first interlayer holes and described conductive plate electrically connect, these a plurality of second interlayer holes and a plurality of the 3rd interlayer hole and the insulation of described conductive plate;
One three ply board is connected with second laminate; One the 4th laminate is connected with three ply board; It is characterized in that: wherein above-mentioned a plurality of second interlayer holes are arranged radially.
2. the interlayer hole aligning method of an integrated circuit multilayer substrate is characterized in that, this aligning method is applicable to that one has the wafer of the thin pad of a plurality of connections, and this method comprises following steps at least:
One first and second laminate is provided, this first laminate surface is equipped with many leads and this many leads approach electrically contact of pad with this a plurality of connection, and this second laminate surface is equipped with a conductive plate and a plurality of interlayer hole that passes through this second laminate and this conductive plate;
When this wafer operation, in these many leads, produce electric current and, make the relative image electric current of induction generation in this conductive plate this conductive plate ground connection;
A plurality of second interlayer holes are arranged radially, and the path of each image electric current all is communicated with this earth point.
3. the interlayer hole aligning method of integrated circuit multilayer substrate as claimed in claim 2 is characterized in that, the aligning method of wherein above-mentioned a plurality of interlayer holes also comprises:
Above-mentioned a plurality of interlayer holes are divided into a plurality of first and second interlayer holes, these a plurality of first interlayer holes and above-mentioned conductive plate electric connection, these a plurality of second interlayer holes and above-mentioned conductive plate insulation;
Make these a plurality of second interlayer holes surround these a plurality of first interlayer holes;
Should a plurality of second interlayer holes with radial arrangement.
4. the interlayer hole aligning method of integrated circuit multilayer substrate as claimed in claim 2 is characterized in that: wherein above-mentioned substrate is the multilager base plate of BGA.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB011293640A CN1170313C (en) | 2001-06-13 | 2001-06-13 | Multi-layer substrate of IC and arrangement method of holes on dielectric layers |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB011293640A CN1170313C (en) | 2001-06-13 | 2001-06-13 | Multi-layer substrate of IC and arrangement method of holes on dielectric layers |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1391272A CN1391272A (en) | 2003-01-15 |
| CN1170313C true CN1170313C (en) | 2004-10-06 |
Family
ID=4669117
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB011293640A Expired - Fee Related CN1170313C (en) | 2001-06-13 | 2001-06-13 | Multi-layer substrate of IC and arrangement method of holes on dielectric layers |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1170313C (en) |
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2001
- 2001-06-13 CN CNB011293640A patent/CN1170313C/en not_active Expired - Fee Related
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| Publication number | Publication date |
|---|---|
| CN1391272A (en) | 2003-01-15 |
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Granted publication date: 20041006 |