CN2896793Y - Circuit board arranged by non-signal through holes - Google Patents
Circuit board arranged by non-signal through holes Download PDFInfo
- Publication number
- CN2896793Y CN2896793Y CNU2006200066226U CN200620006622U CN2896793Y CN 2896793 Y CN2896793 Y CN 2896793Y CN U2006200066226 U CNU2006200066226 U CN U2006200066226U CN 200620006622 U CN200620006622 U CN 200620006622U CN 2896793 Y CN2896793 Y CN 2896793Y
- Authority
- CN
- China
- Prior art keywords
- signal
- perforation
- wiring board
- those
- core layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Structure Of Printed Boards (AREA)
Abstract
A circuit board that is applied with non-signal via array, which comprises a contact surface, a core layer and a plurality of cushions, wherein the cushions are positioned on the contact surface and the non-signal via array consists of a plurality of primary non-signal via holes and one secondary non-signal via holes. The said primary non-signal via holes penetrate the core layer and are in corresponding electrical connection with some of the said cushions. The secondary non-signal via hole penetrates the core layer and is provided among the said primary non-signal holes and the secondary non-signal via hole is not in electrical connection with the said cushions. Space between the secondary non-signal via hole and the said primary non-signal holes is equal to or less than 0.72 times the minimum space among the said some of the cushions that are in electrical connection with primary non-signal via holes. The non-signal via array provided by the utility model generates smaller spurious inductance value, thus noise disturbance during current switch can be reduced.
Description
Technical field
The utility model relates to a kind of wiring board, and particularly relevant for a kind of wiring board of using non-signal perforation arrangement mode.
Background technology
Generally speaking, existing in order to carrying and the wiring board (wiringboard) that is electrically connected a plurality of electronic components mainly be by a plurality of patterned conductive layers (patterned conductive layer) and a plurality of insulating barrier (insulating layer) be superimposed constitute.Wherein, these patterned conductive layers are that definition forms through lithography by copper foil layer (copper foil), and these insulating barriers are to be disposed at respectively between adjacent these patterned conductive layers, in order to isolate these patterned conductive layers.In addition, be to be electrically connected to each other between these overlapped patterned conductive layers through conducting electricity duct (conductive via) or conductive through hole (throughvia is hereinafter to be referred as perforation).In addition, also configurable various electronic components on the surface of wiring board (for example active element or passive component), and reach the purpose of electronic signal transmission (electrical signal propagation) by the wiring board internal wiring.
Please refer to Fig. 1, it illustrates the side-looking generalized section of existing a kind of wiring board.Existing wiring board 100 comprises a plurality of insulating barriers 110, a plurality of patterned conductive layer 120, a plurality of perforation 130, a plurality of conductions duct 140 and a plurality of connection pads 150.One of them of these insulating barriers 110 is core layer 110 (a), and these perforations 130 comprise signal perforation, power supply perforation and ground connection perforation, its run through core layer 110 (a) and with the part these connection pad 150 corresponding electrical connections.One of them of these insulating barriers 110 except core layer 110 (a) run through in each conduction duct 140, and these patterned conductive layers 120 be interconnected with these insulating barriers 110, and these patterned conductive layers 120 at least wherein two are one of them and electrical connections mutually at least by these perforations 130 or these conduction ducts 140.
The configuration mode of the power supply perforation of these perforations 130 (or ground connection perforation) and quantity are based on size of current that these power supply perforations (or ground connection perforation) to the circuit between corresponding these connection pads 150 that are electrically connected with it can carry and design requirement and determine.Yet; the power supply perforation of these perforations 130 of existing line plate 100 (or ground connection perforation) usually can because of circuit design with the clustering adjacent one another are of a certain number in core layer; therefore existing wiring board 100 is by these power supply perforations (or ground connection perforation) transmission current the time; will produce bigger stray inductance (parasitic inductance) value, thereby the noise jamming when causing current switching is comparatively serious.
The utility model content
The purpose of this utility model provides a kind of wiring board, and it has non-signal perforation and arranges to reduce the stray inductance value between the non-signal perforation.
For reaching above-mentioned or other purpose, the utility model proposes a kind of wiring board, it comprises a core layer, a plurality of connection pad and at least one non-signal perforation arrangement.These connection pads are disposed at the side top of core layer.Non-signal perforation is arranged and is comprised a plurality of first non-signal perforation and one second non-signal perforation.These first non-signal perforations run through core layer and with part these connection pads corresponding electrical connection.The second non-signal perforation runs through core layer, the second non-signal perforation is disposed between these first non-signal perforations and is not electrically connected with these connection pads, and the second non-signal perforation and the spacing of these first non-signal perforations are less than or equal to 0.72 times of minimum spacing of corresponding these connection pads of part that are electrically connected to these first non-signal perforations.
For above-mentioned and other purpose, feature and advantage of the present utility model can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Fig. 1 illustrates the side-looking generalized section of existing a kind of wiring board;
Fig. 2 illustrates the side-looking generalized section of a kind of wiring board of the utility model one embodiment;
Fig. 3 illustrate Fig. 2 partial component look up cross-sectional schematic;
Fig. 4 illustrates the cross-sectional schematic of looking up that the non-signal perforation of Fig. 2 arranges;
Fig. 5 illustrates the side-looking generalized section of the chip packing-body of another embodiment of the utility model.
Description of reference numerals
100,200: wiring board
110,240: insulating barrier
110 (a), 210: core layer
120,270: patterned conductive layer
130: perforation
140,250: the conduction duct
150,220: connection pad
230: non-signal perforation is arranged
232: the first non-signal perforations
234: the second non-signal perforations
260: the signal perforation
280: welding cover layer
290: soldered ball
L1, L2: spacing
C: chip
P: chip packing-body
S: contact face
Embodiment
Fig. 2 illustrates the side-looking generalized section of a kind of wiring board of the utility model one embodiment, Fig. 3 illustrate Fig. 2 partial component look up cross-sectional schematic.Please refer to Fig. 2 and Fig. 3, the wiring board 200 of present embodiment for example is circuit board (circuit board) or base plate for packaging (package substrate), and it comprises a core layer 210, a plurality of connection pad 220 and at least one non-signal perforation arrangement 230.These connection pads 220 are disposed at the side top of core layer 210, and in the present embodiment, the contact face S that these connection pads 220 are disposed at wiring board 200 goes up and the electronic installation (not illustrating) in order to be electrically connected to next level.
Non-signal perforation is arranged 230 and is comprised a plurality of first non-signal perforation 232 and one second non-signal perforation 234.These first non-signal perforations 232 run through core layer 210 and with the part these connection pad 220 corresponding electrical connections.The second non-signal perforation 234 runs through core layer 210, the second non-signal perforation 234 is disposed between these first non-signal perforations 232 and is not electrically connected with these connection pads 220, and the second non-signal perforation 234 and the spacing L1 of these first non-signal perforations 232 are less than or equal to 0.72 times of minimum spacing L2 of corresponding these connection pads 220 of part that are electrically connected to these first non-signal perforations 232.This mandatory declaration be, Fig. 3 only illustrates among Fig. 2 these first non-signal perforations 232 of part and one second non-signal perforation 234, and with these connection pads 220 of these first non-signal perforation 232 corresponding electrical connections.
In addition, these first non-signal perforations 232 can be the power supply perforation, and the second non-signal perforation 234 can be the ground connection perforation; Perhaps, these first non-signal perforations 232 can be the ground connection perforation, and the second non-signal perforation 234 can be the power supply perforation.In other words, these the first non-signal perforations 232 and the second non-signal perforation 234 are different types of non-signal perforation.Please refer to Fig. 4, its non-signal perforation that illustrates Fig. 2 is arranged looks up cross-sectional schematic, and for the purpose of clear the differentiation, Fig. 4 illustrates the second non-signal perforation 234 and is solid black person.The solid black that note that Fig. 4 indicates the only signal for being easy to differentiate, and is not to be solid body in order to limit the second non-signal perforation 234 from the section finding of looking up of Fig. 2.As shown in Figure 4, arrange in 230, have one second non-signal perforation 234 among a plurality of first non-signal perforation 232 at a non-signal perforation.
Refer again to Fig. 2 and Fig. 3, when the wiring board 200 of present embodiment and during transmission current by these first non-signal perforations 232 and the second non-signal perforation 234, because these the first non-signal perforations 232 and the second non-signal perforation 234 are different types of non-signal perforation, so equivalent inductance (equivalent inductance) value of non-signal perforation arrangement 230 deducts coupling inductance (coupling inductance) value between the second non-signal perforation 234 and these the first non-signal perforations 232 again for these first non-signal perforation 232 inductance value own add second non-signal perforation 234 inductance value own.In addition, the direction of 232 transmission currents of these first non-signal perforations is opposite with the direction of 234 transmission currents of the second non-signal perforation usually, so more can strengthen the coupling inductance between these the first non-signal perforations 232 and the second non-signal perforation 234, and then reduce the equivalent inductance of non-signal perforation arrangement 230.Therefore, it is less that the non-signal perforation of the wiring board 200 of present embodiment is arranged the 230 stray inductance values that produced, and then the noise jamming can reduce current switching the time.
The wiring board 200 of present embodiment more comprises a plurality of insulating barriers 240, a plurality of conductions duct 250, a plurality of signal perforation 260 and a plurality of patterned conductive layers 270.Above-mentioned core layer 210 can be considered one of them of these insulating barriers 240, and the material of these insulating barriers 240 for example is glass epoxy resin (FR-4) or epoxy resin (epoxy resin).In addition, one of them of these insulating barriers 240 except core layer 210 run through in each conduction duct 250 (its material for example for copper), and these signal perforations 260 then run through core layer 210.In addition, for example definition forms these patterned conductive layers 270 through lithography by copper foil layer, these patterned conductive layers 270 be interconnected with these insulating barriers 240, and these patterned conductive layers 270 at least wherein two are one of them and electrical connections mutually at least by these first non-signal perforation 232, second non-signal perforations 234, these signal perforations 260 or these conduction ducts 250.Moreover wiring board 200 more comprises a welding cover layer 280, be disposed at the side top (in the present embodiment, welding cover layer 280 is disposed on the contact face S of wiring board 200) of core layer 210, and welding cover layer 280 exposes these connection pads 220.
Please refer to Fig. 5, it illustrates the side-looking generalized section of the chip packing-body of another embodiment of the utility model.The chip packing-body P of present embodiment comprises the wiring board 200 (being base plate for packaging at this) of a chip C and the foregoing description.Chip C is disposed on the another side with respect to the contact face S of wiring board 200, and in other words, chip C and these connection pads 220 lay respectively at the top, both sides of core layer 210.In addition, chip C is electrically connected with wiring board 200 by a plurality of projection B, and these connection pads 220 of wiring board 220 can be electrically connected to the electronic installation (not illustrating) of next level by a plurality of soldered balls (solder ball) 290.Mandatory declaration be that chip C also can be electrically connected with wiring board 200 by many bonding wires, but do not illustrate with drawing.
In sum, wiring board of the present utility model is by these first non-signal perforations and the second non-signal perforation and during transmission current, because these the first non-signal perforations and the adjacent second non-signal perforation are different types of non-signal perforation, so the non-signal perforation of wiring board of the present utility model arrange the stray inductance value that produces less, and then the noise jamming can reduce current switching the time.
Though the utility model discloses as above with preferred embodiment; right its is not in order to limit the utility model; any those skilled in the art; in not breaking away from spirit and scope of the present utility model; when can doing a little change and retouching, therefore protection range of the present utility model with appending claims the person of being defined be as the criterion.
Claims (10)
1. wiring board is characterized in that comprising:
One core layer;
A plurality of connection pads are disposed at above the side of this core layer; And
At least one non-signal perforation is arranged, and comprising:
The a plurality of first non-signal perforation, run through this core layer and with part those connection pads corresponding electrical connection; And
One second non-signal perforation, run through this core layer, this second non-signal perforation is disposed between those first non-signal perforations and is not electrically connected with those connection pads, and this second non-signal perforation and the spacing of those first non-signal perforations are less than or equal to 0.72 times of minimum spacing of corresponding those connection pads of part that are electrically connected to those first non-signal perforations.
2. wiring board as claimed in claim 1 is characterized in that, those first non-signal perforations are the power supply perforation, and this second non-signal perforation is the ground connection perforation.
3. wiring board as claimed in claim 1 is characterized in that, those first non-signal perforations are the ground connection perforation, and this second non-signal perforation is the power supply perforation.
4. wiring board as claimed in claim 1 is characterized in that, the direction of those first non-signal perforation institute transmission currents is opposite with the direction of this second non-signal perforation institute transmission current.
5. wiring board as claimed in claim 1 is characterized in that, more comprises:
A plurality of insulating barriers, this core layer are one of those insulating barriers;
A plurality of conductions duct, respectively one of those insulating barriers except this core layer are run through in this conduction duct;
A plurality of signal perforations run through this core layer; And
A plurality of patterned conductive layers, with those insulating barriers be interconnected, at least two of those patterned conductive layers are mutual electrical connections by at least one of those first non-signal perforations, this second non-signal perforation, those signal perforations or those conduction ducts.
6. wiring board as claimed in claim 1 is characterized in that, this wiring board is circuit board or base plate for packaging.
7. wiring board as claimed in claim 1 is characterized in that this wiring board more comprises a welding cover layer, be disposed at the side top of this core layer, and this welding cover layer exposes those connection pads.
8. wiring board as claimed in claim 1 is characterized in that, this wiring board is a base plate for packaging, in order to be electrically connected to a chip.
9. wiring board as claimed in claim 8 is characterized in that this chip is electrically connected with this chip by a plurality of projections.
10. wiring board as claimed in claim 8 is characterized in that this chip is electrically connected with this chip by many bonding wires.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2006200066226U CN2896793Y (en) | 2006-03-02 | 2006-03-02 | Circuit board arranged by non-signal through holes |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2006200066226U CN2896793Y (en) | 2006-03-02 | 2006-03-02 | Circuit board arranged by non-signal through holes |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN2896793Y true CN2896793Y (en) | 2007-05-02 |
Family
ID=38066365
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNU2006200066226U Expired - Lifetime CN2896793Y (en) | 2006-03-02 | 2006-03-02 | Circuit board arranged by non-signal through holes |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN2896793Y (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104637926A (en) * | 2015-01-06 | 2015-05-20 | 武汉新芯集成电路制造有限公司 | Inductor in three-dimensional stacked packaged chip and preparation method thereof |
| CN108029189A (en) * | 2015-09-11 | 2018-05-11 | Zf 腓德烈斯哈芬股份公司 | Multi-functional high-current circuit plate |
-
2006
- 2006-03-02 CN CNU2006200066226U patent/CN2896793Y/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104637926A (en) * | 2015-01-06 | 2015-05-20 | 武汉新芯集成电路制造有限公司 | Inductor in three-dimensional stacked packaged chip and preparation method thereof |
| CN108029189A (en) * | 2015-09-11 | 2018-05-11 | Zf 腓德烈斯哈芬股份公司 | Multi-functional high-current circuit plate |
| CN108029189B (en) * | 2015-09-11 | 2020-08-25 | Zf 腓德烈斯哈芬股份公司 | Multifunctional high-current circuit board |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20070502 |
|
| EXPY | Termination of patent right or utility model |