CN2518221Y - Semiconductor structured base plate - Google Patents
Semiconductor structured base plate Download PDFInfo
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- CN2518221Y CN2518221Y CN 02202170 CN02202170U CN2518221Y CN 2518221 Y CN2518221 Y CN 2518221Y CN 02202170 CN02202170 CN 02202170 CN 02202170 U CN02202170 U CN 02202170U CN 2518221 Y CN2518221 Y CN 2518221Y
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- baseplate
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Abstract
A semi-conductor mounting substrate is to use the laminating method to complete the internal laminated circuit structure and to use the lay-up method to complete the external lay-up circuit structure, which can provide a semi-conductor mounting substrate having high density and small interval, in particular to a geode-cladding lattice arrayed mounting substrate having high density and small interval. In addition, a plurality of projection pads on the top of the semi-conductor mounting substrate is classified into a power-source/grounding projection pad, a first signal projection pad and a second signal projection pad; wherein, the power-source/grounding projection pad is disposed at the center of the substrate, the first signal projection pad is arranged at the outer circumference of the power-source/grounding projection pad and the second signal projection pad is arranged at the outer circumference of the first signal projection pad.
Description
Technical field
The utility model relates to a kind of semiconductor baseplate, and particularly relevant for a kind of semiconductor baseplate that is applied to crystal covering type sphere grid array formula.
Background technology
Flip Chip (Flip Chip, F/C) be the structure packing technique that often is applied to wafer size structure dress, be active surface (active surface) the configuration weld pad (pad) of employing face matrix-style (area array) at wafer (chip), and on weld pad, form projection (bump), in order to connecting wafer be connected carrier (carrier), so have the structure of dwindling dress area, improve structure dress density, and shorten advantage such as signal transmission path.Because rigid substrate (rigidsubstrate) can provide the circuit of high density and high number of contacts to arrange simultaneously, therefore is the carrier that many crystal covered packages often adopt.And the production method of rigid substrate mainly can be divided into lay-up method (laminate) and lamination method (build-up) two big classes.
The making principle of lay-up method is on single sided board with copper foil layer or double sided board, these copper foil layers of difference patterning, so as to forming the conductor layer of patterning, and between each panel, add middle junction plywood (bonding sheet), put into again between two flat boards on the big press, heat simultaneously and pressurize, so as to curing middle junction plywood and in conjunction with each panel, then take out again and carry out machine drilling, and plated-through-hole (Plating Through Hole, PTH) step is led to connector in order to form the plating that runs through each panel simultaneously, and is electrically connected each conductor layer with it.
The making principle of lamination method be with one the insulation sandwich layer (core) be basic unit, and the insulation sandwich layer the surface form insulating barrier and patterning conductor layer successively, and be to utilize conducting connector (via) as electrically connecting between each conductor layer, wherein the technology of conducting connector comprises that the mode of utilizing sensitization pore-forming (Photo-Via), laser hole burning (Laser Ablation) and plasma pit on-mechanical formulas such as (Plasma Etching) to hole forms after the hole, insert electric conducting material or plated conductive material again within the hole, in order to form conductive plunger.
Please refer to Fig. 1, it is the known generalized section of covering geode lattice array baseplate made from lamination method.Covering geode lattice array baseplate 100 is as the basis with an insulation sandwich layer 110, and form conductor layer 112 with regard to the copper foil layer that had originally on the two sides of patterning insulation sandwich layer 110, and utilize the mode of machine drilling and electroplating technology to form the logical connector 114 of plating, so as to electrically connecting two-layer conductor layer 112 up and down, then form insulating barrier 120 respectively on conductor layer 112, and in the mode of on-mechanical boring, comprise the sensitization pore-forming, the mode of laser hole burning and plasma pit, and electroplating technology forms conducting connector 140a, 140b, so as to connecting conductor layer 112 and conductor layer 130a respectively, and two adjacent conductor layer 130a, 130b, conductor layer 130a wherein, 130b utilizes little shadow and electroplating technology to be formed at insulating barrier 120a respectively, on the 120b, utilize anti-layer (solder mask) 150 to expose the conductor layer 130b on part top layer at last respectively, in order to bump pads (the bump pad) 132 that form the top and the solder ball pad (solder ball pad) 134 of below.
(flip chip ball grid array, FCBGA) structure dress when bump pitch (bump pitch) during less than 240 microns, must use 40 microns/40 microns (live width/line-spacing) to carry out line design at covering geode lattice array.Because the manufacturing technology of lamination method (build-up) can be produced the baseplate of high density and low tone distance, therefore at semiconductor subassembly constantly under the situation of high pin position (High Pin Count) development, utilizing lamination method to make to cover geode lattice array baseplate has become main flow.The present geode lattice array baseplate that covers is six laminates (2+2+2) based on the lamination method made, if the density of projection increases, then needs to increase the number of lamination to make things convenient for the layout of circuit.Yet,, utilize the baseplate of lamination method made to have the low and high shortcoming of manufacturing cost of the qualification rate of manufacturing though cover the advantage that geode lattice array baseplate has high density and low tone distance with what lamination method was made.
The utility model content
The purpose of this utility model is to provide a kind of semiconductor baseplate and technology thereof, it utilizes lay-up method to replace the conductor layer and the insulating barrier of the part internal layer of original lamination method made, cover the manufacturing qualification rate of geode lattice array baseplate so as to raising, and reduce the manufacturing cost of covering geode lattice array baseplate simultaneously.
Based on above-mentioned purpose of the present utility model, the utility model provides a kind of semiconductor baseplate, has a lamination line construction, it comprises that multi-layered patterned inside conductor layer, multilayer inner insulating layer and a plurality of plating lead to connector, wherein inside conductor layer and inner insulating layer are interlaced superimposed, the logical connector of plating then runs through inside conductor layer and inner insulating layer simultaneously, and the inside conductor layer is electrically connected to each other via the logical connector of plating.Semiconductor baseplate has more a lamination line construction, comprise the outer conductor layer of two layer patternizations, two layers of external insulation layer and a plurality of conducting connector, wherein outer conductor layer and external insulation layer are disposed at the two sides of lamination line construction respectively, and the conducting connector runs through external insulation layer respectively, and the outer conductor layer electrically connects with the inside conductor layer of lamination line construction mutually via the conducting connector.In addition, semiconductor baseplate more comprises two welding cover layers, is disposed at respectively on the corresponding external insulation layer and outer conductor layer, and exposes the formed a plurality of joint sheet of outer conductor layer, in order to as bump pads and solder ball pad.
Description of drawings
Fig. 1 is the known generalized section of covering geode lattice array baseplate made from lamination method;
Fig. 2 is the generalized section of the semiconductor baseplate of preferred embodiment of the present utility model;
Fig. 3 is the partial schematic diagram of wire laying mode of the conductor layer No.1 230 of Fig. 2;
Fig. 4 is the partial schematic diagram of wire laying mode of the 6th conductor layer 236 of Fig. 2;
Fig. 5 is the schematic diagram of joint sheet (bump pads) layout type of the semiconductor baseplate of Fig. 2.
100: semiconductor baseplate 110: the insulation sandwich layer
112: conductor layer 114: the logical connector of plating
120a, 120b: insulating barrier 130a, 130b: conductor layer
132: bump pads 134: solder ball pad
140a, 140b: conducting connector 150: anti-layer
200: semiconductor baseplate 202: the insulation sandwich layer
204,206,212,214,230,236: conductor layer
208,210,228,234: insulating barrier
216: the logical connector 218 of plating: lamination line construction
220,222: surface 224,226: lamination line construction
232,238: conducting connector 240,242: anti-layer
244: joint sheet (bump pads) 246: joint sheet (solder ball pad)
300,400: substrate edges 302,402: Waffer edge
304: joint sheet (bump pads) 306,406: conducting connector
308,408: lead 404: joint sheet (solder ball pad)
310,320,410,420: power supply/ground connection bump pads
330,340,430,440: the first signal bump pads
350,360,450,460: the secondary signal bump pads
Embodiment
Please refer to Fig. 2, it is the generalized section of the semiconductor baseplate of preferred embodiment of the present utility model.Semiconductor baseplate 200 utilizes an insulation sandwich layer 202, its material comprises glass epoxide base resin, bismaleimide and epoxy resin etc., upper and lower surface at insulation sandwich layer 202 has the conductor layer 204,206 of patterning respectively, and conductor layer 204,206 comprises that the copper foil layer that originally was disposed at the surface of insulation sandwich layer 202 by patterning one is constituted.Then, the insulation board 208 of the conductor layer 212 that single face has patterning is provided, and single face has the insulation board 210 of the conductor layer 214 of patterning, utilize lay-up method that above-mentioned each layer positioned pressing, utilize the mode and the electroplating technology of machine drilling to form the logical connector 216 of plating again, so as to electrically connecting the conductor layer 204,206,212,214 of each layer up and down, and finish inner lamination line construction 218.
Please equally with reference to figure 2, utilize lay-up method to finish after the lamination line construction 218 of semiconductor baseplate 200, then utilize Layer increasing method to form a lamination line construction 224 respectively at the upper surface 220 and the lower surface 222 of lamination line construction 218,226, wherein lamination line construction 224 is by an insulating barrier 228, one patterning conductor layer 230 and a plurality of conducting connector 232 constitute, the lamination line construction 226 of lower floor then has identical structure with the lamination line construction 224 on upper strata, is by an insulating barrier 234 equally, one patterned conductive layer 236 and a plurality of conducting connector 238 constitute.Lamination line construction 224 with the upper strata is an example, at first form the upper surface 220 of insulating barrier 228 in lamination line construction 218, and the mode of utilizing the on-mechanical formula to hole, comprise in modes such as sensitization pore-forming, laser hole burning and plasma pits, and electroplating technology, form conducting connector 232, and when electroplating technology, form conductor layer 230 simultaneously, and utilize the mode patterning conductor layer 230 of little shadow, make that conductor layer 230 is able to electrically connect mutually with the conductor layer 212 of lamination line construction 218 via conducting connector 232.Because on-mechanical formula boring (as sensitization pore-forming, laser hole burning and plasma pit) formed aperture is less than the formed aperture of machine drilling, therefore, the external diameter of conductive plunger 232,238 will be less than the external diameter of the logical connector 216 of plating.
Please equally with reference to figure 2, then on insulating barrier 228 and conductor layer 230, form an anti-layer 240, it exposes part conductor layer 230, to form joint sheet 244, and on the insulating barrier 234 of lower floor and conductor layer 236, form an anti-layer 242, expose part conductor layer 236 equally, the surface of the feasible part conductor layer 236 that exposes forms joint sheet 246.When semiconductor baseplate 200 is applied to cover geode lattice array structure dress, the joint sheet 244 on upper strata is as the bump pads (bump pad) of the chip-covered boss of connecting wafer, and the joint sheet 246 of lower floor then conduct is planted the solder ball pad (solder ballpad) that meets (plant) soldered ball (solder ball).
Please equally with reference to figure 2, preferred embodiment of the present utility model is an example with the semiconductor baseplate of six laminates, under the situation that projection density continues to increase, can suitably increase the number of inner lamination or outside lamination, so as to making things convenient for the layout of circuit.Therefore, semiconductor baseplate 200 of the present utility model is finished after the line construction of the overwhelming majority by lay-up method, the last lamination method of utilizing again forms the joint sheet 244,246 that is connected with the external world, as the bump pads of the chip-covered boss of connecting wafer, and plants the solder ball pad that connects soldered ball in order to respectively.Because the technology of lay-up method is very ripe, so make the internal wiring of semiconductor baseplate with lay-up method, utilize Layer increasing method to form outside line and joint sheet at last again, can significantly improve the manufacturing qualification rate of semiconductor baseplate, particularly cover the manufacturing qualification rate of geode lattice array baseplate, and can significantly reduce its manufacturing cost.
Preferred embodiment of the present utility model more proposes a kind of layout designs of bump pads, can be applicable to semiconductor baseplate, please also refer to Fig. 2, Fig. 3, Fig. 4, Fig. 5, wherein Fig. 3 is the partial schematic diagram of wire laying mode of the conductor layer No.1 230 of Fig. 2, Fig. 4 is the partial schematic diagram of wire laying mode of the 6th conductor layer 236 of Fig. 2, and Fig. 5 is the schematic diagram of joint sheet (bump pads) layout type of the semiconductor baseplate of Fig. 2.As shown in Figure 5, the bump pads layout of semiconductor baseplate 200 is a matrix distribution, and wherein the joint sheet 244 of Fig. 2 is the bump pads 304 of Fig. 3, Fig. 5, and the joint sheet 246 of Fig. 2 then is the solder ball pad 404 of Fig. 4.Then as shown in Figure 3, it should be noted that, the utility model utilizes the joint sheet 304 of inner ring as power supply/ground connection bump pads 310,320, and the joint sheet 304 of centre circle is as the first signal bump pads 330,340, and the joint sheet 304 of outer ring is then as secondary signal bump pads 350,360.
The substrate edges 300 of semiconductor baseplate 200 and Waffer edge 302 are as shown in Figure 3, the power supply of inner ring of the present utility model/ground connection bump pads 310,320 utilizes conducting connector 306 (being the conducting connector 232 of Fig. 2) coiling (routing) downwards to privates layer 204 and the privates layer 206 of Fig. 2, middle two layers (privates layer 204 and privates layers 206) are as power/ground, for example with privates layer 204 as ground plane, privates layer 206 is then as bus plane.Then, wind the line downwards to joint sheet 246 (being the joint sheet 404 of Fig. 4) via the logical connector 216 of plating, the 5th conductor layer 214, conducting connector 238 (being the conducting connector 406 of Fig. 4) and the 6th conductor layer 236 (being the lead 408 of Fig. 4) successively again.
In addition, via the logical connector 216 of second conductor layer 212, plating, the 5th conductor layer 214, conducting connector 238 (being the conducting connector 406 of Fig. 4) and the 6th conductor layer 236 of conducting connector 306 (being the conducting connector 232 of Fig. 2), Fig. 2, lead 408 fan-outs (fan out) of utilizing the 6th conductor layer 236 again are to solder ball pad 404 (i.e. the 6th conductor layer 236 formed joint sheets 246) successively for the first signal bump pads 330,340 of Fig. 3.
In addition, 350,360 of the secondary signal bump pads of Fig. 3 are to utilize the lead 308 of the conductor layer No.1 230 of Fig. 2 to fan out to earlier outside the Waffer edge 302, lead to the joint sheet 246 (being the solder ball pad 404 of Fig. 4) of connector 216, the 5th conductor layer 214, conducting connector 238 (being the conducting connector 406 of Fig. 4) and the 6th conductor layer 236 (being the lead 408 of Fig. 4) more successively via conducting connector 306 (being the conducting connector 232 of Fig. 2), second conductor layer 212, plating.
From the above mentioned, the wire laying mode of conductor package substrate of the present utility model mainly is the lead that utilizes the conductor layer No.1 of top layer, to surpass the edge of wafer than the secondary signal weld pad fan-out of outer ring earlier, wind the line downwards again to solder ball pad, and will wind the line downwards to the 6th conductor layer of the bottom earlier than the first signal weld pad of inner ring, the lead that utilizes the 6th conductor layer again is with the edge of the first signal weld pad fan-out above wafer.When conductor layer No.1 and the 6th conductor layer can't provide enough wiring space, just utilize the lead auxiliary wiring of the second, the 4th and the 5th conductor layer of internal layer, wind the line downwards respectively and fan out to the solder ball pad of the 6th conductor layer so as to bump pads with conductor layer No.1.
In sum, the utility model utilizes lay-up method to finish after the inner lamination line construction, utilizes lamination method to finish outside lamination line construction again, the semiconductor baseplate of high density low tone distance can be provided, and particularly cover geode lattice array baseplate.Because the technology of lay-up method is very ripe, when utilizing lay-up method to finish the most of line construction of semiconductor baseplate, can improves the manufacturing qualification rate of semiconductor baseplate, and reduce the manufacturing cost of semiconductor baseplate.
In addition, the utility model more provides a kind of semiconductor baseplate, its bump pads with its end face is divided into power supply/ground connection bump pads, the first signal bump pads and secondary signal bump pads, wherein these power supplys/ground connection bump pads is positioned at substrate center, and these first signal bump pads are distributed in these power supplys/ground connection bump pads periphery, these secondary signal bump pads then more are distributed in the periphery of these first signal bump pads, and two layers of centres that utilize six layer conductor layers are respectively as power/ground.
Claims (7)
1, a kind of semiconductor baseplate is characterized in that, comprises at least:
One lamination line construction has a first surface and a corresponding second surface, comprising:
A plurality of inside conductor layers of patterning, overlapped successively,
A plurality of inner insulating layers are disposed at respectively between two adjacent those inside conductor layers, in order to isolating those inside conductor layers, and interlaced superimposed with those inside conductor layers, and
Connector is led in a plurality of platings, runs through those inner insulating layers and those inside conductor layers respectively simultaneously, and wherein those inside conductor layers are electrically connected to each other via the logical connector of those platings; And
One lamination line construction comprises:
One first external insulation layer and one second external insulation layer are disposed at this first and this second of this lamination line construction respectively,
One first outer conductor layer of patterning and one second outer conductor layer are disposed at the surface of this first external insulation layer and this second external insulation layer respectively, and have a plurality of first joint sheets and a plurality of second joint sheet respectively,
A plurality of first conducting connectors and a plurality of second conducting connector, run through this first external insulation layer and this second external insulation layer respectively, wherein this first outer conductor layer and this second outer conductor layer electrically connect with those inside conductor layers mutually via those first conducting connectors and those second conducting connectors respectively, and those first conducting connectors and those second conducting plug's outer diameter are all less than the logical plug's outer diameter of those platings.
2, semiconductor baseplate as claimed in claim 1 is characterized in that, it more comprises one first anti-layer, and it is disposed on this first external insulation layer and this first outer conductor layer, and exposes those first joint sheets.
3, semiconductor baseplate as claimed in claim 1 is characterized in that, it more comprises one second anti-layer, and it is disposed on this second external insulation layer and this first outer conductor layer, and exposes those second joint sheets.
4, semiconductor baseplate as claimed in claim 1 is characterized in that, this semiconductor baseplate is as a crystal covering type sphere grid array baseplate.
5, semiconductor baseplate as claimed in claim 4 is characterized in that, those first joint sheets are as bump pads, and those second joint sheets are as solder ball pad.
6, semiconductor baseplate as claimed in claim 1 is characterized in that, the material of those inner insulating layers is selected from a kind of material in the group that is made up of glass epoxide base resin, bismaleimide and epoxy resin.
7, semiconductor baseplate as claimed in claim 1 is characterized in that, those inside conductors constitute via definition one copper foil layer respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02202170 CN2518221Y (en) | 2002-01-28 | 2002-01-28 | Semiconductor structured base plate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02202170 CN2518221Y (en) | 2002-01-28 | 2002-01-28 | Semiconductor structured base plate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN2518221Y true CN2518221Y (en) | 2002-10-23 |
Family
ID=33684799
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 02202170 Expired - Fee Related CN2518221Y (en) | 2002-01-28 | 2002-01-28 | Semiconductor structured base plate |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN2518221Y (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7253526B2 (en) | 2001-12-28 | 2007-08-07 | Via Technologies, Inc. | Semiconductor packaging substrate and method of producing the same |
-
2002
- 2002-01-28 CN CN 02202170 patent/CN2518221Y/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7253526B2 (en) | 2001-12-28 | 2007-08-07 | Via Technologies, Inc. | Semiconductor packaging substrate and method of producing the same |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C19 | Lapse of patent right due to non-payment of the annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |