CN1324697C - Semiconductor baseplate and its fabrication process - Google Patents
Semiconductor baseplate and its fabrication process Download PDFInfo
- Publication number
- CN1324697C CN1324697C CNB021028486A CN02102848A CN1324697C CN 1324697 C CN1324697 C CN 1324697C CN B021028486 A CNB021028486 A CN B021028486A CN 02102848 A CN02102848 A CN 02102848A CN 1324697 C CN1324697 C CN 1324697C
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Production Of Multi-Layered Print Wiring Board (AREA)
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Abstract
The present invention relates to a semiconductor base plate and a manufacture process thereof. After an inside lamination layer circuit structure is completed by a lamination layer method, an outside accumulation layer circuit structure is completed by an accumulation layer method; the present invention provides a semiconductor base plate with high density and small interval, particularly a crystal coated sphere grid array base plate with high density and small interval; in addition, a lug pad arranged on the top surface of the semiconductor base plate is divided into power supply / grounding lug pads, first signal lug pads and second signal lug pads, wherein the power supply / grounding lug pads are positioned in the center of the base plate, the first signal lug pads are distributed on the periphery of the power supply / grounding lug pads; the second signal lug pads are distributed on the periphery of the first signal lug pads.
Description
Technical field
The invention relates to a kind of semiconductor baseplate, and particularly relevant for a kind of semiconductor baseplate that is applied to the chip upside-down mounting type ball grid array.
Technical background
Flip chip technology (fct) (Flip Chip, F/C) be the structure packing technique that often is applied to chip size structure dress, employing face matrix-style (area array) is at active surface (active surface) the configuration weld pad (pad) of chip (chip), and on weld pad, form projection (bump), in order to connect chip and to be connected carrier (carrier), so have the structure of dwindling dress area, improve structure dress density, and shorten advantage such as signal transmission path.Because rigid substrate (rigid substrate) can provide the circuit of high density and high number of contacts to arrange simultaneously, therefore be the carrier that many flip-chip structure dresses often adopt.And the production method of rigid substrate mainly can be divided into lay-up method (laminate) and lamination method (build-up) two big classes.
The making principle of lay-up method is on single sided board with copper foil layer or double sided board, these copper foil layers of difference patterning, whereby to form the conductor layer of patterning, and between each panel, add middle junction plywood (bonding sheet), put into again between two flat boards on the big press, heat simultaneously and pressurize, whereby to solidify the middle junction plywood in conjunction with each panel, then take out again and carry out machine drilling, and plated-through-hole (Plating Through Hole, PTH) step is led to connector in order to form the plating that runs through each panel simultaneously, and is electrically connected each conductor layer with it.
The making principle of lamination method is a basic unit with an insulation sandwich layer (core), and the insulation sandwich layer the surface form insulating barrier and patterning conductor layer in regular turn, and utilize conducting connector (via) between each conductor layer as electrically connecting, wherein the manufacture craft of conducting connector comprises that the mode of utilizing sensitization pore-forming (Photo-Via), laser hole burning (Laser Ablation) and plasma pit on-mechanical formulas such as (PlasmaEtching) to hole forms after the hole, insert electric conducting material or plated conductive material again within the hole, in order to form conductive plunger.
Please refer to Fig. 1, it is the generalized section of the known chip upside-down mounting type ball grid array baseplate made from lamination method.Chip upside-down mounting type ball grid array baseplate 100 insulate sandwich layer 110 as the basis with one, and the conductor layer 112 that forms with regard to the copper foil layer that had originally on the two sides of patterning insulation sandwich layer 110, and utilize the mode of machine drilling and electroplate the logical connector 114 of manufacture craft formation plating, whereby to electrically connect two-layer conductor layer 112 up and down, then form insulating barrier 120 respectively on conductor layer 112, and in the mode of on-mechanical boring, comprise the sensitization pore-forming, the mode of laser hole burning and plasma pit, and the plating manufacture craft forms conducting connector 140a, 140b, whereby to connect conductor layer 112 and conductor layer 130a respectively, and two adjacent conductor layer 130a, 130b, conductor layer 130a wherein, 130b utilizes little shadow respectively and electroplates manufacture craft and is formed at insulating barrier 120a, on the 120b, the last conductor layer 130b that also utilizes anti-layer (solder mask) 150 to expose the part top layer respectively is in order to bump pads (the bump pad) 132 above forming and the solder ball pad (solder ball pad) 134 of below.
(flip chip ball grid array, FCBGA) structure dress when bump pitch (bump pitch) during less than 240 microns, must use 40 microns/40 microns (live width/line-spacing) to carry out line design at the chip upside-down mounting type ball grid array.Because the manufacturing technology of lamination method (build-up) can be produced the baseplate of high density and low tone distance, therefore under the situation that semiconductor device constantly develops towards high pin position (High Pin Count), utilizing lamination method to make chip upside-down mounting type ball grid array baseplate has become main flow.Present chip upside-down mounting type ball grid array baseplate if the density of projection increases, then needs to increase the number of lamination to make things convenient for the layout of circuit based on six laminates (2+2+2) of lamination method made.Yet,, but utilize the baseplate of lamination method made to have the low and high shortcoming of manufacturing cost of the qualification rate of manufacturing though the chip upside-down mounting type ball grid array baseplate made from lamination method has the advantage of high density and low tone distance.
Summary of the invention
The object of the present invention is to provide a kind of semiconductor baseplate, utilize lay-up method to replace the conductor layer and the insulating barrier of the part internal layer of original lamination method made, whereby improving the manufacturing qualification rate of chip upside-down mounting type ball grid array baseplate, and reduce the manufacturing cost of chip upside-down mounting type ball grid array baseplate simultaneously.
Based on above-mentioned purpose of the present invention, the invention provides a kind of semiconductor baseplate, has a lamination line construction, it comprises that multi-layered patterned inside conductor layer, multilayer inner insulating layer and a plurality of plating lead to connector, wherein inside conductor layer and inner insulating layer are interlaced superimposed, the logical connector of plating then runs through inside conductor layer and inner insulating layer simultaneously, and the inside conductor layer is electrically connected to each other through the logical connector of plating.Semiconductor baseplate also has a lamination line construction, comprise the outer conductor layer of two layer patternizations, two layers of external insulation layer and a plurality of conducting connector, wherein outer conductor layer and external insulation layer are disposed at the two sides of lamination line construction respectively, and the conducting connector runs through external insulation layer respectively, and the outer conductor layer electrically connects with the inside conductor layer of lamination line construction mutually through the conducting connector.In addition, semiconductor baseplate also comprises two welding cover layers, be disposed at respectively on the corresponding external insulation layer and outer conductor layer, and expose the formed a plurality of joint sheet of outer conductor layer, and in order to as the bump pads preferred embodiment, and conjunction with figs., elaborate.
Description of drawings
Fig. 1 is the known generalized section of covering geode lattice array baseplate made from long-pending established law;
Fig. 2 is the generalized section of the semiconductor baseplate of preferred embodiment of the present invention;
Fig. 3 is the partial schematic diagram of wire laying mode of the conductor layer No.1 230 of Fig. 2;
Fig. 4 is the partial schematic diagram of wire laying mode of the 6th conductor layer 236 of Fig. 2;
Fig. 5 is the schematic diagram of joint sheet (bump pads) layout type of the semiconductor baseplate of Fig. 2.
Label declaration:
100: semiconductor baseplate 110: the insulation sandwich layer
112: conductor layer 114: the logical connector of plating
120a, 120b: insulating barrier 130a, 130b: conductor layer
132: bump pads 134: solder ball pad
140a, 140b: conducting connector 150: anti-layer
200: semiconductor baseplate 202: the insulation sandwich layer
204,206,212,214,230,236: conductor layer
208,210,228,234: insulating barrier
216: the logical connector 218 of plating: lamination line construction
220,222: surface 224,226: lamination line construction
232,238: conducting connector 240,242: anti-layer
244: joint sheet (bump pads) 246: joint sheet (solder ball pad)
300,400: substrate edges 302,402: chip edge
304: joint sheet (bump pads) 306,406: conducting connector
308,408: lead 404: joint sheet (solder ball pad)
310,320,410,420: power supply/ground connection bump pads
330,340,430,440: the first signal bump pads
350,360,450,460: the secondary signal bump pads
Embodiment
Please refer to Fig. 2, it is the generalized section of the semiconductor baseplate of preferred embodiment of the present invention.Semiconductor baseplate 200 utilizes an insulation sandwich layer 202, its material comprises glass epoxide base resin, two maleic acid vinegar imines and epoxy resin etc., upper and lower surface at insulation sandwich layer 202 has the conductor layer 204,206 of patterning respectively, and conductor layer 204,206 comprises that the copper foil layer that originally was disposed at the surface of insulation sandwich layer 202 by patterning one is constituted.Then, the insulation board 208 of the conductor layer 212 that single face has patterning is provided, and single face has the insulation board 210 of the conductor layer 214 of patterning, utilize lay-up method that above-mentioned each layer positioned pressing, utilize the mode of machine drilling again and electroplate manufacture craft and form the logical connector 216 of plating, whereby electrically connecting the conductor layer 204,206,212,214 of each layer up and down, and finish inner lamination line construction 218.
Please equally with reference to figure 2, utilize lay-up method to finish after the lamination line construction 218 of semiconductor baseplate 200, then utilize Layer increasing method to form a lamination line construction 224 respectively at the upper surface 220 and the lower surface 222 of lamination line construction 218,226, wherein lamination line construction 224 is by an insulating barrier 228, one patterning conductor layer 230 and a plurality of conducting connector 232 constitute, the lamination line construction 226 of lower floor then has identical structure with the lamination line construction 224 on upper strata, equally by an insulating barrier 234, one patterned conductive layer 236 and a plurality of conducting connector 238 constitute.Lamination line construction 224 with the upper strata is an example, at first form the upper surface 220 of insulating barrier 228 in lamination line construction 218, and the mode of utilizing the on-mechanical formula to hole, comprise in modes such as sensitization pore-forming, laser hole burning and electricity slurry pits, and plating manufacture craft, form conducting connector 232, and when electroplating manufacture craft, form conductor layer 230 simultaneously, and utilize the mode patterning conductor layer 230 of little shadow, make conductor layer 230 be passed through conducting connector 232 and electrically connect mutually with the conductor layer 212 of lamination line construction 218.Because formed aperture is less than the formed aperture of machine drilling in on-mechanical formula boring (as sensitization pore-forming, laser hole burning and electricity slurry pit), therefore, the external diameter of conductive plunger 232,238 will be less than the external diameter of the logical connector 216 of plating.
Please equally with reference to figure 2, then on insulating barrier 228 and conductor layer 230, form an anti-layer 240, it exposes part conductor layer 230, to form joint sheet 244, and on the insulating barrier 234 of lower floor and conductor layer 236, form an anti-layer 242, expose part conductor layer 236 equally, the surface of the feasible part conductor layer 236 that exposes forms joint sheet 246.When semiconductor baseplate 200 is applied to cover geode lattice array structure dress, the joint sheet 244 on upper strata is as the bump pads (bump pad) of the chip-covered boss that connects chip, and the joint sheet 246 of lower floor then conduct is planted the solder ball pad (solder ball pad) that meets (plant) soldered ball (solder ball).
Please equally with reference to figure 2, preferred embodiment of the present invention is an example with the semiconductor baseplate of six laminates, under the situation that projection density continues to increase, can suitably increase the number of inner lamination or outside lamination, whereby to make things convenient for the layout of circuit.Therefore, semiconductor baseplate 200 of the present invention relies on lay-up method to be finished after the line construction of the overwhelming majority, the last lamination method of utilizing again forms and the extraneous joint sheet 244,246 that is connected, in order to the bump pads of the chip-covered boss of conduct connection chip respectively, and plants the solder ball pad that connects soldered ball.Because the technology of lay-up method is very ripe, so make the internal wiring of semiconductor baseplate with lay-up method, utilize Layer increasing method to form outside line and joint sheet at last again, can significantly improve the manufacturing qualification rate of semiconductor baseplate, particularly cover the manufacturing qualification rate of geode lattice array baseplate, and can significantly reduce its manufacturing cost.
Preferred embodiment of the present invention proposes a kind of layout designs of bump pads, can be applicable to semiconductor baseplate, please also refer to Fig. 2,3,4,5, wherein Fig. 3 is the partial schematic diagram of wire laying mode of the conductor layer No.1 230 of Fig. 2, Fig. 4 is the partial schematic diagram of wire laying mode of the 6th conductor layer 236 of Fig. 2, and Fig. 5 is the schematic diagram of joint sheet (bump pads) layout type of the semiconductor baseplate of Fig. 2.As shown in Figure 5, the bump pads layout of semiconductor baseplate 200 is a matrix distribution, and wherein the joint sheet 244 of Fig. 2 is Fig. 3,5 bump pads 304, and the joint sheet 246 of Fig. 2 then is the solder ball pad 404 of Fig. 4.Then as shown in Figure 3, it should be noted that, the present invention utilizes the joint sheet 304 of inner ring as power supply/ground connection bump pads 310,320, and the joint sheet 304 of centre circle is as the first signal bump pads 330,340, and the joint sheet 304 of outer ring is then as secondary signal bump pads 350,360.
The substrate edges 300 of semiconductor baseplate 200 and chip edge 302 are as shown in Figure 3, the power supply of inner ring of the present invention/ground connection bump pads 310,320 utilizes conducting connector 306 (being the conducting connector 232 of Fig. 2) coiling (routing) downwards to privates layer 204 and the privates layer 206 of Fig. 2, middle two layers (privates layer 204 and privates layers 206) are as power/ground, for example with privates layer 204 as ground plane, privates layer 206 is then as bus plane.Then, wind the line downwards to joint sheet 246 (being the joint sheet 404 of Fig. 4) through the logical connector 216 of plating, the 5th conductor layer 214, conducting connector 238 (being the conducting connector 406 of Fig. 4) and the 6th conductor layer 236 (being the lead 408 of Fig. 4) in regular turn again.
In addition, the first signal bump pads 330,340 of Fig. 3 is passed through the logical connector 216 of second conductor layer 212, plating, the 5th conductor layer 214, conducting connector 238 (being the conducting connector 406 of Fig. 4) and the 6th conductor layer 236 of conducting connector 306 (being the conducting connector 232 of Fig. 2), Fig. 2 in regular turn, and lead 408 fan-outs (fan out) of utilizing the 6th conductor layer 236 again are to solder ball pad 404 (i.e. the 6th conductor layer 236 formed joint sheets 246).
In addition, 350,360 of the secondary signal bump pads of Fig. 3 are to utilize the lead 308 of the conductor layer No.1 230 of Fig. 2 to fan out to earlier outside the chip edge 302, pass through the joint sheet 246 (being the solder ball pad 404 of Fig. 4) of conducting connector 306 (being the conducting connector 232 of Fig. 2), second conductor layer 212, the logical connector 216 of plating, the 5th conductor layer 214, conducting connector 238 (being the conducting connector 406 of Fig. 4) and the 6th conductor layer 236 (being the lead 408 of Fig. 4) more in regular turn.
From the above mentioned, the wire laying mode of conductor package substrate of the present invention mainly utilizes the lead of the conductor layer No.1 of top layer, to surpass the edge of chip than the secondary signal weld pad fan-out of outer ring earlier, wind the line downwards again to solder ball pad, and will wind the line downwards to the 6th conductor layer of the bottom earlier than the first signal weld pad of inner ring, the lead that utilizes the 6th conductor layer again is with the edge of the first signal weld pad fan-out above chip.When conductor layer No.1 and the 6th conductor layer can't provide enough wiring space, just utilize the lead auxiliary wiring of the second, the 4th and the 5th conductor layer of internal layer, whereby the bump pads of conductor layer No.1 is wound the line downwards respectively and fan out to the solder ball pad of the 6th conductor layer.
In sum, the present invention utilizes lay-up method to finish after the inner lamination line construction, utilizes lamination method to finish outside lamination line construction again, the semiconductor baseplate of high density low tone distance can be provided, and particularly cover geode lattice array baseplate.Because the technology of lay-up method is very ripe, when utilizing lay-up method to finish the most of line construction of semiconductor baseplate, can improves the manufacturing qualification rate of semiconductor baseplate, and reduce the manufacturing cost of semiconductor baseplate.
In addition, the present invention also provides a kind of semiconductor baseplate, its bump pads with its end face is divided into power supply/ground connection bump pads, the first signal bump pads and secondary signal bump pads, wherein these power supplys/ground connection bump pads is positioned at substrate center, and these first signal bump pads are distributed in the periphery of these power supplys/ground connection bump pads, these secondary signal bump pads then also are distributed in the periphery of these first signal bump pads, and two layers of centres that utilize six layer conductor layers are respectively as power/ground.
Though the present invention with a preferred embodiment openly as above; right its is not in order to limiting the present invention, anyly is familiar with this operator, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention defines and is as the criterion when looking claim.
Claims (7)
1. semiconductor baseplate is characterized in that: comprise at least:
One conductor layer No.1 of patterning, one second conductor layer, a privates layer, a privates layer, one the 5th conductor layer and one the 6th conductor layer, overlapped in regular turn, wherein this conductor layer No.1 has several power supplys/ground connection bump pads, several first signal bump pads and several secondary signal bump pads, and those first signal bump pads are distributed in the periphery of those power supplys/ground connection bump pads, and those secondary signal bump pads are distributed in the periphery of those first signal bump pads, and wherein the 6th conductor layer has several joint sheets;
Several inner insulating layers, be disposed between this second conductor layer and this privates layer respectively, between this privates layer and this privates layer, and this privates layer and the 5th conductor layer between;
The logical connector of several platings, run through those inner insulating layers, second conductor layer, this privates layer, this privates layer and the 5th conductor layer respectively simultaneously, wherein this second conductor layer, this privates layer, privates layer and the 5th conductor layer electrically connect mutually through the logical connector of those platings;
One first external insulation layer and one second external insulation layer are disposed at respectively between this conductor layer No.1 and this second conductor layer, and between the 5th conductor layer and the 6th conductor layer;
Several first conducting connectors and several second conducting connectors, run through this first external insulation layer and this second external insulation layer respectively, wherein this conductor layer No.1 electrically connects with this second conductor layer mutually through those first conducting connectors, and the 6th conductor layer electrically connects with the 5th conductor layer mutually through those second conducting connectors
Wherein those first signal bump pads are passed through those first conducting connectors respectively, this second conductor layer, the logical connector of those platings, the 5th conductor layer, those second conducting connectors and the 6th conductor layer and be connected to those corresponding joint sheets, and those secondary signal bump pads are passed through this conductor layer No.1 respectively, those first conducting connectors, this second conductor layer, the logical connector of those platings, the 5th conductor layer and those second conducting connectors and be connected to those corresponding joint sheets, and those power supplys/ground connection bump pads is passed through those first conducting connectors respectively, this second conductor layer, the logical connector of those platings, this privates layer, this privates layer, the 5th conductor layer, those second conducting connectors and the 6th conductor layer and be connected to those corresponding joint sheets.
2. semiconductor baseplate as claimed in claim 1, it is characterized in that: also comprise one first anti-layer, it is disposed on this first external insulation layer and this conductor layer No.1, and exposes those power supplys/ground connection bump pads, those first signal bump pads and those secondary signal bump pads.
3. semiconductor baseplate as claimed in claim 1 is characterized in that: also comprise one second anti-layer, it is disposed on this second external insulation layer and the 6th conductor layer, and exposes those joint sheets.
4. semiconductor baseplate as claimed in claim 1 is characterized in that: wherein this semiconductor baseplate is as a chip upside-down mounting type ball grid array baseplate.
5. semiconductor baseplate as claimed in claim 4 is characterized in that: wherein those joint sheets are as solder ball pad.
6. semiconductor baseplate as claimed in claim 1 is characterized in that: wherein the material of those inner insulating layers is selected from a kind of material in the group that is made up of glass epoxide base resin, two maleic acid vinegar imines and epoxy resin.
7. semiconductor baseplate as claimed in claim 1 is characterized in that: wherein those inside conductors constitute through definition one copper foil layer respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021028486A CN1324697C (en) | 2002-01-28 | 2002-01-28 | Semiconductor baseplate and its fabrication process |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021028486A CN1324697C (en) | 2002-01-28 | 2002-01-28 | Semiconductor baseplate and its fabrication process |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1362739A CN1362739A (en) | 2002-08-07 |
| CN1324697C true CN1324697C (en) | 2007-07-04 |
Family
ID=4739754
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB021028486A Expired - Lifetime CN1324697C (en) | 2002-01-28 | 2002-01-28 | Semiconductor baseplate and its fabrication process |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1324697C (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5562971A (en) * | 1994-04-19 | 1996-10-08 | Hitachi Chemical Company, Ltd. | Multilayer printed wiring board |
| CN1178625A (en) * | 1996-01-11 | 1998-04-08 | 揖斐电株式会社 | Printed circuit board and manufacture thereof |
-
2002
- 2002-01-28 CN CNB021028486A patent/CN1324697C/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5562971A (en) * | 1994-04-19 | 1996-10-08 | Hitachi Chemical Company, Ltd. | Multilayer printed wiring board |
| CN1178625A (en) * | 1996-01-11 | 1998-04-08 | 揖斐电株式会社 | Printed circuit board and manufacture thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1362739A (en) | 2002-08-07 |
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Granted publication date: 20070704 |