CN2872796Y - Electronic assembly - Google Patents
Electronic assembly Download PDFInfo
- Publication number
- CN2872796Y CN2872796Y CN 200620002438 CN200620002438U CN2872796Y CN 2872796 Y CN2872796 Y CN 2872796Y CN 200620002438 CN200620002438 CN 200620002438 CN 200620002438 U CN200620002438 U CN 200620002438U CN 2872796 Y CN2872796 Y CN 2872796Y
- Authority
- CN
- China
- Prior art keywords
- connection pad
- electrically connected
- electronic assembly
- chip
- patterned conductive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The utility model discloses an electronic assembly including a circuit board suitable for electrically connecting with a chip package. The chip package includes a chip seat and multiple inner pins. The circuit board includes at least a patterned conducive layer and at least a first insulating layer. The patterned conductive layer includes at least a first bonding pad and at least a second bonding pad. The first bonding pad has an extending portion, and is suitable for electrically connecting with the chip seat. The second bonding pad is suitable for electrically connecting with one end of at least one of the inner pins, and the other end of the inner pin suitable for electrically connecting with the second bonding pad has projection in the patterned conductive layer at least partially overlapped with the extending portion. Besides, the patterned conductive layer is arranged outside the first insulating layer. The utility model has advantages of improved transmission quality of high-frequency signal.
Description
Technical field
The utility model relates to a kind of wiring board (wiring board) and electronic assembly (electronicassembly), and particularly relevant for a kind of circuit board (circuit board) and the electronic assembly that comprises chip packing-body and circuit board.
Background technology
Generally speaking, existing in order to carry and to be electrically connected the wiring board of a plurality of electronic components, it comprises base plate for packaging (package substrate) and circuit board, mainly be by multi-layered patterned conductive layer (patternedconductive layer) and multilayer dielectric layer (insulating layer) alternately coincide constitute, wherein for example definition forms these patterned conductive layers through lithography by copper foil layer (copper foil), these insulating barriers then are disposed at respectively between adjacent these patterned conductive layers, in order to isolate these patterned conductive layers.In addition, see through conduction duct (conductivevia) and being electrically connected to each other between these overlapped patterned conductive layers.
With regard to circuit board, its surperficial configurable chip packing-body is to form an electronic assembly.The patterned conductive layer of chip packing-body and circuit board surface is electrically connected and reaches the purpose of electronic signal transmission (electrical signal propagation) by the circuit board internal wiring.
Figure 1A illustrates the schematic top plan view of existing a kind of electronic assembly, and Figure 1B illustrates the line A-A generalized section of Figure 1A.Please also refer to Figure 1A and Figure 1B, existing electronic assembly 100 comprises a square flat non-pin (Quad Flat No-lead, QFN) chip packing-body 110 (hereinafter to be referred as the QFN packaging body), a circuit board 120 and a welding cover layer (solder mask layer) 130 of encapsulation kenel.QFN packaging body 110 comprises a chip (chip) 112, a lead frame (leadframe) 114, many bonding wires (bonding wire) 116 and colloid (encapsulant) 118.Chip 112 has an active face (activesurface) 112a and a plurality of weld pad (bonding pad) 112b that is positioned on the active face 112a, lead frame 114 has a chip carrier (chip pad) 114a and a plurality of interior pin (inner lead) 114b, and chip 112 is disposed on the chip carrier 114a.Pin 114b is electrically connected to these weld pads 112b by these bonding wires 116 in chip carrier 114a and these, and colloid 118 coating chip 112, these bonding wires 116 and part lead frames 114 at least.
Yet, under high-frequency signal transmission, the inductive sensor (inducedinductance) that these bonding wires 116 are produced will make holding wire 122b and the interior pin 114b that is electrically connected between the do not match phenomenon of (impedance mismatch) of impedance even more serious, and then reduce the quality that signal transmits between holding wire 122b and the interior pin 114b that is electrically connected.
The utility model content
Another purpose of the present utility model provides a kind of electronic assembly, to promote the transmission quality of its high-frequency signal.
For reaching above-mentioned or other purpose, the utility model proposes a kind of electronic assembly, comprise a chip packing-body and a circuit board.Chip packing-body comprises a chip, a lead frame, many bonding wires and colloid.Chip has an active face and a plurality of weld pad that is positioned on the active face.Lead frame have a chip carrier and a plurality of in pin, chip configuration is on chip carrier, and these interior pins of chip carrier and part are electrically connected to these weld pads by these bonding wires, and colloid coating chip, these bonding wires and part lead frame at least.In addition, chip packing-body is disposed on the circuit board, and circuit board comprises at least one patterned conductive layer and at least one first insulating barrier.Patterned conductive layer has at least one first connection pad and at least one second connection pad, and first connection pad has an extension, and first connection pad and chip carrier are electrically connected.At least one end of pins is electrically connected in second connection pad and these, and the other end that is electrically connected to the interior pin of second connection pad is overlapped at least at the projection and the extension of patterned conductive layer, and patterned conductive layer is disposed at the outside of first insulating barrier.
For above-mentioned and other purpose, feature and advantage of the present utility model can be become apparent, a plurality of embodiment cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Figure 1A illustrates the schematic top plan view of existing a kind of electronic assembly;
Figure 1B illustrates the generalized section of Figure 1A along line A-A;
Fig. 2 A illustrates the schematic top plan view of a kind of electronic assembly of the utility model first embodiment;
Fig. 2 B illustrates the generalized section of Fig. 2 A along line B-B;
Fig. 3 illustrates the schematic top plan view of a kind of electronic assembly of the utility model second embodiment;
Fig. 4 illustrates the schematic top plan view of a kind of electronic assembly of the utility model the 3rd embodiment.
Description of reference numerals
100,200,300,400: electronic assembly
110,210: chip packing-body
112,212: chip
112a, 212a: active face
112b, 212b: weld pad
114,214: lead frame
114a, 214a: chip carrier
114b, 214b, 314b, 414b: interior pin
116,216: bonding wire
118,218: colloid
120,220,320,420: circuit board
122,222,322,422: patterned conductive layer
122a: ground connection connection pad
122b: holding wire
124: insulating barrier
126: the conduction duct
130: welding cover layer
132,232: opening
222a: first connection pad
222b, 322b, 422b: second connection pad
222c, 322c, 422c: transmission line
224: the first insulating barriers
230: the second insulating barriers
D1, d2: width
E, E ', E ": extension
S1: first section
S2: second section
Embodiment
First embodiment
Fig. 2 A illustrates the schematic top plan view of a kind of electronic assembly of the utility model first embodiment, and Fig. 2 B illustrates the generalized section of Fig. 2 A along line B-B.Please also refer to Fig. 2 A and Fig. 2 B, the electronic assembly 200 of first embodiment comprises a chip packing-body 210 and a circuit board 220.Chip packing-body 210 (for example being the QFN packaging body) comprises a chip 212, a lead frame 214, many bonding wires 216 (Fig. 2 A only schematically illustrates 5) and colloid 218.Chip 212 has an active face 212a and a plurality of weld pad 212b (Fig. 2 A only schematically illustrates 5) that is positioned on the active face 212a.Lead frame 214 has a chip carrier 214a and a plurality of interior pin 214b (Fig. 2 A only schematically illustrates 5), chip 212 is disposed on the chip carrier 214a, and chip carrier 214a and part in these pin 214b be electrically connected to these weld pads 212b by these bonding wires 216, and colloid 218 coating chip 212, these bonding wires 216 and part lead frames 214 at least.
In addition, chip packing-body 210 is disposed on the circuit board 220, and circuit board 220 comprises at least one patterned conductive layer 222 and at least one first insulating barrier 224.Patterned conductive layer 222 has at least one first connection pad 222a and at least one second connection pad 222b; Wherein, the first connection pad 222a for example is the ground connection connection pad, and the second connection pad 222b for example is signal bonding pad (signal pad).The first connection pad 222a has an extension (extension part) E, and the first connection pad 222a and chip carrier 214a be electrically connected, so that chip 212 is positioned at the top of the first connection pad 222a.In addition, the end of the second connection pad 222b and two adjacent these interior pin 214b is electrically connected, and the other end that is electrically connected to adjacent these interior pin 214b of the second connection pad 222b is overlapped at least at the projection and the extension E of patterned conductive layer 222, in other words, extension E extends to the two adjacent belows of the other end of pin 214b in these that are electrically connected with the second connection pad 222b.Moreover electronic assembly 200 more comprises one second insulating barrier 230 (for example being welding cover layer), and it is positioned on the patterned conductive layer 222, and second insulating barrier 230 has at least one opening 232 to expose the first connection pad 222a and the second connection pad 222b.
Patterned conductive layer 222 is disposed at the outside of first insulating barrier 224, for example definition forms patterned conductive layer 222 through lithography by copper foil layer, and the material of first insulating barrier 224 for example is glass epoxy resin (FR-4) or epoxy resin (epoxy resin).In this mandatory declaration is that among first embodiment, the patterned conductive layer 222 and first insulating barrier 224 respectively are one deck, but also can be sandwich construction.The formation sandwich construction that for example patterned conductive layer 222 and first insulating barrier 224 alternately coincided, and these first insulating barriers 224 can be disposed at respectively between adjacent these patterned conductive layers 222, in order to isolate these patterned conductive layers 222.In addition, can and be electrically connected to each other through at least one conduction duct (not illustrating) between these overlapped patterned conductive layers 222.In view of the above, the circuit board 220 of first embodiment is non-limiting the utility model in order to give an example.
In first embodiment, patterned conductive layer 222 comprises at least one transmission line 222c, and the end of transmission line 222c and the second connection pad 222b are electrically connected.In addition, with the second connection pad 222b be electrically connected two adjacent in these pin 214b one of them by these bonding wires 216 one of them and be electrically connected with one of them of these weld pads 212b, in other words, be electrically connected to the second connection pad 222b two adjacent have only among pin 214b in these interior pin 214b in order to transmission signals between chip 212 and transmission line 222c.
In this mandatory declaration is that the second connection pad 222b can be electrically connected with one of them the end of pin 214b in these, and the other end that is electrically connected to the interior pin 214b of the second connection pad 222b is overlapped at least at the projection and the extension E of patterned conductive layer 222.In addition, the interior pin 214b that is electrically connected with the second connection pad 222b can by these bonding wires 216 one of them and be electrically connected with one of them of these weld pads 212b.But, above-mentionedly do not illustrate with drawing.
Via as can be known above-mentioned, when the electronic assembly 200 of first embodiment when transmitting high-frequency signal (for example between between 1,000,000,000 hertz to 5,000,000,000 hertz high frequency region), the unmatched phenomenon of the impedance that inductive sensor caused that these bonding wires 216 produce can obtain compensation (compensate) with the two adjacent inductance capacitances (induced capacitance) between the pin 214b in these that are electrically connected to transmission line 222c by the extension E of the first connection pad 222a, and then promotes the quality that signal transmits between transmission line 222c and two adjacent these the interior pin 214b that are electrically connected.In addition, the utility model more can suitably be connected to the second connection pad 222b of circuit board 220 an interior pin 214b or a plurality of adjacent interior pin 214b of chip packing-body 210, via the size and shape of the E of design extension portion to produce suitable inductance capacitance value.
Second embodiment
Please refer to Fig. 3 and Fig. 2 A, wherein Fig. 3 illustrates the schematic top plan view of a kind of electronic assembly of the utility model second embodiment.Second embodiment and first embodiment different be in, in the electronic assembly 300 of second embodiment, the transmission line 322c of the patterned conductive layer 322 of circuit board 320 has one first section (first section) S1 and one second section S2, the width d1 of the first section S1 is less than the width d2 of the second section S2, and the first section S1 and the second connection pad 322b are electrically connected.
Because it is less to be electrically connected to the width d1 of the first section S1 of transmission line 322c of the second connection pad 322b, therefore when the higher high-frequency signal of transmission frequency (for example between between 6,000,000,000 hertz to 9,000,000,000 hertz high frequency region), the inductive sensor that the first section S1 of transmission line 322c is improved, can compensate because of extension E ' and be electrically connected to the two adjacent inductance capacitances that produced between pin 314b in these of transmission line 322c, and then make that the quality of the high-frequency signal that 300 transmission frequencies of electronic assembly of second embodiment are higher is preferable.
The 3rd embodiment
Please refer to Fig. 4 and Fig. 2 A, wherein Fig. 4 illustrates the schematic top plan view of a kind of electronic assembly of the utility model the 3rd embodiment.The 3rd embodiment and first embodiment different be in, in the electronic assembly 400 of the 3rd embodiment, the second connection pad 422b of the patterned conductive layer 422 of circuit board 420 and three adjacent in these end of pin 414b be electrically connected.In addition, be electrically connected to the second connection pad 422b adjacent in these the other end of pin 414b at the projection of patterned conductive layer 422 and the extension E of first connection pad (not illustrating) " overlap at least; in other words, extension E " extend to the adjacent below of the other end of pin 414b in these of three of being electrically connected with the second connection pad 422b.In this mandatory declaration be, be electrically connected with the second connection pad 422b and with the extension E of first connection pad " partly overlapping in these number of pin 414b can change to some extent according to design requirement, therefore the 3rd embodiment is in order to for example and non-limiting the utility model.
Compare with first embodiment, in the 3rd embodiment, owing to be electrically connected with the second connection pad 422b and with the extension E of first connection pad " partly overlapping in these number of pin 414b more; therefore the electronic assembly 400 of the 3rd embodiment and during the high-frequency signal (for example between between 1,000,000,000 hertz to 5,000,000,000 hertz high frequency region) of the same frequency of electronic assembly 200 transmission of first embodiment, the quality of 400 transmission signals of electronic assembly of the 3rd embodiment is preferable.
Please refer to Fig. 3 and Fig. 4, it should be noted that, the external form of the transmission line 422c of the 3rd embodiment can be designed to the external form of the transmission line 322c of second embodiment according to design requirement, so that when transmitting for example between the high-frequency signal between 4,000,000,000 hertz to 6,000,000,000 hertz high frequency region, the quality of 400 transmission signals of electronic assembly of the 3rd embodiment is preferable, the preferable reason of its transmission signals quality is then described as second embodiment, so repeat no more in this.
At last, it must be emphasized that, the frequency separation of mentioned high-frequency signal is only in order to the difference of the frequency separation of these embodiment institute transmitting high-frequency signals of aid illustration among above-mentioned three embodiment, and the number increase and decrease that these frequency separations can change because of the wires design of the patterned conductive layer of circuit board with the interior pin of chip packing-body changes to some extent.Therefore, the frequency separation of the mentioned high-frequency signal of these embodiment is only in order to for example and non-limiting the utility model.
In sum, electronic assembly of the present utility model has following advantage at least:
(1) when electronic assembly of the present utility model during at transmitting high-frequency signal, the unmatched phenomenon of the impedance that inductive sensor caused that these bonding wires produce can obtain compensation by the inductance capacitance between the extension of first connection pad and the interior pin that is electrically connected to transmission line, so make transmission line with the interior pin that is electrically connected between the return loss (return loss) of signal transmission improve and insertion loss (insertion loss) reduction;
(2) electronic assembly of the present utility model can produce suitable inductance by the transmission line change width and compensate above-mentioned inductance capacitance, make when electronic assembly of the present utility model when transmitting more high-frequency signal, the return loss that signal transmits between transmission line and the interior pin that is electrically connected improves more and inserts loss and more reduce.
Though the utility model discloses as above with a plurality of embodiment; right its is not in order to limit the utility model; any those skilled in the art; in not breaking away from spirit and scope of the present utility model; when doing a little change and retouching, therefore protection range of the present utility model is as the criterion when looking appended the claim person of defining.
Claims (9)
1. electronic assembly is characterized in that comprising:
One chip packing-body comprises:
One chip has an active face and a plurality of weld pad that is positioned on the active face;
One lead frame have a chip carrier and a plurality of interior pin, and this chip configuration is on this chip carrier;
Many bonding wires, those interior pins of this chip carrier and part are electrically connected to those weld pads by those bonding wires; And
Colloid coats this chip, those bonding wires and this lead frame of part at least; And
One circuit board, this chip packing-body are disposed on this circuit board, and this circuit board comprises:
At least one patterned conductive layer, this patterned conductive layer has at least one first connection pad and at least one second connection pad, this first connection pad has an extension, and this first connection pad and this chip carrier are electrically connected, pin end one of at least is electrically connected in this second connection pad and those, and be electrically connected to this second connection pad one of at least in those other end of pins overlap at least at projection and this extension of this patterned conductive layer; And
At least one first insulating barrier, this patterned conductive layer is disposed at the outside of this first insulating barrier.
2. electronic assembly as claimed in claim 1 is characterized in that this patterned conductive layer comprises at least one transmission line, and an end of this transmission line and this second connection pad are electrically connected.
3. electronic assembly as claimed in claim 1 is characterized in that, this transmission line has one first section and one second section, and the width of this first section is less than the width of this second section, and this first section and this second connection pad are electrically connected.
4. electronic assembly as claimed in claim 1 is characterized in that, this chip packing-body is the chip packing-body of square flat non-pin encapsulation kenel.
5. electronic assembly as claimed in claim 1 is characterized in that, this first connection pad is a ground connection connection pad.
6. electronic assembly as claimed in claim 1 is characterized in that, this second connection pad is a signal bonding pad.
7. electronic assembly as claimed in claim 1, it is characterized in that, this second connection pad is suitable for being electrically connected at least two adjacent pins in those of this chip packing-body, and be suitable for being electrically connected to this second connection pad adjacent in those other end of pins overlap at least at projection and this extension of this patterned conductive layer.
8. electronic assembly as claimed in claim 7 is characterized in that, with this second connection pad be electrically connected adjacent in those one of pin be electrically connected with one of those weld pads by one of those bonding wires.
9. electronic assembly as claimed in claim 1 is characterized in that, more comprises one second insulating barrier and is positioned on this patterned conductive layer, and this second insulating barrier has at least one opening to be used and expose this first connection pad and this second connection pad.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200620002438 CN2872796Y (en) | 2006-01-18 | 2006-01-18 | Electronic assembly |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200620002438 CN2872796Y (en) | 2006-01-18 | 2006-01-18 | Electronic assembly |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN2872796Y true CN2872796Y (en) | 2007-02-21 |
Family
ID=37741136
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200620002438 Expired - Lifetime CN2872796Y (en) | 2006-01-18 | 2006-01-18 | Electronic assembly |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN2872796Y (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101847791A (en) * | 2010-01-11 | 2010-09-29 | 威盛电子股份有限公司 | Electronic assembly and a storage device thereof |
| CN103428984A (en) * | 2012-05-14 | 2013-12-04 | 联胜（中国）科技有限公司 | Circuit board |
| CN106548995A (en) * | 2015-09-16 | 2017-03-29 | 扬智科技股份有限公司 | Circuit board module and its semiconductor package part |
-
2006
- 2006-01-18 CN CN 200620002438 patent/CN2872796Y/en not_active Expired - Lifetime
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101847791A (en) * | 2010-01-11 | 2010-09-29 | 威盛电子股份有限公司 | Electronic assembly and a storage device thereof |
| CN101847791B (en) * | 2010-01-11 | 2013-02-20 | 威盛电子股份有限公司 | Electronic assembly and a storage device thereof |
| CN103428984A (en) * | 2012-05-14 | 2013-12-04 | 联胜（中国）科技有限公司 | Circuit board |
| CN106548995A (en) * | 2015-09-16 | 2017-03-29 | 扬智科技股份有限公司 | Circuit board module and its semiconductor package part |
| CN106548995B (en) * | 2015-09-16 | 2019-07-12 | 扬智科技股份有限公司 | Circuit board module and its semiconductor package part |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20070221 |
|
| EXPY | Termination of patent right or utility model |