CN118366515B - SRAM structure with reliability and stability and self-timing control method thereof - Google Patents

SRAM structure with reliability and stability and self-timing control method thereof Download PDF

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CN118366515B
CN118366515B CN202410788566.9A CN202410788566A CN118366515B CN 118366515 B CN118366515 B CN 118366515B CN 202410788566 A CN202410788566 A CN 202410788566A CN 118366515 B CN118366515 B CN 118366515B
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gate
memory bank
input end
tube
mos tube
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CN118366515A (en
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张武
卢昌鹏
刘华
王建军
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Shanghai Hailichuang Technology Co ltd
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Shanghai Hailichuang Technology Co ltd
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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Abstract

The invention discloses an SRAM structure with reliability and stability and a self-timing control method thereof, wherein the SRAM structure with reliability and stability comprises a plurality of virtual memory banks connected in parallel; the virtual memory bank is disposed at one side of the real memory bank in the length direction. Further, the virtual memory body comprises a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a first PMOS tube and a second PMOS tube; the gates of the third NMOS tube and the fourth NMOS tube are connected with word lines, and the drains of the third NMOS tube and the fourth NMOS tube are respectively connected with bit lines and complementary bit lines; the bit line and the complementary bit line are both connected to the timing control circuit. The invention can control the word line on time of the real memory bank, thereby accurately controlling the on time of the sense amplifier, shortening the on time of the sense amplifier, improving the control flexibility and effectively saving the power consumption.

Description

SRAM structure with reliability and stability and self-timing control method thereof
Technical Field
The present invention relates to the field of semiconductor memory technology, and in particular, to an SRAM structure with reliability and stability and a self-timing control method thereof.
Background
SRAM, static random access memory, is a type of random access memory, and has a characteristic that data stored therein can be constantly held as long as power is kept on. This characteristic makes SRAM important in a variety of applications requiring high-speed storage and fast data access. With the continuous enhancement and complexity of electronic device functions, the performance requirements of the memory are also increasing. The performance of SRAM as a high-speed memory device in terms of stability, data read-write speed, reliability, and the like directly affects the performance of the entire electronic system. Meanwhile, along with popularization of mobile equipment and internet of things equipment, the power consumption requirements on the equipment are more and more strict.
At present, the existing mode of performing self-timing control by using a virtual memory bank is mainly based on the principle that the characteristics of the virtual memory bank are consistent with those of a real memory bank unit, and the real memory bank unit is controlled in a ratio of 1:1 by using the control time of the virtual memory bank. The mode not only makes the control inflexible, but also makes the control of the real memory unit inaccurate and efficient, thereby reducing the read-write performance of the SRAM and increasing the power consumption.
Disclosure of Invention
The invention aims to provide an SRAM structure with reliability and stability and a self-timing control method thereof, which can control the word line on time of a real memory bank, thereby accurately controlling the on time of a sense amplifier, shortening the on time of the sense amplifier, improving the control flexibility and effectively saving the power consumption.
In order to solve the technical problems, the invention provides an SRAM structure with reliability and stability, which comprises a plurality of virtual memory banks connected in parallel; the virtual memory bank is arranged at one side of the real memory bank in the length direction.
Further, the virtual memory bank comprises a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a first PMOS tube and a second PMOS tube;
The source electrode of the first NMOS tube is grounded, the drain electrode of the first NMOS tube is connected with the source electrode of the third NMOS tube and the drain electrode of the first PMOS tube, and the grid electrodes of the first NMOS tube and the first PMOS tube are both connected with a power supply voltage;
The source electrode of the second NMOS tube is grounded, the drain electrode of the second NMOS tube is connected with the drain electrode of the second PMOS tube and the source electrode of the fourth NMOS tube, and the grid electrodes of the second NMOS tube and the second PMOS tube are both connected with the power supply voltage;
The gates of the third NMOS tube and the fourth NMOS tube are connected with word lines, and the drains of the third NMOS tube and the fourth NMOS tube are respectively connected with bit lines and complementary bit lines;
the bit line and the complementary bit line are connected to a time sequence control circuit;
and the sources of the first PMOS tube and the second PMOS tube are connected with the power supply voltage.
Further, the device also comprises a real memory bank, a time sequence control circuit and a read-write circuit which are connected;
In an initial state, the voltages of the bit lines and the complementary bit lines of the virtual memory bank are high, and after the word lines of the virtual memory bank and the real memory bank are started, the bit lines and the complementary bit lines of the virtual memory bank are discharged into the time sequence control circuit, and meanwhile, the bit lines and the complementary bit lines of the real memory bank generate voltage differences; when the voltage difference reaches a data reading set value of the read-write circuit, the time sequence control circuit closes a word line according to the overturning voltage generated by discharging; data reading is performed.
Further, the time sequence control circuit comprises a data read-write clock module, a system clock module, a feedback loop module, a word line width control module and a control signal generation module;
The input end of the data read-write clock module is connected with the output end of the system clock and the feedback loop module, the input end is connected with the address clock through a pin CLKADR, and the output end of the data read-write clock module is connected with a read-write circuit through a pin CLKDA;
the output end of the system clock module is connected with the input end of the feedback loop module;
the feedback loop module is connected with the word line width control module;
The word line width control module is connected to the control signal generation module and the virtual memory bank;
The control signal generation module is connected to the word lines of the real memory bank through pins WLCLK.
Further, the data read-write clock module comprises a first AND gate; the system clock module comprises a second AND gate; the input end of the first AND gate is connected with the output end of the second AND gate and the feedback loop module, and is connected to the address decoding circuit through a pin CLKADR.
Further, the feedback loop module includes: the first delay device, the first NOT gate, the first MOS tube, the third MOS tube, the fifth MOS tube and the sixth MOS tube;
the input end of the first delay device, the grid electrode of the third MOS tube and the grid electrode of the fifth MOS tube are all connected with the input end of the first AND gate; the output end of the first delay device is connected with the input end of the first NOT gate;
the output end of the first NOT gate is connected with the grid electrode of the first MOS tube and the grid electrode of the sixth MOS tube;
The drain electrode of the first MOS tube is connected with the source electrode of the third MOS tube, and the source electrode of the first MOS tube is grounded;
the drains of the third MOS tube, the fifth MOS tube and the sixth MOS tube are all connected with the word line width control module;
the sources of the fifth MOS tube and the sixth MOS tube are connected with the power supply voltage.
Further, the word line width control module comprises a second MOS tube, a fourth MOS tube, a seventh MOS tube, a second NOT gate, a third NOT gate, a first NOT gate and an inverter;
The drain electrode of the second MOS tube is connected with the drain electrode of the third MOS tube, the drain electrode of the fourth MOS tube, the input end of the second NOT gate and the input end of the first NOT gate, the source electrode is grounded, and the grid electrode is connected with the grid electrode of the fourth MOS tube and the output end of the first NOT gate;
The source electrode of the fourth MOS tube is connected with the drain electrode of the fifth MOS tube and the drain electrode of the sixth MOS tube;
The source electrode of the seventh MOS tube is connected with the power supply voltage, and the grid electrode of the seventh MOS tube is connected with the output end of the third NOT gate;
the output end of the second NOT gate is connected with the control signal generating module;
the input end of the third NOT gate is connected to the precharge circuit through a pin PRCHG;
The input end of the first NOR gate is connected with the output end of the inverter;
the input end of the inverter is connected with the drain electrode of the seventh MOS tube, and the input end of the inverter is also connected with the virtual memory bank.
Further, the control signal generating module includes: the second NOR gate, the second delay device, the first driver, the fourth NOT gate, the third delay device, the second driver, the third AND gate, the OR gate and the fifth NOT gate;
The input end of the second NOR gate, the input end of the second delay device, the input end of the fourth NOR gate and the input end of the first driver are all connected with the output end of the second NOR gate;
The output end of the second NOR gate is connected with the input end of the second driver, and the input end of the second NOR gate is also connected with the output end of the third delayer;
the output end of the first driver controls the on or off of the word line of the real memory bank through a pin WLCLK;
the output end of the second driver is connected to the precharge circuit through the pin PRCHG;
the output end of the second delayer is connected with the input end of the third delayer and the input end of the third AND gate;
The input end of the third AND gate is connected with the output end of the fourth NOT gate and the input end of the OR gate, and the output end of the third AND gate is connected with the input end of the fifth NOT gate;
The output end of the fifth NOT gate is connected with the read-write circuit through a pin RDP;
the output end of the OR gate is connected with the read-write circuit through a pin WEP_n.
Further, the method further comprises a plurality of PD pipes, wherein the PD pipes are arranged on the periphery adjacent to the real memory bank, and the virtual memory bank is located between a part of the PD pipes and the real memory bank.
In addition, the invention also provides an SRAM self-timing control method, which adopts the SRAM structure with reliability and stability, and specifically comprises the following steps:
Starting word lines, discharging bit lines and complementary bit lines of the virtual memory bank, and generating voltage differences between the bit lines and the complementary bit lines of the real memory bank;
and when the voltage difference reaches a data reading set value, closing word lines according to the overturning voltage generated by discharging, and reading data, wherein the bit lines and complementary bit lines of the virtual memory bank stop discharging, and the duration of the opening of the word lines is related to the number of the virtual memory bank.
Further, before the word line is turned on, the method further includes:
precharging bit lines and complementary bit lines of the virtual memory bank to a high voltage;
selecting a data bit of data to be read out, opening a word line, waiting for the bit line and the complementary bit line of the real memory bank to form a voltage difference, and discharging the bit line and the complementary bit line of the virtual memory bank at the same time;
if the voltage difference reaches a set value for reading data of a sense amplifier in a read-write circuit, the discharge reaches a turnover voltage to close a word line, and the sense amplifier is started to read the data;
If the differential pressure does not reach the data reading set value of the sensitive amplifier, returning to the previous step;
after the data to be read is read, the sense amplifier is turned off, and the read operation is ended.
Further, the duration of the word line on is related to the number of the virtual memory banks, and specifically includes:
Assuming that the flip voltage for word line off is Vtrig, the number of virtual banks is N, the duration of word line on is: tdis= Cdbl ×vtrig/(n×i Cell,dum), where I Cell,dum represents the discharge current of the virtual memory bank, cdbl represents the parasitic capacitance of the bit line of the virtual memory bank, vtrig=vdd/x, VDD represents the power supply voltage, x is a positive number;
At Tdis time, the differential voltage generated by the bit line and the complementary bit line of the real memory bank is: Δvbl=i Cell,norm×Tdis/Cbl=[ICell,norm×Cdbl×Vtrig/（N×ICell,dum) ]/cbl≡vtrig/n=vdd/xN; where I Cell,norm denotes the discharge current of the real bank, cbl denotes the parasitic capacitance of the bit line of the real bank, cbl≡ Cdbl.
Further, the sense amplifier data readout setting is several times its design offset.
Further, the method further comprises the following steps:
precharging bit lines and complementary bit lines of the virtual memory bank to a high voltage;
selecting a data bit to be written with data, and opening a word line;
Writing data, and returning to the previous step if the data writing fails;
after the data to be written is written, the word line is turned off, ending the writing operation.
Through the technical scheme, the invention has the following beneficial effects:
Setting a plurality of virtual memory banks in parallel; and the virtual memory bank is arranged on one side of the length direction of the real memory bank, so that the word line opening time of the real memory bank can be controlled, the opening time of the sense amplifier can be accurately controlled, compared with the prior art, the opening time of the sense amplifier can be shortened, the control flexibility can be improved, and the power consumption can be effectively saved. Therefore, the structure can prolong the endurance time of the equipment, reduce the heat generation and improve the stability and the reliability of the equipment through the arrangement of the plurality of parallel virtual memory banks.
Drawings
FIG. 1 is a schematic diagram of an SRAM structure with reliability and stability according to an embodiment of the present invention;
FIG. 2 is a schematic diagram showing the overall structure of an SRAM structure with reliability and stability in one embodiment of the present invention;
FIG. 3 is a schematic diagram of a virtual memory bank in an SRAM structure with reliability and stability according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a timing control circuit in an SRAM structure with reliability and stability according to an embodiment of the present invention;
FIG. 5 is a schematic diagram showing an address bit decoding circuit in an SRAM structure with reliability and stability according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a real memory bank in an SRAM structure with reliability and stability according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of a sense amplifier in an SRAM structure with reliability and stability according to an embodiment of the present invention;
FIG. 8 is a timing diagram of a read operation in an SRAM structure with reliability and stability in accordance with one embodiment of the present invention;
FIG. 9 is a schematic diagram illustrating a simulation of a write operation in an SRAM structure with reliability and stability in accordance with one embodiment of the present invention;
FIG. 10 is a schematic diagram illustrating a read operation in an SRAM structure with reliability and stability according to an embodiment of the present invention;
FIG. 11 is a flowchart of a method for SRAM self-timing control in accordance with one embodiment of the present invention;
FIG. 12 is a flow chart of a write operation in the SRAM self-timing control method in accordance with one embodiment of the present invention;
FIG. 13 is a flow chart of a read operation in the SRAM self-timing control method in accordance with one embodiment of the present invention.
Detailed Description
An SRAM structure with reliability and stability and a self-timing control method thereof according to the present invention will be described in more detail with reference to the accompanying drawings, in which preferred embodiments of the present invention are shown, it being understood that one skilled in the art can modify the invention described herein while still achieving the advantageous effects of the invention. Accordingly, the following description is to be construed as broadly known to those skilled in the art and not as limiting the invention.
The invention is more particularly described by way of example in the following paragraphs with reference to the drawings. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
As shown in fig. 1-2, an embodiment of the present invention proposes an SRAM structure with reliability and stability, which includes a plurality of virtual memory banks connected in parallel; the dummy memory bank is disposed at one side in the length direction of the real memory bank (as in fig. 1, at one side in the horizontal direction of the real memory bank, and perpendicular to the row decoding circuit).
Wherein, the periphery of the real memory bank is also provided with a virtual memory unit (not all shown in the figure) for protecting the real memory bank, and the structure of the virtual memory unit is consistent with that of the real memory bank.
In a specific embodiment, as shown in fig. 3, the virtual memory bank includes a first NMOS transistor MN0, a second NMOS transistor MN1, a third NMOS transistor MN2, a fourth NMOS transistor MN3, a first PMOS transistor MP0, and a second PMOS transistor MP1.
Specifically, the source electrode of the first NMOS transistor MN0 is grounded to VSS, the drain electrode is connected to the source electrode of the third NMOS transistor MN2 and the drain electrode of the first PMOS transistor MP0, and the gates of the first NMOS transistor MN0 and the first PMOS transistor MP0 are both connected to the power supply voltage VDD; the source electrode of the second NMOS tube MN1 is grounded to VSS, the drain electrode is connected to the drain electrode of the second PMOS tube MP1 and the source electrode of the fourth NMOS tube MN3, and the grid electrodes of the second NMOS tube MN1 and the second PMOS tube MP1 are both connected to the power supply voltage VDD; the gates of the third NMOS transistor MN2 and the fourth NMOS transistor MN3 are both connected to the word line WL, and the drains of the third NMOS transistor MN2 and the fourth NMOS transistor MN3 are respectively connected to the bit line BL and the complementary bit line BLB; the bit line BL and the complementary bit line BLB are both connected to a timing control circuit (the bit line BL and the complementary bit line BLB are connected together to form DBL); the sources and gates of the first PMOS transistor MP0 and the second PMOS transistor MP1 are both connected to the power supply voltage VDD.
In addition, as shown in fig. 1 and 2, the present embodiment further includes a plurality of PD pipes disposed at the periphery adjacent to the real memory bank, wherein the virtual memory bank is located between a portion of the PD pipes and the real memory bank.
In this embodiment, the virtual memory bank is used not only to protect the real memory bank, but also to promote the matching between the circuits. Because the memory bank in the embodiment adopts a 6T unit structure, and in the actual manufacturing process, the circuit periphery is generally surrounded by the ground wire, in order to save layout area, the circuit can be laid on the periphery of the actual memory bank as a protection tube through a PD tube. Therefore, the embodiment not only improves the robustness of the circuit, but also provides a foundation for a self-timing control method.
In addition, as shown in fig. 1 and 2, the present embodiment further includes a real memory bank, a timing control circuit, and a read-write circuit connected.
Specifically, in the initial state, the voltages of the bit line BL and the complementary bit line BLB of the virtual memory bank are high, and after the word lines of the virtual memory bank and the real memory bank are turned on (i.e., after the word line DWL connected to the virtual memory bank and the real memory bank in fig. 1 is turned on), the bit line BL and the complementary bit line BLB of the virtual memory bank are discharged to the timing control circuit, and at the same time, the bit line BL and the complementary bit line BLB of the real memory bank generate a voltage difference; when the voltage difference reaches the data reading set value of the read-write circuit, the time sequence control circuit closes the word line DWL according to the overturn voltage generated by discharge at the same time, and data reading is carried out.
The word line DWL controls the opening of the word line WL of the virtual memory bank and the word line WL of the real memory bank.
In this embodiment, as shown in fig. 4, the timing control circuit includes a data read/write clock module, a system clock module, a feedback loop module, a word line width control module, and a control signal generation module.
Specifically, the input end of the data read-write clock module is connected to the output end of the system clock and the feedback loop module, the input end is connected to the address clock through a pin CLKADR, and the output end of the data read-write clock module is connected to the read-write circuit through a pin CLKDA; the output end of the system clock module is connected with the input end of the feedback loop module; the feedback loop module is connected with the word line width control module; the word line width control module is connected to the control signal generation module and the virtual memory bank; the control signal generation module is connected to the word lines of the real memory bank through pins WLCLK.
In this embodiment, the data read-write clock module includes a first and gate; the system clock module comprises a second AND gate; the input end of the first AND gate is connected with the output end of the second AND gate and the feedback loop module, and is connected to the address decoding circuit through a pin CLKADR.
In this embodiment, the feedback loop module includes: the first delay device, the first NOT gate, the first MOS tube M1, the third MOS tube M3, the fifth MOS tube M5 and the sixth MOS tube M6.
Specifically, the input end of the first delay device, the gate of the third MOS transistor M3 and the gate of the fifth MOS transistor M5 are all connected to the input end of the first and gate; the output end of the first delay device is connected with the input end of the first NOT gate; the output end of the first NOT gate is connected with the grid electrode of the first MOS tube M1 and the grid electrode of the sixth MOS tube M6; the drain electrode of the first MOS tube M1 is connected to the source electrode of the third MOS tube M3, and the source electrode of the first MOS tube M1 is grounded to VSS; the drains of the third MOS transistor M3, the fifth MOS transistor M5 and the sixth MOS transistor M6 are all connected to the word line width control module; the sources of the fifth MOS transistor M5 and the sixth MOS transistor M6 are connected to the power supply voltage VDD.
In this embodiment, the word line width control module includes a second MOS transistor M2, a fourth MOS transistor M4, a seventh MOS transistor M7, a second not gate, a third not gate, a first nor gate, and an inverter IO.
Specifically, the drain electrode of the second MOS transistor M2 is connected to the drain electrode of the third MOS transistor M3, the drain electrode of the fourth MOS transistor M4, the input end of the second nor gate and the input end of the first nor gate, the source electrode is grounded to VSS, and the gate electrode is connected to the gate electrode of the fourth MOS transistor M4 and the output end of the first nor gate; the source electrode of the fourth MOS tube M4 is connected with the drain electrode of the fifth MOS tube M5 and the drain electrode of the sixth MOS tube M6; the source electrode of the seventh MOS tube M7 is connected with the power supply voltage VDD, and the grid electrode is connected with the output end of the third NOT gate; the output end of the second NOT gate is connected with the control signal generating module; the input end of the third NOT gate is connected to the precharge circuit through a pin PRCHG; the input end of the first NOR gate is connected with the output end of the inverter IO; the input end of the inverter IO is connected with the drain electrode of the seventh MOS tube M7, and the input end of the inverter IO is also connected with the virtual memory bank.
In this embodiment, the control signal generating module includes: the second NOR gate, the second delay, the first driver, the fourth NOR gate, the third delay, the second driver, the third AND gate, the OR gate and the fifth NOR gate.
Specifically, the input end of the second nor gate, the input end of the second delay device, the input end of the fourth nor gate and the input end of the first driver are all connected to the output end of the second nor gate; the output end of the second NOR gate is connected with the input end of the second driver, and the input end of the second NOR gate is also connected with the output end of the third delayer; the output end of the first driver controls the on or off of the word line of the real memory bank through a pin WLCLK; the output end of the second driver is connected to the precharge circuit through the pin PRCHG; the output end of the second delayer is connected with the input end of the third delayer and the input end of the third AND gate; the input end of the third AND gate is connected with the output end of the fourth NOT gate and the input end of the OR gate, and the output end of the third AND gate is connected with the input end of the fifth NOT gate; the output end of the fifth NOT gate is connected with the read-write circuit (namely connected with a read operation circuit) through a pin RDP; the output end of the OR gate is connected to the read-write circuit (i.e. connected to the write operation circuit) through a pin WEP_n.
By means of the specific structure arrangement of the time sequence control circuit, static power consumption and dynamic power consumption of the circuit can be reduced.
In an embodiment, as shown in fig. 1,2 and 5, the present embodiment further includes an address bit decoding circuit, a row decoding circuit and a column decoding circuit connected to the timing control circuit.
Specifically, the input end of the address bit decoding circuit is connected with the address signal; the address bit decoding circuit is connected with the time sequence control circuit through a pin CLKADR; the address bit decoding circuit is connected with the row decoding circuit through a row address pin; the address bit decoding circuit is connected with the column decoding circuit through a column address pin. The row decoding circuit is connected to word lines WL of the dummy memory bank and the real memory bank through word line pins.
During the read and write process of the SRAM structure, parasitic resistance and capacitance of the bit line BL and the complementary bit line BLB have a significant impact on power consumption and performance. Particularly when writing data, the inversion of the bit line BL and the complementary bit line BLB consumes a lot of precharge energy. Therefore, reducing parasitic capacitance is a key to reducing write power consumption.
The on-time of the word line WL is critical to performance and power consumption when reading out data. Too early switching off of Sense Amplifiers (SA) may lead to data read errors, while too late switching off wastes power consumption. Therefore, the embodiment realizes the maximum reduction of power consumption on the premise of ensuring the correct reading of data by precisely controlling the on-time control of the word line WL.
Unlike the conventional virtual memory self-timing control logic, the present embodiment changes its internal interconnect structure by connecting virtual memory in parallel, realizing 1: n, so that the control logic is more flexible and efficient. The embodiment not only improves the flexibility of self-timing control, but also enables the control of the real memory bank to be more accurate and efficient. The performance of the SRAM structure is improved, and the possibility of using the SRAM structure in wider application scenes is provided.
In addition, the embodiment ensures the reliability and stability of the SRAM structure and realizes high-yield production by accurately adjusting the input voltage differential of SA.
During a read operation of the SRAM structure, as in the 6T SRAM bank circuit (i.e., the real bank) shown in fig. 6, when the word line WL in fig. 6 is set to 1, one of the transistors MN0 or MN1 in fig. 6 is turned on, resulting in the voltage of the bit line BL or the complementary bit line BLB in fig. 6 beginning to drop from VDD to the power ground voltage VSS. Over time, a voltage difference is formed between the bit line BL and the complementary bit line BLB in fig. 6, and when this voltage difference reaches a data readout set value of SA (sense amplifier), the SA can accurately read out the stored data.
However, the instantaneous power consumption of SA is quite significant in the process of reading out data. In order to optimize power consumption, the present embodiment must precisely control to disconnect the bit line BL and the complementary bit line BLB from the SA in fig. 6 in a minimum time and rapidly turn off the SA. On one hand, the instantaneous power consumption of the SA is large, and the SA can be turned off in time, so that the power consumption can be effectively saved; on the other hand, if the voltages of the bit line BL and the complementary bit line BLB drop too much, then the power consumption increases correspondingly when they are precharged before the next read and write operation (PG in fig. 6 represents precharge). Therefore, the present embodiment needs to set WL to "0" (i.e. turn off) timely to prevent the bit line BL or the complementary bit line BLB from continuing to drop, thereby reducing the precharge power consumption. But if the SA is shut down too early, it may result in data read errors; if turned off too late, unnecessary power consumption is wasted. Therefore, it is critical to precisely control the turn-on time of WL in this embodiment.
In this embodiment, as shown in fig. 4 and 7, for the closing of SA, the following is specific: when the timing control circuit turns off the word line according to the inversion voltage generated by the discharge, that is, when the second NOT gate outputs "0" (that is, the command to turn off the word line WL), the word line WL of the real memory bank is outputted and controlled to be "0", that is, turned off, through the first driver. And because the second delay device has a delay effect, at the moment when the second NOT gate outputs 0, the output of the third AND gate is still 1, and the SA is still in an on state. After a predetermined time of the second delay, the signal with the output of the second NOT gate being "0" is transmitted to the third AND gate through the second delay, and finally passes through the sense amplifier (as shown in fig. 7) in the output of the third AND gate and the fifth NOT gate in turn to become an enable signal SAE_ (at this time, the high level) and control the MN3 and the MN4 in fig. 7 to be turned off, at this time, the sense amplifier is turned off, and at the same time, the enable signal SAE_ isturned to "0" through the NOT gate in fig. 7, so as to form a signal SAE. Where enable signal sae_is the not of signal SAE.
It should be noted that, as shown in fig. 7-10, a classical sense amplifier structure and its corresponding voltage timing diagram indicate that SA is very sensitive to the voltage difference of the input voltage. In real engineering applications, there is a certain offset of SA (offset assumes 1 sigma=10mv). To ensure the reliability and stability of SRAM, it is necessary to ensure that the differential pressure across the input SA is several times (e.g., 6sigma or 10 sigma) greater than its design offset, thereby achieving high yield production of the SRAM structure.
Wherein v DL (t) in fig. 8 is the voltage state of the bit line BL, v DL_ (t) is the voltage state of the complementary bit line BLB, and v S (t) is the output state of the sense amplifier; therefore, the embodiment skillfully utilizes the virtual memory bank arranged for protecting the real memory bank in the circuit design to establish the self-timing operation time sequence, thereby remarkably improving the self-control and reliability of the circuit, accelerating the reading speed and reducing the area and the power consumption of the circuit.
In addition, as shown in fig. 11, the embodiment also proposes an SRAM self-timing control method, which adopts the SRAM structure with reliability and stability as described above, and specifically includes the following steps:
S1, starting a word line, discharging a bit line BL and a complementary bit line BLB of a virtual memory bank, and generating a voltage difference between the bit line BL and the complementary bit line BLB of a real memory bank;
S2, when the voltage difference reaches a data reading set value, closing word lines according to the overturning voltage generated by discharging, and reading data, wherein the bit lines BL and the complementary bit lines BLB of the virtual memory bank stop discharging, and the duration of the word line opening is related to the number of the virtual memory bank.
In addition, as shown in fig. 12, the present embodiment further includes the following steps:
S10, precharging a bit line BL and a complementary bit line BLB of the virtual memory bank to high voltage before writing data;
S20, selecting a data bit to be written with data, and opening a word line;
S30, performing data writing, and returning to the previous step if the data writing fails;
s40, after the data to be written is written, closing the word line, and ending the writing operation.
Further, as shown in fig. 13, before the word line is turned on, the method further includes the following steps:
s100, precharging a bit line BL and a complementary bit line BLB of the virtual memory bank to a high voltage;
s200, selecting a data bit needing to be read out, opening a word line, waiting for the bit line BL and the complementary bit line BLB of the real memory bank to form a voltage difference, and discharging the bit line BL and the complementary bit line BLB of the virtual memory bank;
S300, if the voltage difference reaches a set value for reading data of a sense amplifier in a read-write circuit, discharging reaches a turnover voltage to close a word line, and the sense amplifier is started to read the data;
s400, if the pressure difference does not reach the data reading set value of the sensitive amplifier, returning to the previous step;
S500, after the data to be read is read, the sense amplifier is turned off, and the reading operation is finished.
Further, the duration of the word line turn-on is related to the number of the virtual banks, and specifically includes: for example, N virtual banks in parallel are used to control the turn-on time of WL word lines, which is calculated as follows: assuming that the flip voltage of the word line off (i.e., the compare inversion point of the inverter IO) is Vtrig, the number of virtual banks is N, the duration of the word line on is: tdis= Cdbl ×vtrig/(n×i Cell,dum), where I Cell,dum represents the discharge current of the virtual memory bank, cdbl represents the parasitic capacitance of the bit line BL of the virtual memory bank, vtrig=vdd/x, VDD represents the power supply voltage, and x is a positive number. Further, since the charge amount formula is q=it, n×i Cell,dum ×tdis= Cdbl ×vtrig, cdbl ×vtrig represents the precharge charge amount of the present embodiment.
At Tdis time, the differential voltage generated by the bit line BL and the complementary bit line BLB of the real bank is: Δvbl=i Cell,norm×Tdis/Cbl=[ICell,norm×Cdbl×Vtrig/（N×ICell,dum) ]/cbl≡vtrig/n=vdd/xN; where I Cell,norm denotes a discharge current of the real bank, cbl denotes a parasitic capacitance of the bit line BL of the real bank, cbl≡ Cdbl.
In this embodiment, the sense amplifier data readout setting is several times its design offset. The high yield production of SRAM structures is achieved by controlling the number of virtual banks to control the magnitude of avbl versus the multiple offset voltage of the sense amplifier.
In this embodiment, for example, n=6 virtual banks are set, and the word line WL on time of the real bank is controlled by connecting the 6 virtual banks in parallel. The specific theory is calculated as follows:
WL width control solution
Dummy BL Discharge Theory Calculation：
assuming a flip voltage Vtrig of word line off, vtrig=vdd/2, the duration of word line on is: tdis= Cdbl ×vtrig/(6×i) Cell,dum).
At Tdis time, the differential voltage generated by the bit line BL and the complementary bit line BLB of the real bank is: avbl=i Cell,norm×Tdis/Cbl=[ICell,norm×Cdbl×Vtrig/(6×ICell,dum) ]/cbl≡vtrig/6=vdd/12=216 to 300mv (assuming vdd=2.6V to 3.6V).
The number of the virtual memory banks can be set according to actual demands, the relation between Vtrig and VDD can be set according to actual demands, and the voltage value of VDD can be set according to actual demands.
In addition, the above analysis ignores the delay of other control logic gates, since dummy Cell (virtual Cell) enters the linear region earlier, 6×I Cell,norm>6×ICell,dum.
The implementation simulates the self-timing time sequence control logic of the real memory bank by adopting the parallel connection of a plurality of virtual memory banks with the self-defined quantity, thereby remarkably improving the self-control and the reliability of the circuit. In addition, the embodiment not only greatly improves the data reading speed, shortens the SA starting time, realizes the process following, but also realizes the purpose of low circuit power consumption of the SRAM structure during reading, thereby comprehensively optimizing the performance of the semiconductor memory.
In summary, the SRAM structure with reliability and stability and the self-timing control method thereof provided by the present invention have the following advantages:
Setting a plurality of virtual memory banks in parallel; and the virtual memory bank is arranged on one side of the length direction of the real memory bank, so that the word line opening time of the real memory bank can be controlled, the opening time of the sense amplifier can be accurately controlled, compared with the prior art, the opening time of the sense amplifier can be shortened, the control flexibility can be improved, and the power consumption can be effectively saved. Therefore, the structure can prolong the endurance time of the equipment, reduce the heat generation and improve the stability and the reliability of the equipment through the arrangement of the plurality of parallel virtual memory banks.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.

Claims (12)

1. An SRAM structure with reliability and stability is characterized by comprising a plurality of virtual memory banks and a time sequence control circuit which are connected in parallel; the virtual memory bank is arranged at one side of the real memory bank in the length direction;
the virtual memory bank comprises a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a first PMOS tube and a second PMOS tube;
The source electrode of the first NMOS tube is grounded, the drain electrode of the first NMOS tube is connected with the source electrode of the third NMOS tube and the drain electrode of the first PMOS tube, and the grid electrodes of the first NMOS tube and the first PMOS tube are both connected with a power supply voltage;
The source electrode of the second NMOS tube is grounded, the drain electrode of the second NMOS tube is connected with the drain electrode of the second PMOS tube and the source electrode of the fourth NMOS tube, and the grid electrodes of the second NMOS tube and the second PMOS tube are both connected with the power supply voltage;
The gates of the third NMOS tube and the fourth NMOS tube are connected with word lines, and the drains of the third NMOS tube and the fourth NMOS tube are respectively connected with bit lines and complementary bit lines;
the bit line and the complementary bit line are connected to a time sequence control circuit;
the sources of the first PMOS tube and the second PMOS tube are connected with the power supply voltage;
The time sequence control circuit comprises a data read-write clock module, a system clock module, a feedback loop module, a word line width control module and a control signal generation module;
The input end of the data read-write clock module is connected with the output end of the system clock and the feedback loop module, the input end is connected with the address clock through a pin CLKADR, and the output end of the data read-write clock module is connected with a read-write circuit through a pin CLKDA;
the output end of the system clock module is connected with the input end of the feedback loop module;
the feedback loop module is connected with the word line width control module;
The word line width control module is connected to the control signal generation module and the virtual memory bank;
The control signal generation module is connected to the word lines of the real memory bank through pins WLCLK.
2. The SRAM structure of claim 1 with reliability and stability, further comprising a real bank and read-write circuit connected;
In an initial state, the voltages of the bit lines and the complementary bit lines of the virtual memory bank are high, and after the word lines of the virtual memory bank and the real memory bank are started, the bit lines and the complementary bit lines of the virtual memory bank are discharged into the time sequence control circuit, and meanwhile, the bit lines and the complementary bit lines of the real memory bank generate voltage differences; when the voltage difference reaches a data reading set value of the read-write circuit, the time sequence control circuit closes a word line according to the overturning voltage generated by discharging; data reading is performed.
3. The SRAM structure with reliability and stability of claim 2, wherein said data read-write clock module comprises a first and gate; the system clock module comprises a second AND gate; the input end of the first AND gate is connected with the output end of the second AND gate and the feedback loop module, and is connected to the address decoding circuit through a pin CLKADR.
4. The SRAM structure with reliability and stability of claim 3, wherein said feedback loop module comprises: the first delay device, the first NOT gate, the first MOS tube, the third MOS tube, the fifth MOS tube and the sixth MOS tube;
the input end of the first delay device, the grid electrode of the third MOS tube and the grid electrode of the fifth MOS tube are all connected with the input end of the first AND gate; the output end of the first delay device is connected with the input end of the first NOT gate;
the output end of the first NOT gate is connected with the grid electrode of the first MOS tube and the grid electrode of the sixth MOS tube;
The drain electrode of the first MOS tube is connected with the source electrode of the third MOS tube, and the source electrode of the first MOS tube is grounded;
the drains of the third MOS tube, the fifth MOS tube and the sixth MOS tube are all connected with the word line width control module;
the sources of the fifth MOS tube and the sixth MOS tube are connected with the power supply voltage.
5. The SRAM structure of claim 4 with reliability and stability, wherein said wordline width control module comprises a second MOS transistor, a fourth MOS transistor, a seventh MOS transistor, a second not gate, a third not gate, a first nor gate, and an inverter;
The drain electrode of the second MOS tube is connected with the drain electrode of the third MOS tube, the drain electrode of the fourth MOS tube, the input end of the second NOT gate and the input end of the first NOT gate, the source electrode is grounded, and the grid electrode is connected with the grid electrode of the fourth MOS tube and the output end of the first NOT gate;
The source electrode of the fourth MOS tube is connected with the drain electrode of the fifth MOS tube and the drain electrode of the sixth MOS tube;
The source electrode of the seventh MOS tube is connected with the power supply voltage, and the grid electrode of the seventh MOS tube is connected with the output end of the third NOT gate;
the output end of the second NOT gate is connected with the control signal generating module;
the input end of the third NOT gate is connected to the precharge circuit through a pin PRCHG;
The input end of the first NOR gate is connected with the output end of the inverter;
the input end of the inverter is connected with the drain electrode of the seventh MOS tube, and the input end of the inverter is also connected with the virtual memory bank.
6. The SRAM structure with reliability and stability of claim 5, wherein said control signal generation module comprises: the second NOR gate, the second delay device, the first driver, the fourth NOT gate, the third delay device, the second driver, the third AND gate, the OR gate and the fifth NOT gate;
The input end of the second NOR gate, the input end of the second delay device, the input end of the fourth NOR gate and the input end of the first driver are all connected with the output end of the second NOR gate;
The output end of the second NOR gate is connected with the input end of the second driver, and the input end of the second NOR gate is also connected with the output end of the third delayer;
the output end of the first driver controls the on or off of the word line of the real memory bank through a pin WLCLK;
the output end of the second driver is connected to the precharge circuit through the pin PRCHG;
the output end of the second delayer is connected with the input end of the third delayer and the input end of the third AND gate;
The input end of the third AND gate is connected with the output end of the fourth NOT gate and the input end of the OR gate, and the output end of the third AND gate is connected with the input end of the fifth NOT gate;
The output end of the fifth NOT gate is connected with the read-write circuit through a pin RDP;
the output end of the OR gate is connected with the read-write circuit through a pin WEP_n.
7. The SRAM structure of claim 1, further comprising a plurality of PD pipes disposed at adjacent peripheries of the real memory bank, wherein the virtual memory bank is located between a portion of the PD pipes and the real memory bank.
8. An SRAM self-timing control method, employing an SRAM structure with reliability and stability according to any one of claims 1-7, comprising in particular:
Starting word lines, discharging bit lines and complementary bit lines of the virtual memory bank, and generating voltage differences between the bit lines and the complementary bit lines of the real memory bank;
and when the voltage difference reaches a data reading set value, closing word lines according to the overturning voltage generated by discharging, and reading data, wherein the bit lines and complementary bit lines of the virtual memory bank stop discharging, and the duration of the opening of the word lines is related to the number of the virtual memory bank.
9. The SRAM self-timing control method of claim 8, further comprising, prior to said turning on a wordline:
precharging bit lines and complementary bit lines of the virtual memory bank to a high voltage;
selecting a data bit of data to be read out, opening a word line, waiting for the bit line and the complementary bit line of the real memory bank to form a voltage difference, and discharging the bit line and the complementary bit line of the virtual memory bank at the same time;
if the voltage difference reaches a set value for reading data of a sense amplifier in a read-write circuit, the discharge reaches a turnover voltage to close a word line, and the sense amplifier is started to read the data;
If the differential pressure does not reach the data reading set value of the sensitive amplifier, returning to the previous step;
after the data to be read is read, the sense amplifier is turned off, and the read operation is ended.
10. The SRAM self-timing control method of claim 9, wherein the duration of wordline on is related to the number of dummy banks, comprising:
Assuming that the flip voltage for word line off is Vtrig, the number of virtual banks is N, the duration of word line on is: tdis= Cdbl ×vtrig/(n×i Cell,dum), where I Cell,dum represents the discharge current of the virtual memory bank, cdbl represents the parasitic capacitance of the bit line of the virtual memory bank, vtrig=vdd/x, VDD represents the power supply voltage, x is a positive number;
At Tdis time, the differential voltage generated by the bit line and the complementary bit line of the real memory bank is: Δvbl=i Cell,norm×Tdis/Cbl=[ICell,norm×Cdbl×Vtrig/（N×ICell,dum) ]/cbl≡vtrig/n=vdd/xN; where I Cell,norm denotes the discharge current of the real bank, cbl denotes the parasitic capacitance of the bit line of the real bank, cbl≡ Cdbl.
11. The SRAM self-timing control method of claim 10, wherein said sense amplifier data read setpoint is a multiple of its design offset.
12. The SRAM self-timing control method of claim 8, further comprising:
precharging bit lines and complementary bit lines of the virtual memory bank to a high voltage;
selecting a data bit to be written with data, and opening a word line;
Writing data, and returning to the previous step if the data writing fails;
after the data to be written is written, the word line is turned off, ending the writing operation.
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